Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate, the substrate having a first surface and a second surface arranged oppositely, and a transistor arranged on the second surface; forming a release hole in the substrate, the release hole extending into the transistor, and a bottom of the release hole being located in a channel region of the transistor, and a top surface of the release hole being flush with the first surface; and forming a conductive structure in the release hole, the conductive structure extending out of the release hole and covering the first surface above the substrate. The present disclosure forms a conductive structure in the substrate which is in communication with the channel region of the transistor, and transmits holes in the transistor to outside of the substrate, thereby avoiding the generation of floating gate effect between the substrate and the transistor, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) offers small size, high integration, low power consumption, and is faster than all other Read Only Memory (ROM) devices. However, as integration increases, the characteristic size and plate area of ​​capacitors continue to decrease, necessitating the use of thinner and / or higher-k dielectric materials to increase capacitance density. With the advancement of the semiconductor industry, the critical dimensions of devices like DRAM continue to shrink.

[0003] However, as the critical dimensions of devices continue to decrease, a floating gate effect will occur between the transistor and the substrate. The reason for this problem is that when the transistor is in the off state, some of the charge in the capacitor structure will move into the transistor through the capacitor contact structure and capacitor pad, causing an increase in the number of holes in the transistor, thereby increasing the voltage in the transistor and forming a voltage difference between the transistor and the substrate, thereby generating a floating gate effect, which can affect the performance of the semiconductor structure. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0006] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate having a first surface and a second surface opposite to each other, wherein a transistor is disposed on the second surface;

[0008] forming a release hole in the substrate, wherein the release hole extends into the transistor, a bottom of the release hole is located in the channel region of the transistor, and a top surface of the release hole is flush with the first surface;

[0009] A conductive structure is formed in the release hole, and the conductive structure extends out of the release hole and covers the first surface above the substrate.

[0010] According to some embodiments of the present disclosure, the step of providing a substrate includes:

[0011] Providing an initial substrate having a first initial surface and a second initial surface disposed opposite to each other;

[0012] Part of the thickness of the initial substrate is removed along a direction perpendicular to the first initial surface pointing to the second surface, and the surface of the remaining initial substrate forms the first surface, and the remaining initial substrate forms the substrate.

[0013] According to some embodiments of the present disclosure, the step of removing a portion of the initial substrate along the first initial surface includes:

[0014] The first initial surface is planarized by a chemical mechanical polishing process, and a portion of the thickness of the initial substrate is removed.

[0015] According to some embodiments of the present disclosure, the step of forming a release hole in the substrate includes:

[0016] forming a mask layer on the first surface;

[0017] forming a photoresist layer on the mask layer, and patterning the photoresist layer to form a mask pattern in the photoresist layer, wherein the mask pattern includes a plurality of first openings and protrusions for separating the first openings, wherein projections of the first openings on the transistor are located within the source of the transistor;

[0018] The mask layer, the substrate, the source of the transistor, and a portion of the channel region of the transistor exposed in the first opening are removed to form a release hole.

[0019] According to some embodiments of the present disclosure, the step of removing the mask layer, the substrate, the source of the transistor, and a portion of the channel region of the transistor exposed in the first opening to form a release hole includes:

[0020] forming an oxide layer on the sidewalls of the first opening, wherein the oxide layer extends outside the first opening and covers the top surface of the mask layer, and the oxide layer located within the first opening encloses a second opening;

[0021] The mask layer, the substrate, the source of the transistor, and a portion of the channel region of the transistor exposed in the second opening are removed to form the release hole.

[0022] According to some embodiments of the present disclosure, before the step of forming a mask layer on the first surface, the manufacturing method includes:

[0023] A first dielectric layer is formed on the first surface.

[0024] According to some embodiments of the present disclosure, the step of forming a mask layer on the first surface includes:

[0025] A first mask layer and a second mask layer are sequentially stacked on the first dielectric layer, and the first mask layer and the second mask layer are made of different materials.

[0026] According to some embodiments of the present disclosure, the step of forming a conductive structure in the release hole includes:

[0027] forming a second initial dielectric layer in the release hole, wherein the second initial dielectric layer extends out of the release hole and covers the first dielectric layer;

[0028] removing the second initial dielectric layer on the first dielectric layer and the second initial dielectric layer on the bottom of the release hole, so that the remaining second initial dielectric layer constitutes a second dielectric layer, and the second dielectric layer forms a middle hole in the release hole;

[0029] A conductive structure is formed in the middle hole, and the conductive structure extends out of the middle hole and covers the first dielectric layer.

[0030] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0031] A substrate having a first surface and a second surface opposite to each other, wherein a plurality of transistors are disposed on the second surface and arranged in an array;

[0032] A conductive structure comprising a conductive body and a plurality of conductive protrusions provided on the conductive body, wherein the conductive body is provided on the first surface, the plurality of conductive protrusions are provided in a one-to-one correspondence with the plurality of transistors, and the end of the conductive protrusion facing away from the conductive body passes through the substrate and the source of the transistor and is connected to the channel region of the transistor.

[0033] According to some embodiments of the present disclosure, the material of the conductive body and the material of the conductive protrusion both include one of copper, aluminum, or tungsten.

[0034] According to some embodiments of the present disclosure, a plurality of bit line structures arranged along the row direction of the transistors are provided in the substrate, the top surfaces of the bit line structures are located on the second surface, and the sources of the transistors are connected to the bit line structures.

[0035] According to some embodiments of the present disclosure, a plurality of word lines arranged along a column direction of the transistors are formed on the substrate, and the word lines are used to connect channel regions of a plurality of the transistors.

[0036] According to some embodiments of the present disclosure, a capacitor contact structure is connected to the drain of the transistor, and a capacitor structure is connected to the capacitor contact structure.

[0037] According to some embodiments of the present disclosure, the capacitor contact structure includes a first contact structure and a second contact structure that are adhesively connected, wherein one end of the first contact structure facing away from the second contact structure is connected to the drain of the transistor, and the end of the second contact structure facing away from the first contact structure is connected to the capacitor structure.

[0038] According to some embodiments of the present disclosure, the first contact structure has a first surface and a second surface arranged opposite to each other, and the second contact structure has a third surface and a fourth surface arranged opposite to each other, wherein the second surface is connected to the drain of the transistor, the first surface is connected to the third surface, and the fourth surface is connected to the capacitor structure, wherein the projected area of ​​the first surface on the substrate is larger than the projected area of ​​the third surface on the substrate.

[0039] In the semiconductor structure manufacturing method and semiconductor structure provided by the embodiments of the present disclosure, a conductive structure is formed in the substrate, and one end of the conductive structure is connected to the transistor. When there are excess holes in the transistor, the conductive structure can be used to transfer the holes to the outside of the substrate, thereby avoiding the floating gate effect between the substrate and the transistor, thereby improving the performance of the semiconductor structure.

[0040] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. For those of ordinary skill in the art, other drawings can be derived from these drawings without inventive effort.

[0042] Figure 1 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0043] Figure 2 It is a schematic diagram of forming a substrate and a transistor in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0044] Figure 3 FIG. 1 is a schematic diagram of forming a first opening in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0045] Figure 4 FIG. 1 is a schematic diagram of forming an initial oxide layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0046] Figure 5 FIG. 1 is a schematic diagram of forming an oxide layer and a second opening in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0047] Figure 6 FIG. 1 is a schematic diagram of forming a release hole in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0048] Figure 7 FIG. 1 is a schematic diagram of forming a second initial dielectric layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0049] Figure 8 It is a schematic diagram of forming a second dielectric layer and a middle hole in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0050] Figure 9 It is a schematic diagram of forming a conductive structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, and a schematic diagram of a semiconductor structure.

[0051] Reference numerals:

[0052] 10. Base; 11. Initial base;

[0053] 20. Transistor; 21. Source;

[0054] 22. Channel region; 23. Drain;

[0055] 30. Isolation structure; 31. Air gap layer;

[0056] 40. Word line; 50. Bit line structure;

[0057] 60. First dielectric layer; 70. Mask layer;

[0058] 71. First mask layer; 72. Second mask layer;

[0059] 80. Photoresist layer; 81. First opening;

[0060] 82. protrusion; 83. second opening;

[0061] 90, release hole; 100, oxide layer;

[0062] 110, initial oxide layer; 130, second dielectric layer;

[0063] 131, second initial dielectric layer; 140, middle hole;

[0064] 150. Conductive structure; 151. Conductive body;

[0065] 152. Conductive protrusion; 160. Capacitive contact structure;

[0066] 161. First contact structure; 162. Second contact structure;

[0067] 1611, first paragraph; 1612, second paragraph;

[0068] 1621, third paragraph; 1622, fourth paragraph;

[0069] 170. Capacitor structure; 171. Upper electrode;

[0070] 172. dielectric layer; 173. lower electrode;

[0071] 180. Capacitor pad. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0073] A floating gate effect will occur between the transistor and the substrate in the related technology, and the floating gate effect will affect the performance of the semiconductor structure. The inventors have found that the reason for this problem is that when the transistor is in the off state, part of the charge in the capacitor structure will move into the transistor through the capacitor contact structure and the connection pad, causing the number of holes in the transistor to increase, thereby increasing the voltage in the transistor, and then forming a voltage difference between the transistor and the substrate to produce a floating gate effect.

[0074] In response to the above-mentioned technical problems, in the semiconductor structure manufacturing method and semiconductor structure provided by the embodiments of the present disclosure, a conductive structure is formed in the substrate, one end of the conductive structure is connected to the transistor. When there are excess holes in the transistor, the conductive structure can be used to transfer the holes to the outside of the substrate, thereby avoiding the floating gate effect between the substrate and the transistor, thereby improving the performance of the semiconductor structure.

[0075] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 1 As shown, Figure 1 A flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figure 2-Figure 9 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 2-Figure 9 The fabrication method of semiconductor structures is introduced.

[0076] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0077] like Figure 1 As shown, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0078] Step S100: providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other, and a transistor is disposed on the second surface.

[0079] For example, Figure 2 and Figure 9 As shown, the substrate 10 serves as a supporting component of the dynamic random access memory, and is used to support other components arranged thereon. The substrate 10 can be made of a semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0080] Along the direction perpendicular to the substrate 10, that is, the Y direction shown in the figure, the substrate 10 has a first surface 101 and a second surface 102 arranged opposite to each other, wherein the first surface 101 can be understood as the upper surface of the substrate 10, and the second surface 102 can be understood as the lower surface of the substrate 10.

[0081] For example, Figure 2 As shown, an initial substrate 11 is provided, and the initial substrate 11 has a first initial surface 111 and a second initial surface 102 disposed opposite to each other;

[0082] Along the vertical direction from the first initial surface 111 to the second surface 102 , a portion of the thickness of the initial substrate 11 is removed, and the surface of the remaining initial substrate 11 forms the first surface 101 , and the remaining initial substrate 11 forms the substrate 10 .

[0083] That is, the first initial surface 111 can be planarized using a chemical mechanical polishing process to remove a portion of the thickness of the initial substrate 11 . The remaining initial substrate 11 constitutes the substrate 10 , and the planarized first initial surface 111 constitutes the first surface 101 .

[0084] In this embodiment, a transistor 20 is further provided on the second surface 102. For example, an isolation structure 30 can be formed on the second surface by a deposition process, and then the isolation structure 30 is patterned to form a plurality of trenches in the isolation structure 30. The plurality of trenches are along a first direction, that is, Figure 2The trenches are spaced apart in the X direction as shown in FIG. 5 , and then a bit line structure 50 is formed in each trench. Then, a plurality of active pillars arranged in an array are formed on the bit line structure 50 .

[0085] After the active pillars are formed, word lines 40 extending along the first direction are formed on the isolation structure 30 . Part of the word lines 40 wrap around the channel regions 22 of the active pillars. Each active pillar and the word lines 40 wrapped around the active pillars constitute a transistor 20 .

[0086] An air gap layer 31 is also formed in the isolation structure 30 .

[0087] Step S200 : forming a release hole in the substrate, wherein the release hole extends into the transistor, and the bottom of the release hole is located in the channel region of the transistor, and the top surface of the release hole is flush with the first surface.

[0088] For example, Figure 3 As shown, a mask layer 70 is formed on the first surface 101 . The mask layer 70 may be formed on the first surface 101 by using a deposition process.

[0089] It should be noted that, in this embodiment, the mask layer 70 can be a single film layer or a stacked structure. When the mask layer 70 includes a stacked structure, the mask layer can include a first mask layer 71 and a second mask layer 72 that are stacked. The first mask layer 71 is arranged on the first dielectric layer 60, and the first dielectric layer 60 may include a silicon oxide layer, wherein the material of the first mask layer 71 and the material of the second mask layer 72 are different. For example, the material of the first mask layer 71 may include amorphous carbon, and the material of the second mask layer 72 may include silicon oxynitride.

[0090] After the mask layer 70 is formed, a photoresist layer 80 can be formed on the mask layer 70 by coating, and then the photoresist layer is patterned by exposure, development or etching to form a mask pattern in the photoresist layer 80, wherein the mask pattern includes a plurality of first openings 81 and protrusions 82 for separating each first opening 81, the number of the first openings 81 corresponds one-to-one to the number of transistors 20, and the projection of the first opening 81 on the transistor 20 is located in the source 21 of the transistor 20.

[0091] like Figure 5 As shown, an oxide layer 100 is formed on the sidewall of the first opening 81. The oxide layer 100 extends outside the first opening 81 and covers the top surface of the mask layer 70. The oxide layer 100 located in the first opening 81 surrounds the second opening 83, wherein the oxide layer 100 can be a silicon oxide layer.

[0092] For example, Figure 4As shown, an initial oxide layer 110 may be formed on the sidewalls and bottom wall of the first opening 81 by an atomic layer deposition process. The initial oxide layer 110 extends outside the first opening 81 and covers the top surface of the mask layer 70 .

[0093] Then, the initial oxide layer 110 located on the bottom wall of the second opening 83 is removed by etching gas or etching liquid, and the retained initial oxide layer 110 forms an oxide layer 100, that is, the formed oxide layer 100 covers the top surface and side wall of the protrusion 82, wherein the oxide layer 100 located in the first opening 81 surrounds the second opening 83.

[0094] In this embodiment, the oxide layer 100 is provided to reduce the diameter of the first opening 81 , thereby reducing the diameter of the release hole 90 , thereby reducing excessive damage to the transistor 20 by the release hole 90 and ensuring the performance of the transistor 20 .

[0095] Finally, the mask layer 70, the substrate 10, the source 21 of the transistor 20 and a portion of the channel region 22 of the transistor 20 exposed in the second opening 83 are removed by etching liquid or etching gas to form a release hole 90. Figure 6 shown.

[0096] It should be noted that, in this embodiment, a portion of the release hole 90 is located in the transistor 20, and the other portion is located in the substrate 10; in addition, in some embodiments, after the release hole 90 is formed, it is necessary to use dry or wet etching to remove the photoresist layer 80, the mask layer 70 and the oxide layer 100.

[0097] In this embodiment, the mask layer 70 is a stacked structure. During the pattern transfer process, the mask pattern formed by the protrusion 82 covered with the oxide layer 100 can be used as a mask to etch the second mask layer 72 to form a second mask layer 72 with a pattern. Then, the second mask layer 72 with a pattern is used as a mask to continue etching the first mask layer 71, the substrate 10 and the transistor 20 to form a release hole 90.

[0098] This embodiment uses multiple pattern transfer processes to ensure the accuracy of the pattern finally transferred to the substrate 10 and the transistor 20 , thereby improving the precision of the release hole 90 .

[0099] In some embodiments, after providing the substrate 10 and before forming the mask layer 70 on the first surface 101 , the method for manufacturing the semiconductor structure further includes forming a first dielectric layer 60 on the first surface 101 , that is, the first dielectric layer 60 is disposed between the first surface 101 and the mask layer 70 .

[0100] In this embodiment, the first dielectric layer 60 is provided on the first surface 101 to protect the substrate 10 , thereby reducing lateral etching of the substrate 10 when forming the release hole 90 , thereby improving the performance of the semiconductor structure.

[0101] Step S300 : forming a conductive structure in the release hole, wherein the conductive structure extends out of the release hole and covers the first surface above the substrate.

[0102] For example, Figure 7 As shown, first, the second initial dielectric layer 131 is formed in the release hole 90 by using an atomic layer deposition process. The second initial dielectric layer 131 extends to the outside of the release hole 90 and covers the first dielectric layer 60 .

[0103] Then, the second initial dielectric layer 131 located on the first dielectric layer 60 and the second initial dielectric layer 131 located at the bottom of the release hole 90 is removed by etching liquid or etching gas. The remaining second initial dielectric layer 131 forms the second dielectric layer 130. The second dielectric layer 130 forms the middle hole 140 in the release hole 90. Figure 8 shown.

[0104] like Figure 9 As shown, a conductive structure 150 is formed in the middle hole by a deposition process. The conductive structure 150 extends outside the middle hole 140 and covers the first dielectric layer 60. The conductive structure 150 may be made of conductive materials such as copper, aluminum or tungsten.

[0105] It should be noted that, in this embodiment, the deposition process may include an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process.

[0106] In the semiconductor structure manufacturing method and semiconductor structure provided by the embodiments of the present disclosure, a conductive structure is formed in the substrate, and one end of the conductive structure is connected to the transistor. When there are excess holes in the transistor, the conductive structure can be used to transfer the holes to the outside of the substrate, thereby avoiding the floating gate effect between the substrate and the transistor, thereby improving the performance of the semiconductor structure.

[0107] like Figure 9 As shown, the embodiment of the present disclosure further provides a semiconductor structure, including:

[0108] The substrate 10 has a first surface 101 and a second surface 102 opposite to each other. A plurality of transistors 20 are disposed on the second surface 102 . The plurality of transistors 20 are arranged in an array.

[0109] The conductive structure 150 includes a conductive body 151 and a plurality of conductive protrusions 152 provided on the conductive body 151. The conductive body 151 is provided on the first surface 101. The plurality of conductive protrusions 152 are provided in a one-to-one correspondence with the plurality of transistors 20. The end of the conductive protrusion 152 facing away from the conductive body 151 passes through the substrate 10 and the source 21 of the transistor 20 and is connected to the channel region 22 of the transistor 20.

[0110] The material of the conductive body 151 and the material of the conductive protrusion 152 are both metal materials. For example, the material of the conductive body 151 and the conductive protrusion 152 may include copper, aluminum or tungsten.

[0111] In the semiconductor structure provided by the embodiment of the present disclosure, a conductive structure is formed in the substrate, and one end of the conductive structure is connected to the channel region of the transistor. When there are excess holes in the transistor, the conductive structure can be used to transfer the holes to the outside of the substrate, thereby avoiding the floating gate effect between the substrate and the transistor, thereby improving the performance of the semiconductor structure.

[0112] In some embodiments, the semiconductor structure further includes a first dielectric layer 60 , which is disposed between the first surface 101 and the conductive body 151 , and an end of the conductive protrusion 152 facing away from the conductive body 151 passes through the first dielectric layer 60 and is connected to the channel region 22 of the transistor 20 , wherein the material of the first dielectric layer 60 may include silicon oxide.

[0113] In this embodiment, the first dielectric layer 60 is provided to prevent the conductive body 151 from being electrically connected to other devices disposed in the substrate 10 , thereby ensuring normal use of the semiconductor structure.

[0114] In some embodiments, the semiconductor structure further includes a second dielectric layer 130 . The second dielectric layer 130 is disposed on the surface of the conductive protrusion 152 . The material of the second dielectric layer 130 may include silicon nitride.

[0115] In this embodiment, the second dielectric layer 130 is provided to prevent the conductive protrusion 152 from being electrically connected to the drain 23 of the transistor 20 or other devices provided in the substrate 10 , thereby ensuring the performance of the semiconductor structure.

[0116] In some embodiments, a plurality of bit line structures 50 are disposed in the substrate 10 and arranged along the row direction of the transistors 20 . The top surfaces of the bit line structures 50 are located on the second surface 102 , and the sources 21 of the transistors 20 are connected to the bit line structures 50 .

[0117] It should be noted that, in this embodiment, the row direction of the transistors 20 may be the X direction shown in the figure.

[0118] The plurality of bit line structures 50 may be spaced apart along the row direction of the transistors 20 , and the bit line structures 50 may extend along the column direction of the transistors 20 , that is, the bit line structures 50 may extend perpendicular to the X direction.

[0119] In some embodiments, a plurality of word lines 40 arranged along a column direction of the transistors 20 are formed on the substrate 10 . The word lines 40 are used to connect the channel regions 22 of the plurality of transistors 20 .

[0120] A third dielectric layer and an isolation layer are stacked on the word line 40 , and the third dielectric layer abuts against the word line 40 . The third dielectric layer includes a silicon oxide layer, and the isolation layer includes a silicon nitride layer.

[0121] In some embodiments, the drain 23 of the transistor 20 is connected to a capacitor contact structure 160 , and the capacitor contact structure 160 is connected to a capacitor structure 170 , wherein the capacitor structure 170 includes an upper electrode 171 , a dielectric layer 172 and a lower electrode 173 , and a capacitor pad 180 may be connected to the lower electrode 173 .

[0122] It should be noted that the capacitor structure 170 and the capacitor contact structure 160 are further provided with multiple layers of support layers and third dielectric layers that are alternately arranged in sequence.

[0123] Exemplarily, the capacitor contact structure 160 includes a first contact structure 161 and a second contact structure 162 that are adhesively connected, wherein one end of the first contact structure 161 facing away from the second contact structure 162 is connected to the drain 23 of the transistor 20 , and the other end of the second contact structure 162 facing away from the first contact structure 161 is connected to the capacitor structure 170 .

[0124] This embodiment realizes the connection between the capacitor structure and the drain of the transistor through a capacitor contact structure. In actual application, when data needs to be written to the capacitor structure, a voltage is applied to the word line, which opens the channel region of the transistor, so that the source and drain of the transistor are connected. At this time, the data on the word line is transmitted to the drain through the source, and then transmitted to the capacitor structure through the capacitor contact structure for data storage.

[0125] In this embodiment, the first contact structure 161 may be in a regular shape, such as a rectangle or a cylinder, or in an irregular shape.

[0126] Exemplarily, the first contact structure 161 includes a first segment 1611 and a second segment 1612 connected to the first segment 1611 . An end of the first segment 1611 facing away from the second segment 1612 is connected to the drain 23 , and an end of the second segment 1612 facing away from the first segment 1611 is connected to the second contact structure 162 .

[0127] Taking the plane perpendicular to the substrate 10 as the longitudinal section, the longitudinal section of the first section 1611 is a rectangle, and the longitudinal section of the second section 1612 is a trapezoid with a smaller top and a larger bottom. This can increase the area of ​​the first contact structure 161, thereby reducing the resistance of the first contact structure 161 and improving the sensitivity of signal transmission.

[0128] The second contact structure 162 includes a third segment 1621 and a fourth segment 1622 connected to the third segment 1621 . An end of the third segment 1621 facing away from the fourth segment 1622 is connected to the first contact structure 161 . An end of the fourth segment 1622 facing away from the third segment 1621 is connected to one end of the capacitor structure 170 .

[0129] Taking the plane perpendicular to the substrate 10 as the longitudinal section, the longitudinal section of the third section 1621 is a trapezoid with a larger top and a smaller bottom, and the longitudinal section of the fourth section 1622 is a rectangle. This can increase the contact area between the second contact structure 162 and the first contact structure 161, thereby reducing the contact resistance and improving the sensitivity of signal transmission.

[0130] In some embodiments, the first contact structure 161 has a first surface and a second surface disposed oppositely to each other, i.e., the first surface constitutes one end of the first segment 1611, and the second segment constitutes an end of the second segment 1612 facing away from the first segment 1611. The second contact structure 162 has a third surface and a fourth surface disposed oppositely to each other, i.e., the third surface constitutes one end of the third segment 1621, and the fourth surface constitutes an end of the fourth segment 1622 facing away from the third segment 1621. The second surface is connected to the drain 23 of the transistor 20, the first surface is connected to the third surface, and the fourth surface is connected to the capacitor structure 170. The projected area of ​​the first surface on the substrate 10 is larger than the projected area of ​​the third surface on the substrate 10, which facilitates alignment of the first contact structure 161 and the second contact structure 162.

[0131] In the semiconductor structure provided by the embodiment of the present disclosure, a conductive structure is formed in the substrate, and one end of the conductive structure is connected to the channel region of the transistor. When there are excess holes in the transistor, the conductive structure can be used to transfer the holes to the outside of the substrate, thereby avoiding the floating gate effect between the substrate and the transistor, thereby improving the performance of the semiconductor structure.

[0132] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0133] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0134] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0135] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0136] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0137] In one or more of the accompanying drawings, identical elements are represented by similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be described in a single figure. Many specific details of the present disclosure, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be practiced without following these specific details.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: Providing a substrate, the substrate having a first surface and a second surface opposite to each other, wherein a transistor is disposed on the second surface; forming a release hole in the substrate, wherein the release hole extends into the transistor, a bottom of the release hole is located in the channel region of the transistor, and a top surface of the release hole is flush with the first surface; forming a conductive structure in the release hole, wherein the conductive structure extends out of the release hole and covers the first surface above the substrate; The step of forming a release hole in the substrate includes: forming a mask layer on the first surface; forming a photoresist layer on the mask layer, and patterning the photoresist layer to form a mask pattern in the photoresist layer, wherein the mask pattern includes a plurality of first openings and protrusions for separating the first openings, wherein projections of the first openings on the transistor are located within the source of the transistor; removing the mask layer, the substrate, the source of the transistor, and a portion of the channel region of the transistor exposed in the first opening to form a release hole; The step of removing the mask layer, the substrate, the source of the transistor, and a portion of the channel region of the transistor exposed in the first opening to form a release hole includes: forming an oxide layer on the sidewalls of the first opening, wherein the oxide layer extends outside the first opening and covers the top surface of the mask layer, and the oxide layer located within the first opening encloses a second opening; The mask layer, the substrate, the source of the transistor, and a portion of the channel region of the transistor exposed in the second opening are removed to form the release hole.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of providing a substrate comprises: Providing an initial substrate having a first initial surface and a second initial surface disposed opposite to each other; Part of the thickness of the initial substrate is removed along a direction perpendicular to the first initial surface pointing to the second surface, and the surface of the remaining initial substrate forms the first surface, and the remaining initial substrate forms the substrate.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The step of removing a portion of the initial substrate along the first initial surface includes: The first initial surface is planarized by a chemical mechanical polishing process, and a portion of the thickness of the initial substrate is removed.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before the step of forming a mask layer on the first surface, the manufacturing method includes: A first dielectric layer is formed on the first surface.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: The step of forming a mask layer on the first surface includes: A first mask layer and a second mask layer are sequentially stacked on the first dielectric layer, and the first mask layer and the second mask layer are made of different materials.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The step of forming a conductive structure in the release hole comprises: forming a second initial dielectric layer in the release hole, wherein the second initial dielectric layer extends out of the release hole and covers the first dielectric layer; removing the second initial dielectric layer on the first dielectric layer and the second initial dielectric layer on the bottom of the release hole, so that the remaining second initial dielectric layer constitutes a second dielectric layer, and the second dielectric layer forms a middle hole in the release hole; A conductive structure is formed in the middle hole, and the conductive structure extends out of the middle hole and covers the first dielectric layer.

7. A semiconductor structure, characterized in that The semiconductor structure comprises: A substrate having a first surface and a second surface opposite to each other, wherein a plurality of transistors are disposed on the second surface and arranged in an array; a conductive structure comprising a conductive body and a plurality of conductive protrusions disposed on the conductive body, wherein the conductive body is disposed on the first surface, the plurality of conductive protrusions are disposed in a one-to-one correspondence with the plurality of transistors, and an end of the conductive protrusion facing away from the conductive body passes through the substrate and the source of the transistor and is connected to the channel region of the transistor; A plurality of bit line structures arranged along the row direction of the transistors are provided in the substrate, the top surfaces of the bit line structures are located on the second surface, and the sources of the transistors are connected to the bit line structures.

8. The semiconductor structure according to claim 7, wherein: The material of the conductive body and the material of the conductive protrusion both include one of copper, aluminum or tungsten.

9. The semiconductor structure according to claim 7, wherein: A plurality of word lines arranged along the direction of the transistor columns are formed on the substrate, and the word lines are used to connect the channel regions of the plurality of transistors.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: The drain of the transistor is connected to a capacitor contact structure, and the capacitor contact structure is connected to a capacitor structure.

11. The semiconductor structure according to claim 10, wherein: The capacitor contact structure includes a first contact structure and a second contact structure bonded together. One end of the first contact structure facing away from the second contact structure is connected to the drain of the transistor. One end of the second contact structure facing away from the first contact structure is connected to the capacitor structure.

12. The semiconductor structure according to claim 11, wherein: The first contact structure has a first surface and a second surface arranged opposite to each other, and the second contact structure has a third surface and a fourth surface arranged opposite to each other, wherein the second surface is connected to the drain of the transistor, the first surface is connected to the third surface, and the fourth surface is connected to the capacitor structure, wherein the projected area of ​​the first surface on the substrate is larger than the projected area of ​​the third surface on the substrate.

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