A manufacturing process of a flash memory cell array and a flash memory cell array

Abstract

The application discloses a preparation process of a flash memory cell array and the flash memory cell array. The process comprises the following steps: arranging a strip pre-mapping on a substrate; the strip pre-mapping comprises a source region and a drain region; forming a vertically-stacked control gate and a floating gate on both sides of the source region, and implanting ions into the source region; forming an erase gate between adjacent vertically-stacked gates in a second direction; forming a selection gate on the side of the vertically-stacked gate away from the source region; the erase gates of adjacent flash memory cells are discontinuous on the source region in a first direction; arranging a photoresist layer on the source region in the first direction, the photoresist layer covers the source region and the erase gate, and the ion doping of the area covered by the erase gate and the area not covered by the erase gate of the source region is the same. The technical scheme provided by the application can keep the breakdown voltage of the source region, reduce the leakage, reduce the power consumption of the source programming voltage pump, reduce the generation of channel holes, and improve the reliability of the device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor memory devices, and particularly relate to a flash memory cell array and a preparation process thereof. BACKGROUND

[0002] A semiconductor device array composed of a plurality of semiconductor devices can realize analog signal conversion and vector matrix arithmetic calculation, and is therefore widely used in the fields of artificial intelligence, data processing, model calculation, etc.

[0003] In the existing semiconductor device array process, the preparation process still has deficiencies, thereby affecting the working performance of the flash memory device, especially when programming in the source end injection mode, the breakdown voltage of the source electrode is low, which easily causes large leakage current and reduces the device performance in the programming process. SUMMARY

[0004] The present application provides a preparation process of a flash memory cell array and a flash memory cell array, which realizes maintaining the breakdown voltage of the source electrode, reducing the leakage current, reducing the power consumption of the source electrode programming voltage pump, reducing the generation of channel holes, and improving the reliability of the device.

[0005] In a first aspect, the present application provides a preparation process of a flash memory cell array, comprising:

[0006] A strip pre-plot is arranged on a substrate by field oxidation or shallow trench isolation; wherein the strip pre-plot includes a source region and a drain region; the source region extends and distributes in the substrate along a first direction; the drain region and the source region form an active region in a second direction; the first direction intersects the second direction;

[0007] A vertical stacked gate is formed on both sides of the source region; the vertical stacked gate sequentially includes a control gate and a floating gate in the direction close to the substrate; ions are implanted into the source region in the substrate between the vertical stacked gates to form a source electrode;

[0008] An erase gate is formed between adjacent vertical stacked gates along the second direction; a select gate is formed on the side of the vertical stacked gate away from the source region; wherein the erase gates of adjacent flash memory cells are discontinuous on the source region along the first direction;

[0009] A photoresist layer is arranged on the source region along the first direction, covering the source region and the erase gate;

[0010] The flash memory cell array is subjected to ion implantation, and after the implantation is completed, the photoresist layer is removed, so that the ion doping of the area of the source region covered by the erase gate and the area not covered by the erase gate is the same.

[0011] Optionally, the photoresist layer has a thickness of 1000 angstroms to 2000 angstroms.

[0012] Optionally, the ion implantation process includes at least one of light doping implantation, Halo implantation, and P / N Plus implantation.

[0013] Optionally, after forming the vertically stacked gates on both sides of the source region, the method further comprises:

[0014] forming a polysilicon oxide on the sidewall of the vertically stacked gates to form a tunneling dielectric.

[0015] Optionally, the tunneling dielectric has a thickness of 100 angstroms to 150 angstroms.

[0016] Optionally, the tunneling dielectric includes silicon oxide.

[0017] In a second aspect, an embodiment of the present application provides a flash memory cell array, comprising: a substrate, a floating gate, a control gate, an erase gate, a select gate, a source region, and a drain region.

[0018] The source region extends along a first direction in the substrate; the floating gate and the control gate are arranged on both sides of the source region to form a vertically stacked gate.

[0019] The erase gate is between adjacent vertically stacked gates along a second direction; wherein the first direction intersects the second direction.

[0020] The select gate is on a side of the vertically stacked gate away from the source region; and the drain region is on a side of the select gate away from the source region.

[0021] The drain region and the source region form an active region in the second direction; the erase gate covers an overlapping region of the active region and the source region, wherein the erase gates of adjacent flash memory cells are discontinuous on the source region along the first direction; and the source region is ion-doped identically in a region covered by the erase gate and a region not covered by the erase gate.

[0022] Optionally, the flash memory cell array further comprises a tunneling dielectric, the tunneling dielectric being arranged on the sidewall of the vertically stacked gate adjacent to the erase gate and the select gate.

[0023] Optionally, the floating gate has a thickness of about 100 angstroms to 700 angstroms.

[0024] The technical scheme provided by the embodiment of the present application is characterized in that a photoresist layer is arranged on the source region in the first direction, the photoresist layer covers the source region and the erase gate, thereby preventing more N-type or P-type ions from being doped into the source region during ion implantation, and the photoresist layer is removed after the implantation, so that the ion doping of the area covered by the erase gate and the area not covered by the erase gate of the source region is the same. Therefore, the photoresist layer is used to keep the source region with the same ion doping, avoid the influence of other ions, so that in application, the source end implantation mode is used for programming, the breakdown voltage of the source region can be kept normal, the power consumption of the source programming voltage pump is reduced, the channel hole generation is reduced, and the influence of the channel hole on the reliability of the device is reduced. At the same time, since the photoresist layer also covers the erase gate region, it prevents different types of ions from being implanted into the erase gate region, and further improves the reliability of the device BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A flowchart of a preparation process of a flash memory cell array is provided for the embodiment of the present application.

[0026] Figures 2-5 A preparation process structure diagram under the AA section of the flash memory cell array is provided for the embodiment of the present application.

[0027] Figures 6-9 A preparation process structure diagram under the BB section of the flash memory cell array is provided for the embodiment of the present application.

[0028] Figure 10 A top view structure diagram of the flash memory cell array is provided for the embodiment of the present application.

[0029] Figure 11 A top view structure diagram of another flash memory cell array is provided.

[0030] Figure 12 A top view structure diagram of another flash memory cell array is provided. DETAILED DESCRIPTION

[0031] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0032] Figure 1 A flowchart of a preparation process of a flash memory cell array is provided for the embodiment of the present application, as shown in Figure 1 , Figures 2-5A preparation process structure schematic diagram under the AA section of the flash memory cell array is provided for the embodiment of the present application; Figures 6-9 A preparation process structure schematic diagram under the BB section of the flash memory cell array is provided for the embodiment of the present application; Figure 10 A top view structure schematic diagram of the flash memory cell array is provided for the embodiment of the present application, referring to Figures 1-10 The process flow comprises:

[0033] S110, a strip pre-mapping is arranged on the substrate by field oxidation or shallow trench isolation; wherein the strip pre-mapping comprises a source region 110 and a drain region 120; the source region 110 is distributed and extended in the substrate along a first direction x; the drain region 120 and the source region 110 form an active region in a second direction y; the first direction x intersects with the second direction y;

[0034] Specifically, taking the first direction x as the row direction and the second direction y as the column direction as an example, the source region 110 is distributed and extended in the row direction in a strip shape, and the drain region 120 forms a channel region, i.e. an active region 130, with the source region 110 in the column direction, wherein the active region 130 is parallel to the bit line. The structure formed in the AA section is as shown in Figure 2 , and the structure formed in the BB section is as shown in Figure 6 .

[0035] S120, a vertical stacked gate 140 is formed on both sides of the source region 110; the vertical stacked gate 140 is stacked by a control gate 141 and a floating gate 142 in the direction close to the substrate; ions are implanted into the source region in the substrate between the vertical stacked gates to form a source electrode;

[0036] Specifically, a first layer of polysilicon dielectric layer is formed on the substrate, which can be doped during the deposition of the polysilicon layer, a second layer of polysilicon dielectric layer is deposited, and then etched to form the control gate 141, and heavily doped with phosphorus, arsenic or boron ion materials. The control gate 141 pattern is defined in lithography, and after lithography, the unmasked part of the oxide or nitride layer can form a dielectric cap on the control gate 141. Illustratively, a relatively thin thermal oxide can be grown on the side edges of the control gate 141 to protect them from damage in subsequent processing. Thereafter, a dielectric film such as oxide or nitride is deposited on the wafer, and then anisotropically etched to remove the dielectric layer from the flat area, leaving a dielectric spacer on the side of the control gate 141. Wherein the dielectric spacer can be silicon nitride, the first layer of polysilicon dielectric layer and the second layer of polysilicon dielectric layer are anisotropically etched to form a plurality of separated vertical stacked gates 140, which are formed in the AA section as shown in Figure 3 , and the BB section as shown in Figure 7The structure is shown. The vertical stack gate 140 is a vertical stack of the control gate 141 and the floating gate 142. The source region 110 in the substrate between adjacent stack gate pairs is implanted with source ions to form a channel gate, i.e. the source.

[0037] S130, forming an erase gate 150 between adjacent vertical stack gates 140 in the second direction y; forming a select gate on the side of the vertical stack gate 140 away from the source region 110; wherein the erase gates 150 of adjacent flash memory cells are discontinuous on the source region 110 in the first direction x;

[0038] Specifically, a conductive layer is deposited on the entire flash memory cell wafer and is doped. The conductive layer is anisotropically etched to form the erase gate 150 and the select gate 160, wherein in the first direction x, adjacent flash memory cells are distinguished by discontinuous erase gates 150. The erase gate 150 covers at least the overlapping position of the source region 130 and the source region 110. This step forms a structure as shown in the AA cross-section Figure 4 as shown in the structure, the BB cross-section is as shown in Figure 8 as shown in the structure.

[0039] S140, disposing a photoresist layer 170 on the source region 110 in the first direction x, the photoresist layer 170 covering the source region 110 and the erase gate 150;

[0040] Specifically, referring to Figure 10 in the first direction x, the photoresist layer 170 is disposed between adjacent stack gate pairs, the photoresist layer 170 covering at least the source region 110, and the photoresist layer 170 being at least equal in thickness to the structure thickness of the stack gate, and the photoresist layer 170 is used to block the surface of the erase gate 150 and the surface of the source region 110. This step forms a structure as shown in the AA cross-section Figure 5 as shown in the structure, the BB cross-section is as shown in Figure 9 as shown in the structure.

[0041] S150, ion implantation is performed on the flash memory cell array, and after the ion implantation is completed, the photoresist layer 170 is removed, so that the ion doping of the region of the source region 110 covered by the erase gate 150 and the region not covered by the erase gate 150 is the same.

[0042] Specifically, drain ions are implanted into the drain region 120 in the substrate. Due to the presence of the photoresist layer 170, the photoresist layer 170 can be used to block ion implantation into the erase gate 150 and the source region 110, so that the doping ions in the covered region and the uncovered region of the source region 110 can be kept the same, and at the same time, the influence of at least one of the subsequent ion implantation processes, such as light doping implantation, Halo implantation, P / N Plus implantation, etc. on the source region 110 can be avoided. After the ion implantation process is completed, the photoresist layer 170 can be removed by etching.

[0043] The technical scheme provided by the embodiment of the present application is that a photoresist layer is arranged on the source region in the first direction, the photoresist layer covers the source region and the erase gate, thereby blocking more N-type or P-type ions from being doped into the source region in the ion implantation process, and the photoresist layer is removed after the ion implantation is completed, so that the ion doping of the area covered by the erase gate and the area not covered by the erase gate of the source region is the same. Therefore, the photoresist layer is used to keep the source region with the same ion doping, avoid the influence of other ions, so that in application, the source end implantation mode is used for programming, the breakdown voltage of the source region can be kept normal, the power consumption of the source programming voltage pump is reduced, the channel hole generation is reduced, and the influence of the channel hole on the reliability of the device is reduced. At the same time, since the photoresist layer also covers the erase gate region, it blocks different types of ions from being implanted into the erase gate region, and further improves the reliability of the device

[0044] For example, when the select gate 160 is arranged, the select gate 160 of the adjacent flash memory cell can also be discontinuous in the first direction x on the source region 110, so that the select gate 160 of the adjacent flash memory cell in the second direction y is physically disconnected, thereby being distinguished, Figure 11 FIG. 6 is a top view of another flash memory cell array structure, and Figure 11 The threshold voltage of the device can be adjusted by HCI programming, and the erase can adopt a tunneling effect, BTBT (band-to-band tunneling), etc., so that the erase gate 150 can no longer be arranged. Before ion implantation is performed on the flash memory cell array, the photoresist layer 170 is arranged between the adjacent stacked gate pairs, and the photoresist layer 170 covers the source region 110. Due to the presence of the photoresist layer 170, the ion implantation into the source region 110 can be blocked by the photoresist layer 170, so that the doping ions in the covered area and the uncovered area of the source region 110 can be kept the same. At the same time, the influence of the subsequent ion implantation process, such as light doping implantation, Halo implantation, P / N Plus implantation, etc., on the source region 110 can also be avoided. After the ion implantation process is completed, the photoresist layer 170 can be removed by etching.

[0045] When the source region 110 is arranged, the source region 110 of the adjacent flash memory cell can also be discontinuous in the first direction x, so that the source region 110 of the adjacent flash memory cell in the second direction y is physically disconnected, thereby being distinguished, Figure 12 FIG. 6 is a top view of another flash memory cell array structure, and Figure 12The flash memory cell can be set bias through the source, the control gate 141 and the drain, adjust the threshold voltage of the device through HCI programming writing, and the erase can adopt a tunneling effect, BTBT (band-to-band tunneling) and the like, so that the erase gate 150 can no longer be set. Before ion implantation is performed on the flash memory cell array, a photoresist layer 170 is arranged between adjacent stacked gate pairs, and the photoresist layer 170 covers the source region 110. Due to the presence of the photoresist layer 170, ion implantation into the source region 110 can be blocked by the photoresist layer 170, so that the doping ions in the covered area and the uncovered area of the source region 110 can be kept the same, and at the same time, the influence of the source region 110 on the subsequent ion implantation process, such as at least one of light doping implantation, Halo implantation, P / N Plus implantation and the like, can be avoided. After the ion implantation process is completed, the photoresist layer 170 can be removed by etching.

[0046] Optionally, the thickness of the photoresist layer 170 is between 1000 angstroms and 2000 angstroms.

[0047] Specifically, the vertical stacked gate 140 includes a control gate 141 and a floating gate 142, and the surface of the vertical stacked gate 140 is further provided with a dielectric layer, and the dielectric layer covers the control gate 141. The thickness of the photoresist layer 170 is at least the same as the thickness of the dielectric layer, and can also be greater than the dielectric layer, and part of the dielectric layer is covered, as shown in Figure 5 , so as to completely cover the source region 110 in the substrate and play a blocking and isolating role.

[0048] Optionally, the ion implantation process includes at least one of light doping implantation, Halo implantation, P / N Plus implantation. Specifically, due to the blocking of the photoresist layer 170, the source region 110 can avoid the influence of other ions when at least one of light doping implantation, Halo implantation, P / N Plus implantation is performed, thereby improving the performance of the device.

[0049] Optionally, after the vertical stacked gate 140 is formed on both sides of the source region 110, the method further includes: generating a polysilicon oxide on the sidewall of the vertical stacked gate 140 to form a tunneling dielectric 180.

[0050] Specifically, referring to Figure 3 and Figure 7A tunneling dielectric layer such as oxide or nitride is deposited on the wafer, and then anisotropically etched to remove the excess tunneling dielectric layer from the flat area, forming a layer of tunneling dielectric 180 on the side of the vertically stacked gate 140, improving the tunneling efficiency between the vertically stacked gate 140 and the erase gate 150 and the select gate 160. Exemplarily, the thickness of the tunneling dielectric is 100-150 angstroms. Optionally, the material of the tunneling dielectric can be silicon oxide and its combination.

[0051] In combination Figure 10 , see Figure 4 and Figure 8 , the embodiment of the present application also provides a flash memory cell array, comprising: a substrate, a floating gate 142, a control gate 141, an erase gate 150, a select gate 160, a source region 110 and a drain region 120;

[0052] The source region 110 extends along a first direction x in the substrate; the two sides of the source region 110 are respectively provided with the vertically stacked floating gate 142 and the control gate 141, forming the vertically stacked gate 140;

[0053] Along a second direction y, the erase gate 150 is between adjacent vertically stacked gates 140; wherein the first direction x intersects the second direction y;

[0054] The select gate 160 is on the side of the vertically stacked gate 140 away from the source region 110; the drain region 120 is on the side of the select gate 160 away from the source region 110;

[0055] The drain region 120 and the source region 110 form an active region 130 in the second direction y; the erase gate 150 covers the overlapping area of the active region 130 and the source region 110, wherein the erase gate 150 of adjacent flash memory cells is discontinuous on the source region 110 along the first direction x; the ion doping of the area of the source region 110 covered by the erase gate 150 and the area of the source region 110 not covered by the erase gate 150 is the same.

[0056] Specifically, adjacent flash memory cells in the second direction y share an erase gate 150, each flash memory cell has a vertically stacked gate 140, wherein the vertically stacked gate 140 includes a control gate 141 and a floating gate 142, the control gate 141 is located on the floating gate 142, and the thickness of the floating gate 142 is 100-700 angstroms, and each flash memory cell also has a select gate 160, the select gate 160 is located on one side of the vertically stacked gate 140. After depositing a polysilicon layer on the wafer, the select gate 160 and the erase gate 150 are formed simultaneously by anisotropic etching in a dry etching process. Wherein, the erase gate 150 is discontinuous along the first direction x on the source region 110, which distinguishes adjacent flash memory cells in the first direction x. Wherein, the ion doping of the area covered by the erase gate 150 and the area not covered by the erase gate 150 of the source region 110 is the same, so that the source end injection programming mode is adopted, so that the breakdown voltage of the source region 110 remains normal, reduces the leakage current, reduces the power consumption of the source programming voltage pump, reduces the generation of channel holes, and reduces the influence of channel holes on device reliability. At the same time, the ions of the erase gate 150 are not affected by other injected ions, which also increases the reliability of the device to some extent.

[0057] Optionally, the flash memory cell array further comprises: a tunneling dielectric, the tunneling dielectric is arranged on the side wall adjacent to the erase gate 150 and the select gate 160 of the vertically stacked gate 140, so as to improve the tunneling efficiency between the vertically stacked gate 140 and the erase gate 150 and the select gate 160.

[0058] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A process for fabricating an array of flash memory cells, comprising: Comprising: provisioning a strip pre-plot on a substrate by field oxidation or shallow trench isolation; wherein the strip pre-plot comprises a source region and a drain region; the source region is distributed along a first direction in the substrate; the drain region and the source region form an active region in a second direction; the first direction intersects the second direction; forming a vertical stack gate on both sides of the source region; the vertical stack gate is a stack of a control gate and a floating gate in order from a direction close to the substrate; forming an erase gate between adjacent vertical stack gates along the second direction; a select gate is formed on a side of the vertical stack gate away from the source region; wherein the erase gate of adjacent flash memory cells is discontinuous along the first direction on the source region, covering part of the source region; provisioning a photoresist layer on the source region along the first direction, the photoresist layer covering the area of the source region not covered by the erase gate and the erase gate; under the coverage of the photoresist layer, ion implantation is performed on the flash memory cell array, so that the ion doping of the area of the source region covered by the erase gate and the area of the source region not covered by the erase gate is the same, wherein the area of the source region not covered by the erase gate is located between the areas covered by the erase gate; after the ion implantation is completed, the photoresist layer is removed.

2. The fabrication process of a flash memory cell array according to claim 1, wherein, The thickness of the photoresist layer is between 1000 angstroms and 2000 angstroms.

3. The fabrication process of a flash memory cell array according to claim 1, wherein, The ion implantation implantation process includes at least one of light doping implantation, Halo implantation, P / N Plus implantation.

4. The fabrication process of a flash memory cell array according to claim 1, wherein, After forming a vertical stack gate on both sides of the source region, further comprising: forming a polysilicon oxide on the sidewall of the vertical stack gate to form a tunneling dielectric.

5. The fabrication process of a flash memory cell array according to claim 4, wherein, The thickness of the tunneling dielectric is 100 angstroms to 150 angstroms.

6. The fabrication process of a flash memory cell array according to claim 5, wherein, The tunneling dielectric includes silicon oxide.

7. An array of flash memory cells, comprising: Comprising: a substrate, a floating gate, a control gate, an erase gate, a select gate, a source region, and a drain region; the source region is distributed along a first direction in the substrate; the floating gate and the control gate are respectively provided on both sides of the source region to form a vertical stack gate; the erase gate is between adjacent vertical stack gates along a second direction; wherein the first direction intersects the second direction; the select gate is on a side of the vertical stack gate away from the source region; the drain region is on a side of the select gate away from the source region; the drain region and the source region form an active region in the second direction; the erase gate covers the overlapping area of the active region and the source region, wherein the erase gate of adjacent flash memory cells is discontinuous along the first direction on the source region, covering part of the source region; the ion doping of the area of the source region covered by the erase gate and the area of the source region not covered by the erase gate is the same, wherein the area of the source region not covered by the erase gate is located between the areas covered by the erase gate.

8. The flash memory cell array of claim 7, wherein, Further comprising: A tunneling dielectric is disposed on sidewalls of the vertical stack gate adjacent to the erase gate and the select gate, respectively.

9. The flash memory cell array of claim 7, wherein, The floating gate has a thickness of about 100-700 Angstroms.

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