Liquid crystal display panel, preparation method thereof and liquid crystal photo-alignment jig

Abstract

The application relates to a liquid crystal display panel and a preparation method thereof, and a liquid crystal photo-alignment jig. An array substrate of the display panel has a display area and a binding test area located at the periphery of the display area. The display area comprises a plurality of sub-pixels and a plurality of signal lines arranged in an array, and the binding test area comprises a plurality of test terminals arranged at intervals. The test terminals are electrically connected to the signal lines through metal traces. The counter substrate comprises a common electrode layer and a to-be-edged area corresponding to the binding test area. The to-be-edged area comprises a plurality of test electrodes arranged in the same layer as the common electrode layer and arranged at intervals. At least part of the test terminals is provided with a conductive part. At least part of the test terminals is respectively connected to the corresponding test electrodes through the respective conductive parts, so as to transmit a common voltage or a curing voltage to the liquid crystal display panel. The display panel can reduce the number of metal traces in the peripheral binding test area and the cross-line between each metal trace, reduce the risk of electrostatic discharge, and improve the product yield.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a liquid crystal display panel, a preparation method thereof and a liquid crystal photo-alignment jig. BACKGROUND

[0002] When a liquid crystal display panel (LCD) in a vertically aligned (VA) mode is aligned by a fine slit vertical alignment (FSA) method, a predetermined voltage is applied to a liquid crystal layer, and the liquid crystal layer is irradiated with light at the voltage, so that reactive monomers (RM) in the liquid crystal layer are polymerized and cured, thereby forming polymer layers on both sides of the substrate of the liquid crystal layer, and the liquid crystal molecules are deflected at a certain angle, thereby completing the liquid crystal photo-alignment process.

[0003] The outer lead bonding (OLB) area of the array substrate generally has array test (ATT) terminals for testing the array substrate after the array substrate process is completed, and cell test (CT) terminals for testing the display panel, and curing terminals for curing the display panel are also provided on the curing jig outside the display panel. An external power supply voltage device is used to connect and power each test terminal to apply a predetermined curing voltage to the display panel. Since the curing terminals and each test terminal are electrically connected to the signal lines in the display panel through a plurality of metal traces, the plurality of metal traces usually enter the display panel in a cross-line manner, which increases the risk of electronic static discharge (ESD) in the peripheral OLB area and affects product yield. SUMMARY

[0004] The purpose of the present application is to provide a liquid crystal display panel, a preparation method thereof and a liquid crystal photo-alignment jig, which can reduce the number of metal traces in the peripheral bonding test area and the cross-line between each metal trace, reduce the risk of static discharge and improve product yield.

[0005] In a first aspect, the embodiments of the present application provide a liquid crystal display panel, comprising an array substrate, an opposite substrate and a liquid crystal layer between the array substrate and the opposite substrate, the array substrate having a display area and a binding test area at a periphery of the display area, the display area comprising a plurality of sub-pixels and a plurality of signal lines arranged in an array, the binding test area comprising a plurality of test terminals arranged at intervals, the test terminals being electrically connected to the signal lines through metal traces, the opposite substrate comprising a common electrode layer and a to-be-edged area corresponding to the binding test area, wherein the to-be-edged area comprises a plurality of test electrodes arranged at intervals and in the same layer as the common electrode layer, at least part of the test terminals are provided with conductive parts, and at least part of the test terminals are respectively connected to the corresponding test electrodes through the respective conductive parts to transmit a common voltage or a curing voltage to the liquid crystal display panel.

[0006] In a possible implementation, the plurality of signal lines extend from the display area to the binding test area and are electrically connected to the corresponding test electrodes through part of the test terminals.

[0007] In a possible implementation, the test terminals comprise first test terminals and second test terminals arranged at intervals; the plurality of signal lines are electrically connected to the corresponding first test terminals and second test terminals through metal traces in the binding test area.

[0008] In a possible implementation, the plurality of first test terminals are arranged in rows, part of the first test terminals are used to connect a curing voltage signal; the plurality of second test terminals are arranged in rows, part of the second test terminals and part of the first test terminals are used to connect a common voltage signal; the plurality of first test terminals are one-to-one electrically connected to the plurality of second test terminals through metal traces, and part of the second test terminals are electrically connected to each other through metal traces.

[0009] In a possible implementation, the plurality of test electrodes comprise first test electrodes, second test electrodes, third test electrodes and fourth test electrodes arranged at intervals; part of the first test terminals are respectively connected to the first test electrodes through the respective conductive parts; part of the first test terminals are respectively connected to the second test electrodes through the respective conductive parts; part of the first test terminals and part of the second test terminals are respectively connected to the third test electrodes through the respective conductive parts; and part of the second test terminals are respectively connected to the fourth test electrodes through the respective conductive parts.

[0010] In a possible implementation, the conductive part is silver paste or a metal wire doped with conductive particles.

[0011] In a second aspect, the embodiments of the present application provide a liquid crystal photo-alignment jig for providing an alignment voltage to the liquid crystal display panel as described above, wherein the liquid crystal photo-alignment jig comprises a photo-alignment plate, first and second solidification terminals arranged at intervals on the photo-alignment plate, and a solidification signal line connected between the first solidification terminal and the part of the test terminals of the liquid crystal display panel, and a common signal line connected between the second solidification terminal and the part of the test terminals of the liquid crystal display panel.

[0012] In a third aspect, the embodiments of the present application provide a preparation method of the display panel as described above, comprising: cutting the common electrode layer of the opposed substrate in the edge cutting area into a plurality of test electrodes arranged at intervals; arranging a conductive part on each of the part of the test terminals of the array substrate in the binding test area, wherein the test terminal is electrically connected to the signal line in the display area through a metal trace; bridging and connecting the part of the test terminals to the corresponding test electrodes through the respective conductive parts; providing the liquid crystal photo-alignment jig as described above, and electrically connecting the common signal line and the solidification signal line of the liquid crystal photo-alignment jig to the corresponding test terminals; applying a voltage to the first and second solidification terminals, and simultaneously irradiating the liquid crystal display panel with ultraviolet light to align the liquid crystal layer of the liquid crystal display panel.

[0013] In a possible implementation, before aligning the liquid crystal layer of the liquid crystal display panel, the method further comprises: applying power to the part of the test terminals of the array substrate to perform single-panel testing on the array substrate.

[0014] In a possible implementation, after aligning the liquid crystal layer of the liquid crystal display panel, the method further comprises: removing the edge cutting area of the opposed substrate to expose the binding test area; and applying power to the part of the test terminals of the array substrate to perform cell testing on the liquid crystal display panel.

[0015] According to the liquid crystal display panel and the preparation method thereof and the liquid crystal photo-alignment jig provided by the embodiments of the present application, the common electrode layer of the to-be-edged region of the opposed substrate is cut into a plurality of test electrodes which are spaced apart, then the conductive parts are arranged on the partial test terminals in the binding test region of the array substrate, and the partial test terminals are respectively bridged and connected with the corresponding test electrodes through the respective conductive parts, so as to transmit the common voltage or the curing voltage to the liquid crystal display panel. In this way, the number of metal traces of the peripheral binding test region and the cross-line between the metal traces can be reduced, the risk of electrostatic discharge is reduced, and the product yield is improved. In addition, the signal channel and the wiring mode of the liquid crystal photo-alignment jig can be simplified, after the related test and the alignment of the liquid crystal layer are performed on the single array substrate, the to-be-edged region of the opposed substrate can be removed to perform the cell testing, and the alignment of the liquid crystal layer and the multiple function tests can be realized by arranging a small number of test terminals in the OLB region of the array substrate. In this way, the metal trace cross-line is reduced, the manufacturing cost and the test cost are greatly reduced, and the reliability of the product is improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] The features, advantages, and technical effects of the exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals. The drawings are not drawn according to the actual proportions, but are used only to illustrate the relative positional relationship, and the layer thickness of some parts is exaggerated in the drawing for the purpose of understanding. The layer thickness in the drawings does not represent the proportional relationship of the actual layer thickness.

[0017] Figure 1 A structure schematic diagram of a liquid crystal display panel and a liquid crystal photo-alignment jig in the related art is shown.

[0018] Figure 2 A structure schematic diagram of a liquid crystal display panel and a liquid crystal photo-alignment jig in the related art is shown. Figure 1 An enlarged structure schematic diagram of the region B is shown.

[0019] Figure 3 A structure schematic diagram of a liquid crystal display panel and a liquid crystal photo-alignment jig provided by the embodiments of the present application is shown.

[0020] Figure 4 An enlarged structure schematic diagram of the region C is shown. Figure 3 An enlarged structure schematic diagram of the region C is shown.

[0021] Figure 5 A partial structure schematic diagram of the opposed substrate of a liquid crystal display panel is shown. Figure 3 A partial structure schematic diagram of the opposed substrate of a liquid crystal display panel is shown.

[0022] Figure 6 A cross-sectional view along the direction D-D is shown. Figure 4 A cross-sectional view along the direction D-D is shown.

[0023] Figure 7 A cross-sectional view along the direction E-E is shown. Figure 4 A cross-sectional view along the direction E-E is shown.

[0024] Figure 8 shows Figure 4 a sectional view along the direction F-F;

[0025] Figure 9 A flow chart of a method for manufacturing a liquid crystal display panel is shown.

[0026] Explanation of reference numerals:

[0027] 1, array substrate; AA, display area; OLB, binding test area; H, solidification voltage signal; L, common voltage signal; 11, test terminal; 11A, first test terminal; 11B, second test terminal; 12, conductive part;

[0028] 2, counter substrate; 21, common electrode layer; 22, test electrode; CA, to-be-edged area; 22A, first test electrode; 22B, second test electrode; 22C, third test electrode; 22D, fourth test electrode;

[0029] 3, liquid crystal layer; 4, light alignment plate; 40, solidification terminal; 41, first solidification terminal; 42, second solidification terminal; 43, solidification signal line; 44, common signal line. DETAILED DESCRIPTION

[0030] Features and exemplary embodiments of various aspects of the present application will be described below in detail. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without some or all of these specific details. The description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary obscuring of the present application; and, for clarity, the dimensions of regions structures can be exaggerated. Furthermore, features, structures or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0031] Figure 1 A structure schematic diagram of a liquid crystal display panel and a liquid crystal light alignment tool in the related art is shown.

[0032] Figure 2 shows Figure 1 An enlarged structure schematic diagram of the area B.

[0033] As Figure 1 and Figure 2As shown, the liquid crystal photoalignment fixture 4 in the related technology includes multiple curing terminals 40 and photoalignment traces electrically connected to the curing terminals 40. The photoalignment traces generally include common signal lines and curing signal lines. The common signal lines are used to provide a common voltage signal N to the common electrode layer on the opposing substrate 2 of the liquid crystal display panel and the common electrode line on the array substrate 1. The curing signal lines are used to provide a curing voltage signal M to the pixel electrodes in the array substrate 1 of the liquid crystal display panel. The voltage difference formed between the common electrode layer and the pixel electrodes drives the liquid crystal cells in the liquid crystal layer to rotate by a preset angle.

[0034] The bonding test area OLB of the array substrate 1 includes multiple first test terminals 11A and multiple second test terminals 11B. The liquid crystal photoalignment fixture 4 is electrically connected to the first test terminals 11A and the second test terminals 11B via curing signal lines and common signal lines, respectively, thereby providing a common voltage and curing voltage to the liquid crystal display panel and aligning the liquid crystal layer of the liquid crystal display panel. The multiple first test terminals 11A and the multiple second test terminals 11B are also used for single-board testing of the array substrate 1, and the second test terminals 11B are also used for CT testing of the liquid crystal display panel after alignment and cell assembly.

[0035] like Figure 2 As shown, the curing signal line provides a curing voltage signal M to the pixel electrodes in the array substrate, which is generally a high-level signal. The common signal line provides a common voltage signal N to the common electrode layer on the opposing substrate and the common electrode line of the array substrate, which is generally a low-level signal. There are many cross-line positions between the curing signal line and the common signal line, as well as between the common signal line and the metal traces. Electrostatic discharge is easily generated between these cross-lines, which can easily damage the metal traces in the OLB area of ​​the array substrate and affect the liquid crystal alignment effect.

[0036] In view of this, embodiments of this application propose a display panel and a liquid crystal photoalignment fixture, which can reduce the number of metal traces in the peripheral bonding test area and the number of cross-lines between each metal trace, reduce the risk of electrostatic discharge, and improve product yield.

[0037] Figure 3 This diagram illustrates the structure of the liquid crystal display panel and the liquid crystal photoalignment fixture provided in an embodiment of this application. Figure 4 Show Figure 3 A magnified structural diagram of region C in the middle; Figure 5 Show Figure 3 A partial structural diagram of the opposing substrate of the liquid crystal display panel; Figure 6 Show Figure 4 Cross-sectional view along direction DD.

[0038] like Figures 3 to 4As shown, the embodiment of the present application provides a display panel, which comprises an array substrate 1, an opposite substrate 2 and a liquid crystal layer 3 between the array substrate 1 and the opposite substrate 2, the array substrate 1 has a display area AA and a binding test area OLB outside the display area AA, the display area AA comprises a plurality of sub-pixels and a plurality of signal lines arranged in an array, and the binding test area OLB comprises a plurality of test terminals 11 arranged at intervals, and the test terminals 11 are electrically connected to the signal lines through metal traces.

[0039] In some examples, the opposite substrate 2 is a color film substrate, and the color filter on array (COA) function and the black matrix on array (BOA) function are integrated. In other examples, the array substrate 1 can also integrate the color filter on array (COA) function or the black matrix on array (BOA) function, which will not be described in detail.

[0040] As shown in Figure 5 and Figure 6 The opposite substrate 2 comprises a common electrode layer 21 and a cutting edge area CA corresponding to the binding test area OLB, the cutting edge area CA comprises a plurality of test electrodes 22 arranged at intervals and in the same layer as the common electrode layer 21, at least part of the test terminals 11 are provided with conductive parts 12, and at least part of the test terminals 11 are respectively connected to the corresponding test electrodes 22 through the respective conductive parts 12, so as to transmit the common voltage or the curing voltage to the liquid crystal display panel. Further, the liquid crystal photo-alignment tool 4 is used to provide an alignment voltage to the liquid crystal display panel, and the liquid crystal photo-alignment tool comprises a photo-alignment plate 4, a first curing terminal 41 and a second curing terminal 42 arranged at intervals on the photo-alignment plate 4, a curing signal line 43 connected between the first curing terminal 41 and part of the test terminals 11 of the liquid crystal display panel, and a common signal line 44 connected between the second curing terminal 42 and part of the test terminals 11 of the liquid crystal display panel, the curing signal line 43 is used to provide a curing voltage to the liquid crystal display panel, and the curing voltage signal H is generally a high-level signal, and the common signal line 44 is used to provide a common voltage to the liquid crystal display panel, and the common voltage signal L is generally a low-level signal. The voltage difference between the common voltage and the curing voltage drives the liquid crystal cells in the liquid crystal layer to rotate and produce a certain deflection angle, and at the same time, the liquid crystal layer is irradiated with ultraviolet light, that is, the photo-alignment process of the liquid crystal display panel is completed.

[0041] As shown in Figure 4As shown, the liquid crystal photo-alignment tool 4 is only provided with two curing terminals 40 and two voltage signal lines, i.e., the first curing terminal 41, the second curing terminal 42, the curing signal line 43 and the common signal line 44. The plurality of test terminals 11 in the binding test area OLB of the array substrate 1 are electrically connected to the plurality of signal lines in the display area AA through metal traces, and some of the test terminals 11 are electrically connected to the curing signal line 43 and the common signal line 44, respectively. Meanwhile, the cutting area CA of the array substrate 2 corresponding to the binding test area OLB includes a plurality of test electrodes 22 which are arranged in the same layer as the common electrode layer 21 and are spaced apart, wherein some of the test terminals 11 are provided with conductive parts 12, and some of the test terminals 11 are bridged to the corresponding test electrodes 22 through the respective conductive parts 12, so as to transmit the common voltage or the curing voltage of the liquid crystal photo-alignment tool 4 to the liquid crystal display panel.

[0042] In some embodiments, the liquid crystal photo-alignment tool 4 can simultaneously perform alignment and related tests for a plurality of liquid crystal display panels. The number of the second curing terminals 42 and the common signal lines 44 is the same as the number of the liquid crystal display panels, and each second curing terminal 42 is electrically connected to a corresponding liquid crystal display panel through a common signal line 44; further comprising a plurality of sub-curing signal lines which are respectively electrically connected to the curing signal line 43, and the first curing terminal 41 is electrically connected to a corresponding liquid crystal display panel through each sub-curing signal line.

[0043] Compared with the related art, the number of the curing terminals 40 and the voltage signal lines in the liquid crystal photo-alignment tool 4 is reduced, i.e., the curing signal channel is reduced, and the number of the metal traces in the OLB area of the array substrate 1 is reduced, so that there is no cross-line between each voltage signal line and each test terminal 11, and between each voltage signal line and each metal trace, even if alignment and testing are simultaneously performed for a plurality of liquid crystal display panels, which greatly reduces the risk of electrostatic discharge in the peripheral OLB area of the array substrate, and is beneficial to improve the product yield.

[0044] According to the liquid crystal display panel and the liquid crystal photo-alignment tool, the common electrode layer 21 of the cutting area CA of the array substrate 2 is cut into a plurality of test electrodes 22 which are spaced apart, and then some of the test terminals 11 in the binding test area OLB of the array substrate 1 are provided with conductive parts 12, and some of the test terminals 11 are bridged to the corresponding test electrodes 22 through the respective conductive parts 12, so as to transmit the common voltage or the curing voltage to the liquid crystal display panel. In this way, the number of the metal traces in the peripheral binding test area OLB and the cross-line between each metal trace can be reduced, the risk of electrostatic discharge can be reduced, and the product yield can be improved. In addition, the curing signal channel and the wiring mode of the liquid crystal photo-alignment tool 4 can be simplified, and the manufacturing cost of the liquid crystal display panel can be reduced.

[0045] In some embodiments, the conductive part 12 is silver paste or metal wire doped with conductive particles to improve the conductive performance between the test terminal 11 and the test electrode 22, so as to facilitate the bridging connection of each test terminal 11 to the corresponding test electrode 22 through the respective conductive part 12.

[0046] In some embodiments, the plurality of signal lines extend from the display area to the binding test area and are electrically connected to the corresponding test electrodes through the partial test terminals.

[0047] Specifically, the plurality of signal lines include scan lines and data lines arranged in cross to define sub-pixels, and a common electrode line located between two scan lines and separated from the pixel electrodes of the sub-pixels by an insulating layer. The common electrode line, the data lines and the scan lines extend from the display area AA to the binding test area OLB, wherein the data lines and the scan lines are electrically connected to the corresponding test electrodes 22 through the partial test terminals 11 and the corresponding conductive parts 12, for providing a fixing voltage to the pixel electrodes. The common electrode line is electrically connected to the corresponding test electrodes 22 through the partial test terminals 11 and the corresponding conductive parts 12, for providing a common voltage to the common electrode layer 21. The voltage difference between the common electrode layer 21 and the pixel electrodes can drive the liquid crystal molecules of the liquid crystal layer to rotate by a preset angle.

[0048] In addition, each sub-pixel further includes a switching element electrically connected to the pixel electrode, which can be a thin film transistor including a gate, a source and a drain. The drain of each thin film transistor is connected to the pixel electrode, the gate is connected to the scan line, and the source is connected to the data line. When a high level is input to the gate through the gate line, the source and the drain are turned on, i.e. the thin film transistor is turned on. At this time, the data line inputs a data signal voltage into the pixel electrode; when a low level is input to the gate through the gate line, the source and the drain are disconnected, i.e. the thin film transistor is turned off. At this time, the voltage in the pixel electrode disappears. Since the common electrode line, the pixel electrode and the insulating layer therebetween form a storage capacitor, the storage capacitor can maintain the voltage on the pixel electrode, i.e. the input and disappearance of the voltage in the pixel electrode both have a changing process, so that a continuous display image can be obtained, resulting in a better image display effect.

[0049] In some embodiments, the test terminal 11 includes first test terminals 11A and second test terminals 11B distributed at intervals, and the plurality of signal lines are electrically connected to the corresponding first test terminals 11A and second test terminals 11B through metal traces in the binding test area, respectively.

[0050] In one example, as shown in FIG. 1, the display panel 1 includes a display area AA and a binding test area OLB. The display area AA includes a plurality of sub-pixels arranged in a matrix, and each sub-pixel includes a pixel electrode, a common electrode layer 21 and a liquid crystal layer 20. The pixel electrode is electrically connected to a switching element, which can be a thin film transistor including a gate, a source and a drain. The drain of each thin film transistor is connected to the pixel electrode, the gate is connected to a scan line, and the source is connected to a data line. The common electrode layer 21 is electrically connected to a common electrode line. The common electrode line, the data lines and the scan lines extend from the display area AA to the binding test area OLB, wherein the data lines and the scan lines are electrically connected to the corresponding test electrodes 22 through the partial test terminals 11 and the corresponding conductive parts 12, for providing a fixing voltage to the pixel electrodes. The common electrode line is electrically connected to the corresponding test electrodes 22 through the partial test terminals 11 and the corresponding conductive parts 12, for providing a common voltage to the common electrode layer 21. The voltage difference between the common electrode layer 21 and the pixel electrodes can drive the liquid crystal molecules of the liquid crystal layer to rotate by a preset angle. Figure 4As shown, the first test terminal 11A is located on the side of the second test terminal 11B away from the display area AA. The common electrode line, data line, and scan line are electrically connected to the corresponding first test terminal 11A and second test terminal 11B respectively through metal traces in the bonding test area OLB.

[0051] When power is applied to some of the test terminals 11 of the array substrate 1, single-board testing can be performed on the array substrate 1. When voltage is applied to the first curing terminal 41 and the second curing terminal 42, and ultraviolet light is applied to the liquid crystal display panel, the liquid crystal layer 3 of the liquid crystal display panel can be aligned. After alignment is completed, the edge area CA to be cut on the opposing substrate 2 is removed, causing the bridging connection between some of the test terminals 11 and their respective conductive parts 12 and the corresponding test electrodes 22 to fail. The array substrate 1 exposes the bonding test area OLB, and when power is applied to some of the test terminals 11, cell assembly testing of the liquid crystal display panel can be performed. In this way, multiple functional tests can be achieved with a small number of test terminals, reducing manufacturing costs. At the same time, it can also reduce the number of metal traces in the peripheral bonding test area OLB and the crossovers between the metal traces, reducing the risk of electrostatic discharge and improving product yield.

[0052] In some embodiments, a plurality of first test terminals 11A are arranged in a row, and some of the first test terminals 11A are used to connect to a solidified voltage signal; a plurality of second test terminals 11B are arranged in a row, and some of the second test terminals 11B and some of the first test terminals 11A are used to connect to a common voltage signal; the plurality of first test terminals 11A are electrically connected to the plurality of second test terminals 11B one-to-one through metal traces, and some of the second test terminals 11B are electrically connected to each other through metal traces.

[0053] In one example, such as Figure 4 As shown, the first test terminal 11A includes five first test terminals 11A arranged in a row, with the first to fifth first test terminals 11A labeled with serial numbers 1 to 5 respectively. The second test terminal 11B includes six second test terminals 11B arranged in a row, with the first to sixth second test terminals 11B labeled with serial numbers 1 to 6 respectively. The curves represent the bridging connections between each test terminal 11 and its corresponding test electrode 22 through its respective conductive part 12.

[0054] The first, second and third first test terminals 11A are respectively and one-to-one electrically connected with the first, second and third second test terminals 11B through metal traces. The fourth and fifth first test terminals 11A are respectively and one-to-one electrically connected with the fifth and sixth second test terminals 11B through metal traces. The first, second and fourth first test terminals 11A are respectively connected with the corresponding test electrodes 22 through the respective conductive parts 12, for connecting the solidification voltage signal H. The third and fourth second test terminals 11B and the fifth first test terminal 11A are respectively connected with the corresponding test electrodes 22 through the respective conductive parts 12, for connecting the common voltage signal L. In this way, the number of metal traces and the cross-wires between the metal traces in the peripheral bonding test area OLB can be reduced, the risk of electrostatic discharge can be reduced, and the product yield can be improved, while realizing the single-board test and the box test of the alignment and array substrate 1.

[0055] Figure 7 shown Figure 4 a cross-sectional view along direction E-E; Figure 8 shown Figure 4 a cross-sectional view along direction F-F.

[0056] In some embodiments, the plurality of test electrodes 22 arranged in the cutting area CA of the opposite substrate 2 include the first test electrodes 22A, the second test electrodes 22B, the third test electrodes 22C and the fourth test electrodes 22D which are spaced apart. Each test electrode 22 can be formed by laser cutting the common electrode layer 22 in the cutting area CA. The first test terminals 11A are respectively connected with the first test electrodes 22A through the respective conductive parts 12. The first test terminals 11A are respectively connected with the second test electrodes 22B through the respective conductive parts 12. The first test terminals 11A and the second test terminals 11B are respectively connected with the third test electrodes 22C through the respective conductive parts 12. The second test terminals 11B are respectively connected with the fourth test electrodes 22D through the respective conductive parts 12.

[0057] in combination Figures 5 to 8 , still with Figure 4The five first test terminals 11A and six second test terminals 11B are taken as an example for illustration. The first and second first test terminals 11A are respectively bridged with the first test electrode 22A through the respective conductive portions 12; the second and fourth first test terminals 11A are respectively bridged with the second test electrode 22B through the respective conductive portions 12; the fifth first test terminal 11A and the fourth second test terminal 11B are respectively bridged with the third test electrode 22C through the respective conductive portions 12; and the third and fourth second test terminals 11B are respectively bridged with the fourth test electrode 22D through the respective conductive portions 12. After the first test terminals 11A, the second test terminals 11B are respectively bridged with the corresponding test electrodes 22 through the respective conductive portions 12, the flowing direction of the current is as shown by the arrows. Figures 6 to 8

[0058] Figure 9 A flow chart of the preparation method of the liquid crystal display panel is shown.

[0059] As shown in Figure 9 The preparation method of any one of the liquid crystal display panels as described above includes the following steps S1-S3. Step S1 is to perform single panel testing on the array substrate 1, step S2 is to perform alignment on the liquid crystal layer of the liquid crystal display panel, and step S3 is to perform cell testing on the liquid crystal display panel.

[0060] Specifically, step S2 of performing alignment on the liquid crystal layer of the liquid crystal display panel includes the following steps S21-S25.

[0061] Step S21: cutting the common electrode layer 21 of the opposed substrate 2 located in the edge cutting area CA into a plurality of test electrodes 22 distributed at intervals;

[0062] Step S22: providing a conductive portion 12 on each of the test terminals 11 of the array substrate 1 located in the binding test area OLB, wherein the test terminal 11 is electrically connected to the signal line located in the display area AA through a metal trace;

[0063] Step S23: bridging and connecting each of the test terminals 11 through the respective conductive portions 12 with the corresponding test electrode 22;

[0064] Step S24: providing the liquid crystal photo-alignment tool as described above, and electrically connecting the common signal line 43 and the curing signal line 44 of the liquid crystal photo-alignment tool with the corresponding test terminals 11, respectively;

[0065] Step S25: applying a first voltage to the first curing terminal 41 and the second curing terminal 42, and simultaneously irradiating the liquid crystal display panel with ultraviolet light to perform alignment on the liquid crystal layer of the liquid crystal display panel.​

[0066] Further, before the liquid crystal layer of the liquid crystal display panel is aligned in step S2, step S1 of applying power to the partial test terminals of the array substrate 1 to perform single panel testing on the array substrate 1 is further included.

[0067] Specifically, the first test terminal 11A of the array substrate 1 is applied with power by needle, so that the first test terminal 11A is electrically connected to the plurality of signal lines in the display area AA through the second test terminal 11B and each metal trace, thereby completing the single panel testing on the array substrate 1.

[0068] Further, after the liquid crystal layer of the liquid crystal display panel is aligned in step S2, step S3 of performing cell testing on the liquid crystal display panel is further included. Specifically, the step S3 includes:

[0069] Step S31 of removing the to-be-edged area CA of the opposing substrate 2 to expose the binding test area OLB;

[0070] Step S32 of applying power to the partial test terminals of the array substrate 1 to perform cell testing on the liquid crystal display panel to perform cell testing on the liquid crystal display panel.

[0071] Specifically, the second test terminal 11B of the array substrate 1 is applied with power by needle, so that the second test terminal 11B is electrically connected to the plurality of signal lines in the display area AA through each metal trace, thereby completing the cell testing on the liquid crystal display panel.

[0072] The preparation method of the liquid crystal display panel provided by the embodiments of the present application simplifies the curing signal channel and wiring mode of the liquid crystal photo-alignment jig 4, and after the related testing on the single panel of the array substrate 1 and the alignment of the liquid crystal layer of the liquid crystal display panel, the to-be-edged area CA of the opposing substrate 2 is removed to perform cell testing on the liquid crystal display panel. A small number of test terminals are arranged in the OLB area of the array substrate 1 to achieve alignment and multiple function testing. The metal trace cross-line is reduced, the manufacturing cost and the testing cost are greatly reduced, and the reliability of the product is improved.

[0073] It should be readily understood that "on", "over", and "above" in the present application should be interpreted in the broadest manner, such that "on" means not only "directly on", but also includes the meaning of "on" with intermediate features or layers therebetween, and "over" or "above" includes the meaning of "over" or "above" with no intermediate features or layers therebetween (i.e., directly on).

[0074] As used herein, the term "substrate" refers to a material on which a subsequent material layer is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer, etc.

[0075] As used herein, the term "layer" can refer to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a scope less than the scope of the underlying or overlying structure. Further, a layer can be a region of a continuous structure that is homogeneous or inhomogeneous and that has a thickness less than the thickness of the continuous structure. For example, a layer can be between or at any pair of lateral planes between a top surface and a bottom surface of the continuous structure. A layer can extend laterally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (within which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0076] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit it; even though the present application has been described in detail with reference to the above-described embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the above-described embodiments, or make equivalent replacements to some or all of the technical features thereof; and such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A liquid crystal display panel, comprising an array substrate, an opposite substrate and a liquid crystal layer between the array substrate and the opposite substrate, the array substrate having a display area and a binding test area at a periphery of the display area, the display area comprising a plurality of sub-pixels and a plurality of signal lines arranged in an array, the binding test area comprising a plurality of test terminals arranged at intervals, the test terminals being electrically connected to the signal lines through metal traces, the opposite substrate comprising a common electrode layer and a to-be-edged area corresponding to the binding test area, characterized in that: the to-be-edged area comprises a plurality of test electrodes arranged at intervals and in the same layer as the common electrode layer, at least part of the test terminals being provided with conductive parts, at least part of the test terminals being respectively connected to corresponding test electrodes through the conductive parts to transmit a common voltage or a curing voltage to the liquid crystal display panel; the plurality of signal lines extend from the display area to the binding test area and are electrically connected to corresponding test electrodes through part of the test terminals; the test terminals comprise first test terminals and second test terminals arranged at intervals; the plurality of signal lines are respectively electrically connected to corresponding first test terminals and second test terminals through metal traces in the binding test area; the plurality of signal lines comprise scan lines and data lines arranged in a cross shape to define sub-pixels, and a common electrode line between two scan lines, the common electrode line being separated from pixel electrodes of the sub-pixels by an insulating layer; the plurality of first test terminals and the plurality of second test terminals are used for single-panel testing of the array substrate, and the second test terminals are also used for cell testing of the liquid crystal display panel after alignment and cell formation; the plurality of first test terminals are arranged in rows, and part of the first test terminals are used for connecting a curing voltage signal; the plurality of second test terminals are arranged in rows, and part of the second test terminals and part of the first test terminals are used for connecting a common voltage signal; the plurality of first test terminals are respectively and one-to-one electrically connected to the plurality of second test terminals through metal traces, and part of the second test terminals are electrically connected to each other through metal traces. ​ ​ ​ ​ ​ ​ 2. The liquid crystal display panel according to claim 1, characterized by ​ ​ ​ 3. The liquid crystal display panel according to claim 2, wherein ​ ​ ​ ​ ​ 4. The liquid crystal display panel according to claim 1, wherein ​ 5. A liquid crystal photo-alignment apparatus for providing an alignment voltage to the liquid crystal display panel according to any one of claims 1 to 4, characterized in that, The liquid crystal photo-alignment jig comprises a photo-alignment plate, first and second curing terminals arranged at intervals on the photo-alignment plate, and a curing signal line connected between the first curing terminal and part of the test terminals of the liquid crystal display panel and a common signal line connected between the second curing terminal and part of the test terminals of the liquid crystal display panel.

6. A method of manufacturing a liquid crystal display panel as claimed in any one of claims 1 to 4, characterized in that Comprise: cutting the common electrode layer of the opposed substrate in the to-be-edged region into a plurality of test electrodes arranged at intervals; arranging conductive parts on part of the test terminals of the array substrate in the binding test region respectively, wherein the test terminals are electrically connected to the signal lines in the display region through metal traces; bridging part of the test terminals to the corresponding test electrodes through the respective conductive parts; providing the liquid crystal photo-alignment jig as claimed in claim 5, and electrically connecting the common signal line and the curing signal line of the liquid crystal photo-alignment jig to the corresponding test terminals respectively; applying voltage to the first and second curing terminals while irradiating the liquid crystal display panel with ultraviolet light to align the liquid crystal layer of the liquid crystal display panel; before aligning the liquid crystal layer of the liquid crystal display panel, further comprising: energizing part of the test terminals of the array substrate to perform single-panel testing on the array substrate; after aligning the liquid crystal layer of the liquid crystal display panel, further comprising: removing the to-be-edged region of the opposed substrate to expose the binding test region; energizing part of the test terminals of the array substrate to perform cell testing on the liquid crystal display panel.

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