A power-on control method, device, system and computer readable storage medium

Abstract

The application provides a power-on control method, device, system and computer readable storage medium. The method is applied to a CPLD. The CPLD is connected with switch devices. Each switch device is arranged in a power supply path between a power supply and each PCIE device. The method comprises the following steps: controlling all switch devices to remain disconnected to control each power supply path to be disconnected; when a start-up signal is detected, a first preset signal value for setting a time-sharing power-on mode is acquired; a target time-sharing power-on mode is determined according to the first preset signal value, and each switch device is controlled to be turned on in turn according to the target time-sharing power-on mode to sequentially control PCIE devices connected with the switch devices to be powered on and started. The switch devices can be arranged in the power supply path between the power supply and each PCIE device, and the CPLD is used to sequentially control each control switch device to be turned on according to the target time-sharing power-on mode to realize orderly power-on and start control of each PCIE device, and problems such as excessively high power consumption and system disorder caused by simultaneous start of the PCIE devices can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of server power-on control, in particular to a power-on control method, device, system and computer readable storage medium. BACKGROUND

[0002] PCIE devices (peripheral component interconnect express, high-speed serial computer expansion bus standard) are common devices in servers, such as GPUs (graphics processing units), MOC cards, network cards, etc. In related technologies, if PCIE devices are started at the same time, it is easy to cause problems such as excessive power consumption and system disorder, so how to control the orderly start of PCIE devices is a technical problem that technicians in the field need to solve. SUMMARY

[0003] The purpose of the present application is to provide a power-on control method, device, system and computer readable storage medium, which can use CPLD (Complex Programmable Logic Device, Complex Programmable Logic Device) to control the orderly power-on start of each PCIE device in sequence, thereby effectively avoiding problems such as excessive power consumption and system disorder caused by simultaneous start of PCIE devices.

[0004] To solve the above technical problems, the present application provides a power-on control method applied to a CPLD, wherein the CPLD is connected with switching devices, each of the switching devices is arranged in a power supply path between a power supply and each PCIE device, and the method comprises:

[0005] controlling all the switching devices to remain disconnected to control each of the power supply paths to be disconnected;

[0006] when a start signal is detected, obtaining a first preset signal value for setting a time-sharing power-on mode;

[0007] determining a target time-sharing power-on mode according to the first preset signal value, and controlling each of the switching devices to be turned on in sequence according to the target time-sharing power-on mode, so as to control the PCIE devices connected with each of the switching devices to be powered on and started in sequence.

[0008] Optionally, the step of determining a target time-sharing power-on mode according to the first preset signal value, and controlling each of the switching devices to be turned on in sequence according to the target time-sharing power-on mode comprises:

[0009] when it is determined that the first preset signal value corresponds to a power consumption type time-sharing power-on mode, controlling a corresponding switching device to be turned on every first preset time according to a preset switching device turn-on sequence; and the first preset time is greater than the duration of maintaining maximum power consumption of each of the PCIE devices during the start process.

[0010] Optionally, the method further comprises:

[0011] when the first preset signal value corresponds to the functional time-sharing power-on mode, controlling the corresponding switch device to be turned on every second preset time according to a preset switch device turn-on sequence; the second preset time is greater than a time for the host device to allocate a hard disk drive letter to each PCIE device.

[0012] Optionally, the method further comprises:

[0013] acquiring a second preset signal value for setting a time-sharing power-on sequence, and determining the switch device turn-on sequence according to the second preset signal value.

[0014] Optionally, the method further comprises:

[0015] reading the first preset signal value from a dial switch or a designated register;

[0016] Optionally, the method further comprises:

[0017] reading the second preset signal value from the dial switch or the designated register.

[0018] Optionally, the method further comprises:

[0019] when the first preset signal value does not correspond to any time-sharing power-on mode, controlling all switch devices to be turned on at the same time to control each PCIE device to be normally started.

[0020] Optionally, the switch device is a MOS tube, and the method further comprises:

[0021] keeping a voltage output to the MOS tube as a first preset value to control the MOS tube to be kept off;

[0022] Optionally, the method further comprises:

[0023] adjusting the voltage output to each MOS tube to a second preset value according to the target time-sharing power-on mode to control the MOS tube to be turned on.

[0024] The application further provides an upper power control device applied to a CPLD, wherein the CPLD is connected with switch devices, each of the switch devices is arranged in a power supply path between a power supply and each PCIE device, and the device comprises:

[0025] a disconnecting control module for controlling all the switch devices to keep disconnected to control each of the power supply paths to be disconnected;

[0026] a first signal value acquisition module for acquiring a first preset signal value for setting a time-sharing upper power mode when a start-up signal is detected;

[0027] an upper power control module for determining a target time-sharing upper power mode according to the first preset signal value, and controlling each of the switch devices to be turned on in sequence according to the target time-sharing upper power mode to sequentially control PCIE devices connected with each of the switch devices to be started up.

[0028] The application further provides an upper power control system comprising a CPLD, switch devices, a power supply and PCIE devices, wherein the CPLD is connected with the switch devices, each of the switch devices is arranged in a power supply path between the power supply and each of the PCIE devices, and the CPLD is configured to execute the upper power control method.

[0029] The CPLD is configured to execute the upper power control method.

[0030] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores computer executable instructions, and the computer executable instructions are loaded and executed by a processor to implement the upper power control method.

[0031] The application provides an upper power control method applied to a CPLD, wherein the CPLD is connected with switch devices, each of the switch devices is arranged in a power supply path between a power supply and each PCIE device, and the method comprises the following steps: controlling all the switch devices to keep disconnected to control each of the power supply paths to be disconnected; acquiring a first preset signal value for setting a time-sharing upper power mode when a start-up signal is detected; determining a target time-sharing upper power mode according to the first preset signal value, and controlling each of the switch devices to be turned on in sequence according to the target time-sharing upper power mode to sequentially control PCIE devices connected with each of the switch devices to be started up.

[0032] It can be seen that the application can set the switching device in the power supply path between the power supply and each PCIE device, and control the on-off of the switching device by using the CPLD; before detecting the start-up signal, the CPLD can first control all the switching devices to keep closed to control the disconnection of each power supply path, that is, to ensure that each PCIE device is closed; when the start-up signal is detected, the CPLD can obtain the first preset signal value for setting the time-sharing power-on mode, and select the corresponding target time-sharing power-on mode according to the signal value, to control the switching devices to be turned on in sequence based on the mode, that is, to control the PCIE devices connected with the switching devices to be started in order according to the mode, thereby effectively avoiding the problems of high power consumption and system disorder caused by the simultaneous start of the PCIE devices, and effectively ensuring the orderly operation of the PCIE devices and the server. The application can also provide a power-on control device, system and computer readable storage medium, which have the above beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0034] Figure 1 A flow chart of a power-on control method provided by an embodiment of the present application;

[0035] Figure 2 A topological schematic diagram of a power-on control system provided by an embodiment of the present application;

[0036] Figure 3 A flow chart of another power-on control method provided by an embodiment of the present application;

[0037] Figure 4 A structural block diagram of a power-on control device provided by an embodiment of the present application;

[0038] Figure 5 A structural block diagram of a power-on control system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0040] In the related art, if PCIE devices are started at the same time, problems such as excessive power consumption and system disorder are prone to occur, and therefore how to control the orderly start of PCIE devices is a technical problem that needs to be solved by those skilled in the art. Therefore, the present application can provide a power-on control method, which can use a CPLD to sequentially control the orderly power-on start of each PCIE device, thereby effectively avoiding problems such as excessive power consumption and system disorder caused by the simultaneous start of PCIE devices. Please refer to Figure 1 , Figure 1 A flowchart of a power-on control method provided by an embodiment of the present application, the method is applied to a CPLD, the CPLD is connected with switching devices, each switching device is arranged in a power supply path between a power supply and each PCIE device, and the method can include the following steps.

[0041] S101, control all switching devices to remain disconnected to control each power supply path to be disconnected.

[0042] In the embodiment of the present application, before the server is powered on, the CPLD controls all switching devices to remain disconnected to ensure that the power supply path between the power supply and each PCIE device is disconnected. In this way, before the CPLD performs the corresponding power-on control action, even if the server is powered on, each PCIE device cannot be powered on due to the disconnected state of each power supply path. In other words, the start time of each PCIE device is determined by the CPLD.

[0043] It should be noted that the embodiments of the present application are not limited to specific switching devices, for example, they can be MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transisto, also known as field effect tubes), or switching chips with switching functions, which can be set according to actual application requirements. For easy setting, the above-mentioned switching devices can be MOS tubes, and then the CPLD can adjust the voltage output to the MOS tube to control the on-off of the MOS tube. It should be pointed out that a corresponding MOS tube is arranged on the power supply path between the power supply and each PCIE device, and the specific arrangement can be referred to Figure 2 , Figure 2As shown in a topological diagram of the power-on control system provided by the embodiment of the present application, MOS1-N corresponding to the paths between PCIE1-N and the power supply module are arranged.

[0044] In a possible case, the switch device is a MOS tube, and the step of controlling all the switch devices to keep off can include:

[0045] Step 11: keeping the voltage output to the MOS tube as a first preset value to control the MOS tube to keep off.

[0046] It should be noted that the embodiment of the present application does not limit the specific value of the first preset value, as long as the MOS tube can be kept off.

[0047] S102, when detecting a power-on signal, acquiring a first preset signal value for setting a time-sharing power-on mode.

[0048] When detecting a power-on signal (such as a power-on signal generated by a user triggering a power-on key), the CPLD will actively acquire a first preset signal value for setting a time-sharing power-on mode, so as to determine the mode for controlling the PCIE device to power on based on the signal value. The embodiment of the present application does not limit where the CPLD acquires the first preset signal value, for example, the preset signal value can be written into a register readable by the CPLD, so that the CPLD reads data from the register; of course, a dial switch connected to the CPLD can also be set, and the CPLD will read the dial of the dial switch and take the dial as the first preset signal value.

[0049] In a possible case, acquiring the first preset signal value for setting the time-sharing power-on mode can include:

[0050] Step 21: reading the first preset signal value from the dial switch or the designated register.

[0051] In other words, the dial switch will be directly connected to the CPLD, as shown in Figure 2 .

[0052] S103, determining a target time-sharing power-on mode according to the first preset signal value, and sequentially controlling each switch device to conduct according to the target time-sharing power-on mode, so as to sequentially control the PCIE device connected to each switch device to power on and start.

[0053] It can be understood that when the switch device is a MOS tube, the CPLD only needs to adjust the voltage value output to each MOS tube to make each MOS tube conduct, so as to realize the power-on control of the PCIE device.

[0054] In a possible case, sequentially controlling each switch device to conduct according to the target time-sharing power-on mode can include:

[0055] Step 31: according to the target time-sharing power-on mode, the voltage output to each MOS tube is adjusted to a second preset value in sequence to control the MOS tube to be turned on.

[0056] It should be noted that the embodiment of the present application does not limit the specific value of the second preset value, as long as it can ensure that the MOS tube is turned on.

[0057] Further, in order to adapt to different power-on requirements, the embodiment of the present application sets a corresponding time-sharing power-on mode for each power-on control scene, so that the CPLD controls the PCIE device to power on by using a suitable target time-sharing power-on mode. For example, when the total power consumption of the PCIE device is high, for example, when the PCIE device is mostly GPU, if all PCIE devices are started at the same time, the total startup power consumption of these devices may exceed the capacity of the power supply, thereby causing the server to fail to start. Therefore, the embodiment of the present application designs a corresponding power consumption type time-sharing power-on mode. When the first preset signal value of the CPLD corresponds to the power consumption type time-sharing power-on mode, it can control the corresponding switching device to be turned on every first preset time based on the preset switching device turn-on sequence, so as to start each PCIE device in the above sequence, wherein the first preset time should be greater than the duration of the maximum power consumption of each PCIE device during the startup process. For example, when the duration of each PCIE device maintaining full load power consumption during startup is 200ms, the embodiment of the present application can set the first preset time to 300ms, so that each PCIE device can avoid the time period when the previous PCIE device maintains full load power consumption during startup, thereby ensuring that the power supply can bear the startup power of the PCIE device.

[0058] In one possible case, according to the first preset signal value to determine the target time-sharing power-on mode, and according to the target time-sharing power-on mode to control each switching device to be turned on in sequence, which can include:

[0059] Step 41: when it is determined that the first preset signal value corresponds to the power consumption type time-sharing power-on mode, the corresponding switching device is controlled to be turned on every first preset time according to the preset switching device turn-on sequence; the first preset time is greater than the duration of the maximum power consumption of each PCIE device during the startup process.

[0060] It should be noted that the embodiment of the present application does not limit the specific value of the first preset time, which can be set as needed after measuring the duration of the maximum power consumption of each PCIE device during the startup process.

[0061] Further, some PCIE devices have a competition relationship in the starting process, and thus if these PCIE devices are started at the same time, system disorder is easily caused, for example, for the configuration of multiple RAID cards (Redundant Arrays of Independent Disks, disk array), since the RAID cards have a competition relationship when being powered on at the same time, the problem of hard disk disorder is often easily caused. Therefore, the embodiment of the present application designs a corresponding functional time-sharing power-on mode, when the CPLD first preset signal value corresponds to the power consumption type time-sharing power-on mode, the corresponding switch device is controlled to be turned on every second preset time based on the preset switch device turn-on sequence, so as to start each PCIE device in the above sequence, wherein the second preset time should be greater than the time for the host device to allocate hard disk drive letters for each PCIE device, for example, it can be set to 100 ms. In this way, since the host device can set the hard disk drive letters in the starting sequence of the PCIE device, the problem of system disorder caused by the simultaneous starting of the PCIE device can be effectively avoided.

[0062] In a possible case, the step of determining the target time-sharing power-on mode according to the first preset signal value, and controlling each switch device to be turned on in sequence according to the target time-sharing power-on mode, can include:

[0063] Step 51: when it is determined that the first preset signal value corresponds to the functional time-sharing power-on mode, the corresponding switch device is controlled to be turned on every second preset time according to the preset switch device turn-on sequence; the second preset time is greater than the time for the host device to allocate hard disk drive letters for each PCIE device.

[0064] It should be noted that the embodiment of the present application does not limit the specific value of the second preset time, which can be set as needed after measuring the time for the host device to allocate hard disk drive letters for each PCIE device. It can be understood that the second preset time can be as small as possible to reduce the total starting time of the server under the condition of meeting the application requirements.

[0065] Further, when the server does not need to time-share the power-on of the PCIE device, the first preset signal value can also be set to not correspond to any time-sharing power-on mode, and thus the CPLD can control all switch devices to be turned on at the same time to control each PCIE device to be normally started when it is determined that the first preset signal value does not correspond to any time-sharing power-on mode.

[0066] In a possible case, the step of determining the target time-sharing power-on mode according to the first preset signal value, and controlling each switch device to be turned on in sequence according to the target time-sharing power-on mode, can include:

[0067] Step 61: when determining that the first preset signal value does not correspond to any time-sharing power-on mode, controlling all switch devices to be turned on at the same time to control the PCIE device to start normally.

[0068] It should be noted that the embodiment of the present application does not limit the specific first preset signal value, and does not limit the corresponding relationship between the first preset signal value and each time-sharing power-on function mode, which can be set according to actual application requirements. For example, when the first preset signal value is set by a dial switch, and there are only two time-sharing power-on functions of power consumption type and function type, a 2-bit dial switch can be set, wherein when the dial value is 10, the power consumption type time-sharing power-on mode is corresponded, when the dial value is 11, the function type time-sharing power-on mode is corresponded, and when the dial value is 00 and 01, the time-sharing power-on function is closed. Of course, if the types of time-sharing power-on modes are more, a dial switch with more bits can also be set, or other forms of first preset signal values can also be used, which can be set according to actual application requirements.

[0069] Further, it can be noted that the CPLD controls the PCIE device to start based on the power consumption type time-sharing power-on mode and the function type time-sharing power-on mode, and is processed based on the preset switch device turn-on sequence. The embodiment of the present application does not limit the specific switch device turn-on sequence, which can be fixed or can be freely adjusted by the user. In order to improve the control flexibility, the switch device turn-on sequence can be determined by another preset signal value, that is, the CPLD can further obtain this preset value before controlling each switch device to be turned on, and determine the corresponding switch device turn-on sequence according to this preset value, so that the user only needs to adjust this signal value to adjust the above-mentioned switch device turn-on sequence.

[0070] In one possible case, before controlling each switch device to be turned on in turn according to the target time-sharing power-on mode, it can further include:

[0071] Step 71: obtaining a second preset signal value for setting a time-sharing power-on sequence, and determining a switch device turn-on sequence according to the second preset signal value.

[0072] Similarly, the second preset signal value can also be set in the dial switch or the designated register readable by the CPLD.

[0073] In one possible case, obtaining a second preset signal value for setting a time-sharing power-on sequence can include:

[0074] Step 81: reading the second preset signal value from the dial switch or the designated register.

[0075] It should be explained that the embodiment of the application does not limit the specific second preset signal value, and does not limit the corresponding relationship between the second preset signal value and the conduction sequence of each switching device. It can be set according to the actual application requirement. For example, the total number of PCIE devices of the existing server usually does not exceed 8, at this time, a 6-bit dial switch can meet the requirement, when the dial switch value is 000000, it corresponds to sequence 1, when the dial switch value is 000001, it corresponds to sequence 2, when the dial switch value is 000010, it corresponds to sequence 3, and so on.

[0076] Based on the above embodiment, the application can set a switching device in the power supply path between the power supply and each PCIE device, and use the CPLD to control the on-off of the switching device. Before detecting the power-on signal, the CPLD can first control all the switching devices to keep closed to control the disconnection of each power supply path, that is, to ensure that each PCIE device is closed. When the power-on signal is detected, the CPLD can obtain the first preset signal value for setting the time-sharing power-on mode, and select the corresponding target time-sharing power-on mode according to the signal value, so as to control the conduction of each switching device in turn based on this mode, that is, to control the orderly power-on of the PCIE device connected with each switching device in turn according to this mode, thereby effectively avoiding the problems of high power consumption and system disorder caused by the simultaneous start of the PCIE device, and effectively guaranteeing the orderly operation of the PCIE device and the server.

[0077] The above power-on control method will be described in detail in combination with a specific flow chart. Please refer to Figure 3 , Figure 3 The flow chart of another power-on control method provided by the embodiment of the application can include:

[0078] ①In the 12V path of the power supply to the PCIE device, a MOS tube is added, and the CPLD can control the on-off of the MOS tube by adjusting the high and low voltage output to the MOS tube. When the MOS tube is turned on, the PCIE device can be normally powered.

[0079] ②Two dial switches are designed on the mainboard to set the related functions of time-sharing power-on. A 2-bit dial switch can be used for setting the switch and mode of time-sharing power-on function. The specific table can be referred to as follows.

[0080] First bit Second bit Function 1 0 Power type split power-up 1 1 Function type split power-up 0 0 Split power-up function off 0 1 Split power-up function off

[0081] ③According to the different time-sharing power-on scenes, two modes are designed.

[0082] Power consumption type time-sharing power-on: when the total power consumption of the PCIE device is high (such as multi-GPU configuration), this mode is used. At this time, in order to avoid that the simultaneous power-on of the device exceeds the total power consumption of the power module, each PCIE device needs to be powered on with an interval of 300ms.

[0083] Functional time-sharing power-on: this mode is used to realize time-sharing power-on for certain specific needs. For example, the configuration of multiple RAID cards, due to the competition relationship when the RAID cards are powered on at the same time, the problem of hard disk disorder often occurs, at this time, this mode can be used, each RAID card is powered on in order, and the hard disk drive letter can be allocated according to the actual needs. In this mode, in order to reduce the total boot time, each PCIE device is powered on at intervals of 100ms.

[0084] ④Dial 2 is used to customize the power-on sequence of PCIE devices. Currently, the total number of PCIE devices in a 2U server usually does not exceed 8, at this time, a 6-bit dial switch can meet the needs, and the specific configuration is analyzed.

[0085] The power-on control device, system and computer readable storage medium provided by the embodiment of the application are introduced below, and the power-on control device, system and computer readable storage medium described below can be mutually corresponding to the power-on control method described above.

[0086] Please refer to Figure 4 , Figure 4 The structure block diagram of a power-on control device provided by the embodiment of the application, the device is applied to a CPLD, the CPLD is connected with switch devices, each switch device is arranged in a power supply path between a power supply and each PCIE device, and the device can include:

[0087] The disconnecting control module 401 is used to control all switch devices to remain disconnected, so as to control each power supply path to be disconnected.

[0088] The first signal value acquisition module 402 is used to acquire a first preset signal value for setting a time-sharing power-on mode when detecting a boot signal.

[0089] The power-on control module 403 is used to determine a target time-sharing power-on mode according to the first preset signal value, and sequentially control each switch device to be turned on according to the target time-sharing power-on mode, so as to sequentially control the PCIE devices connected with each switch device to be powered on and started.

[0090] Optionally, the power-on control module 403 is specifically used for:

[0091] When it is determined that the first preset signal value corresponds to the power consumption type time-sharing power-on mode, the corresponding switch device is controlled to be turned on every first preset time according to the preset switch device turn-on sequence; the first preset time is greater than the duration of maintaining the maximum power consumption of each PCIE device in the starting process.

[0092] Optionally, the power-on control module 403 is specifically used for:

[0093] When the first preset signal value corresponds to the functional split power-on mode, the switch device is controlled to be turned on every second preset time according to the preset switch device turn-on sequence; the second preset time is greater than the time for the host device to allocate hard disk drive letters to the PCIE devices.

[0094] Optionally, the apparatus can further include:

[0095] The power-on sequence determination module is configured to obtain a second preset signal value for setting the split power-on sequence before the switch devices are controlled to be turned on in sequence according to the target split power-on mode, and determine the switch device turn-on sequence according to the second preset signal value.

[0096] Optionally, the first signal value obtaining module 402 can include:

[0097] The first obtaining sub-module is configured to read the first preset signal value from the dial switch or the designated register;

[0098] Correspondingly, the power-on sequence determination module can include:

[0099] The second obtaining sub-module is configured to read the second preset signal value from the dial switch or the designated register;

[0100] Optionally, the power-on control module 403 is specifically configured to:

[0101] When the first preset signal value does not correspond to any split power-on mode, all the switch devices are controlled to be turned on at the same time to control the PCIE devices to be normally started.

[0102] Optionally, the switch device is a MOS tube, and the disconnection control module 401 can include:

[0103] The signal maintaining sub-module is configured to maintain the voltage output to the MOS tube as a first preset value to control the MOS tube to be kept disconnected;

[0104] Correspondingly, the power-on control module 403 can include:

[0105] The signal adjusting sub-module is configured to adjust the voltage output to the MOS tube as a second preset value according to the target split power-on mode to control the MOS tube to be turned on.

[0106] Please refer to Figure 5 , Figure 5 A structural block diagram of a power-on control system provided by an embodiment of the application, which can include: a CPLD 501, switch devices 502, a power supply 503, and PCIE devices 504, the CPLD 501 is connected with the switch devices 502, each switch device 502 is arranged in a power supply path between the power supply 503 and the PCIE devices 504, wherein,

[0107] CPLD, configured to perform the power-on control method as described above.

[0108] Since the embodiments of the power-on control system part correspond to the embodiments of the power-on control method part, the embodiments of the power-on control system part are described in the description of the embodiments of the power-on control method part, and are not described here again.

[0109] Optionally, the switch device 502 can be a MOS tube.

[0110] The embodiments of the present application also provide a computer readable storage medium, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the steps of the power-on control method of any of the above embodiments.

[0111] Since the embodiments of the computer readable storage medium part correspond to the embodiments of the power-on control method part, the embodiments of the storage medium part are described in the description of the embodiments of the power-on control method part, and are not described here again.

[0112] The embodiments in the description are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0113] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or combination of the two. In order to clearly show the interchangeability of hardware and software, the components and steps of each example are described in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0114] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, software module executed by a processor, or combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0115] The above describes in detail the power-on control method, device, system and computer readable storage medium provided by the present application. The principles and implementation modes of the present application are described by applying specific examples, and the above description of the examples is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A power-on control method, characterized by, The method is applied to a CPLD connected with switch devices, each of the switch devices is arranged in a power supply path between a power supply and each PCIE device, and the method comprises the following steps: controlling all the switch devices to keep off, so as to control each of the power supply paths to be off; when a start-up signal is detected, acquiring a first preset signal value for setting a time-sharing power-on mode; determining a target time-sharing power-on mode according to the first preset signal value, and controlling each of the switch devices to be on in turn according to the target time-sharing power-on mode, so as to control PCIE devices connected with each of the switch devices to start up in turn; the step of determining a target time-sharing power-on mode according to the first preset signal value, and controlling each of the switch devices to be on in turn according to the target time-sharing power-on mode comprises the following steps: when it is determined that the first preset signal value corresponds to a power consumption type time-sharing power-on mode, controlling a corresponding switch device to be on every first preset time according to a preset switch device on sequence; the first preset time is greater than a duration of maintaining maximum power consumption of each of the PCIE devices in a start-up process; when it is determined that the first preset signal value corresponds to a functional time-sharing power-on mode, controlling a corresponding switch device to be on every second preset time according to a preset switch device on sequence; the second preset time is greater than a time of assigning a hard disk drive letter to each of the PCIE devices by a host device; when it is determined that the first preset signal value does not correspond to any of the time-sharing power-on modes, controlling all the switch devices to be on at the same time, so as to control each of the PCIE devices to start up normally; the step of acquiring a first preset signal value for setting a time-sharing power-on mode comprises the following step: reading the first preset signal value from a dial switch or a specified register.

2. The power-on control method of claim 1, wherein Before the step of controlling each of the switch devices to be on in turn according to the target time-sharing power-on mode, the method further comprises the following steps: acquiring a second preset signal value for setting a time-sharing power-on sequence, and determining the switch device on sequence according to the second preset signal value.

3. The power-on control method according to claim 2, wherein the step of acquiring a second preset signal value for setting a time-sharing power-on sequence comprises the following step: reading the second preset signal value from a dial switch or a specified register. The switch devices are MOS transistors, and the step of controlling all the switch devices to keep off comprises the following step:

4. The power-on control method of claim 1, wherein keeping a voltage output to the MOS transistors as a first preset value, so as to control the MOS transistors to keep off; Correspondingly, the step of controlling each of the switch devices to be on in turn according to the target time-sharing power-on mode comprises the following step: adjusting the voltage output to each of the MOS transistors as a second preset value in turn according to the target time-sharing power-on mode, so as to control the MOS transistors to be on. The device is applied to a CPLD connected with switch devices, each of the switch devices is arranged in a power supply path between a power supply and each PCIE device, and the device comprises the following modules:

5. A power-up control device, characterized by comprising: an off control module, configured to control all the switch devices to keep off, so as to control each of the power supply paths to be off; a first signal value acquisition module, configured to acquire a first preset signal value for setting a time-sharing power-on mode when a start-up signal is detected; a target time-sharing power-on mode determination module, configured to determine a target time-sharing power-on mode according to the first preset signal value, and control each of the switch devices to be on in turn according to the target time-sharing power-on mode, so as to control PCIE devices connected with each of the switch devices to start up in turn. The power-on control module is configured to determine a target time-sharing power-on mode according to the first preset signal value, and sequentially control the switch devices to be turned on according to the target time-sharing power-on mode, so as to sequentially control the PCIE devices connected to the switch devices to be powered on and started; The power-on control module is configured to: When it is determined that the first preset signal value corresponds to the power consumption type time-sharing power-on mode, the corresponding switch device is controlled to be turned on every first preset time according to a preset switch device turn-on sequence; the first preset time is greater than a duration in which each PCIE device maintains maximum power consumption during a starting process; When it is determined that the first preset signal value corresponds to the functional time-sharing power-on mode, the corresponding switch device is controlled to be turned on every second preset time according to a preset switch device turn-on sequence; the second preset time is greater than a time in which a host device allocates a hard disk drive letter to each PCIE device; When it is determined that the first preset signal value does not correspond to any time-sharing power-on mode, all switch devices are controlled to be turned on at the same time, so as to control each PCIE device to be normally started; The first signal value acquisition module comprises: A first acquisition sub-module configured to read the first preset signal value from a dial switch or a specified register.

6. A power-up control system, comprising: Comprise: A CPLD, switch devices, a power supply and PCIE devices, the CPLD is connected with the switch devices, each switch device is arranged in a power supply path between the power supply and each PCIE device, wherein, The CPLD is configured to execute the power-on control method according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions, and when the computer executable instructions are loaded and executed by the processor, the power-on control method according to any one of claims 1 to 4 is realized.

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