A high-precision, low-latency large integer division acceleration device based on redundancy

Abstract

The present invention provides a high-precision, low-latency large integer division acceleration device based on redundancy, which includes an RSD preprocessing module, a subtraction-like coding module, an RSD multiplier, and a truncation module. The RSD preprocessing module is used to normalize the input redundant numbers to meet the algorithm requirements, the subtraction-like coding module is used to use simple coding to quickly implement a large number subtraction operation, the RSD multiplier is used to achieve a fast product of two redundant numbers, and the order truncation module is used to truncate the high bits of the first half of the result of the RSD multiplier to facilitate the reuse of the RSD multiplier. The underlying adder used in the entire device is a redundant adder, which shortens the delay and significantly reduces the overall total operation time.

Description

Technical Field

[0001] The present invention relates to a large integer division device and a modulus taking device with a non-fixed modulus in the field of cryptography technology, and in particular to a high-precision, low-latency large integer division acceleration device based on redundancy. Background Art

[0002] With the continuous advancement of computer technology, issues related to network information security continue to emerge. Currently, the core operation for ensuring network security is the encryption of network-related data. In cryptography and its field, many proven algorithms have been proposed and published to meet the requirements of different application environments, such as elliptic curve cryptography (ECC) and RSA in the field of public key cryptography. These algorithms have been widely used in technologies such as blockchain and security chips to enhance security. To meet the corresponding security requirements, related encryption and decryption technologies require mathematical operations such as addition, subtraction, multiplication, division, and modulo calculations to be performed with word lengths of 512 or 1024 bits. For example, the RSA cryptographic algorithm, based on the difficulty of factoring large integers, obtains the modulus n by multiplying two large prime numbers p and q. In the modulus n operation, the public key exponent e and the private key exponent d are used to perform the corresponding encryption and decryption processes.

[0003] Currently, a class of functions called Verifiable Delay Functions (VDFs) is widely used and rapidly developing in many decentralized systems. Their core principle is that the computational process must sequentially execute a specified number of steps, and the verification process must be fast. VDFs pose a risk if an attacker can compute significantly faster than the average user. Therefore, to ensure the security of related applications, their rapid implementation needs to be publicly available. Numerous studies have explored optimizations at the algorithmic and architectural levels. For example, a VDF over a quadratic domain class group (reference: ZHU D, SONG Y, TIAN J, et al. An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group [C] / / 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). 2020: 137-140) accelerates the square operation during computation from an algorithmic optimization perspective. However, at the hardware level, the above solutions and the aforementioned modulo operations all involve division. The current implementation of large number division is very complex. The long critical path and many iteration cycles lead to slow calculation speed, which has become a major factor affecting the efficiency of the algorithm.

[0004] Considering the above, a hardware implementation of large number division can further optimize most modern cryptographic systems.

[0005] Existing division operation schemes can be roughly divided into three types:

[0006] The first type: digital loop algorithms. These algorithms originate from manual calculations, where the remainder is used to determine the quotient. Therefore, the number of cycles is linearly related to the number of digits in the quotient. The SRT division algorithm is a widely used, representative digital loop algorithm, and improvements have been proposed for different application environments. However, since these algorithms only obtain a single digit of precision in the quotient at each iteration, convergence is very slow when operating on numbers with large bit widths.

[0007] The second method is based on Newton iteration. Newton iteration is also known as Newton-Raphson algorithm. It is the earliest and most widely used iterative algorithm. For the division operation N / D, it can be converted to first find the reciprocal of the divisor that meets the accuracy requirements, that is, 1 / D, and then multiply it by the dividend N to get the final result: N*(1 / D). The reciprocal part is based on the function The method of finding the zero point is to use the iterative formula x under the condition of quadratic convergence i+1 =x i (2-Dx i ) to find the required reciprocal value. To ensure convergence, the input number needs to be preprocessed so that it satisfies the range (0.5, 1]. At the same time, an approximate algorithm (reference: Lunglmayr M, Ploder O. Fast approximate reciprocal approximation s for iterative algorithms [J]. arXiv preprint arXiv:2007.06241, 2020) can provide a suitable initial value to reduce the iteration cycle, that is, x0 = 3–2*D. The algorithm is as follows:

[0008] Algorithm 1: Newton Raphson algorithm

[0009] Input:D∈(0.5,1]

[0010] 1: Initialize:x0←3–2*D

[0011] 2: for i = 0 to k do

[0012] 3:a←D*x i

[0013] 4:x i+1 ←x i*(2-a)

[0014] 5:end for

[0015] 6:Return x i+1 →1 / D

[0016] Output: 1 / D∈[1,2)

[0017] Compared with digital loop algorithms, this algorithm only requires log2W iterations and some additional operations to complete the division operation (W is the bit width of the divisor, the same below). Therefore, this algorithm is suitable for low-latency design of large numbers. At the same time, each iteration involves two multiplication operations. The hardware resources and operation speed depend on the multiplication operation part.

[0018] The third method is the division operation based on the Goldschmidt algorithm. Based on the Taylor expansion formula of the function 1 / (1+x) at point 0: 1 / (1+x) = 1-x+x 2 -x 3 +x 4 -x 5 +…=(1-x)(1+x 2 )(1+x 4 )(1+x 8 )…, process the input divisor D so that it satisfies the range (0.5,1], and simply set D = 1 + x (in this case |x| < 1), and we can get:

[0019]

[0020] For D0=D=1+x, F0=2–D=1-x, N0=N, we observe

[0021] D1=D0*F0=1-x 2 ,F1=2–D1=1+x 2 ;

[0022] D2=D1*F1=1-x 4 ,F2=2–D2=1+x 4 ;

[0023] …

[0024]

[0025] So the denominator can be written as i+1 =D i *(2-D i )=D i *F i , the numerator can be written as N i+1 =N i *(2-D i)=N i *F i As i increases, the numerator in formula (1) approaches 1, while the denominator approaches N / D, which is the final quotient. The algorithm is as follows:

[0026] Algorithm 2: Goldschmidt algorithm

[0027] Input:D∈(0.5,1]

[0028] 1:Initialize:D0←D,F0←2-D,N0←N

[0029] 2: for i = 0 to k do

[0030] 3:D i+1 ←D i *F i

[0031] 4:N i+1 ←N i *F i

[0032] 5:F i+1 ←2-D i+1

[0033] 6:end for

[0034] 7:Return N i+1 →N / D

[0035] Output: N / D

[0036] This algorithm, similar to the Newton-Schmidt algorithm, converts a division operation into two multiplication operations, resulting in approximately log2W iterations. Compared to the Newton-Schmidt algorithm, its advantages are that it can directly calculate the final quotient, and the two multiplication operations are independent and can be run in parallel, making it more hardware-friendly. However, its disadvantage is that if an error occurs during the iteration, the error will not be automatically updated, making it highly dependent on the accuracy of the calculations during the process. Summary of the Invention

[0037] Purpose of the invention: In order to solve the problem that the current large number division device based on functional iteration involves multiplication and subtraction operations during iteration, and the multiplication and subtraction operations can be converted into addition and shift operations, and the delay of the addition operation increases sharply with the input bit width, resulting in low overall calculation speed and long running time, the present invention provides a high-precision and low-latency large integer division acceleration device based on redundancy. The data format of the present invention adopts the representation form of redundant signed numbers (redundant-signed-digit, abbreviated as RSD), and the device includes an RSD preprocessing module, a first data selector, a second data selector, a subtraction-like encoding module, a first RSD multiplier module, a second RSD multiplier module, a first truncation module, a second truncation module, a first register, a second register and a shift register;

[0038] The RSD preprocessing module is used to preprocess the input divisor to obtain a data type D that meets the requirements of the functional iteration algorithm (such as the Goldschmidt algorithm). norm , that is, D norm The value of is greater than 0 and less than 1, and the most significant bit n D , D norm Output to the first data selector, n D Output to shift register;

[0039] The first data selector is used to obtain the output D in the RSD preprocessing module according to the control signal norm and the data stored in the first register to obtain an iterative divisor (the data stored in the first register is the result obtained by the first truncation module, and the output of the preprocessing module is the initial input, and the data stored in the first register is the input during iteration, so it does not affect the loop function), and output it to the subtraction-like coding module and the first RSD multiplier module;

[0040] The second data selector is used to select between the dividend of the input and the data stored in the second register according to the control signal to obtain the iterative dividend (the data stored in the second register is the result obtained by the second truncation module, and the dividend of the input is the initial input, and the data stored in the second register is input in the iteration, therefore does not affect the loop function), and output to the second RSD multiplier module;

[0041] The subtraction-like encoding module is used to encode the iterative divisor in a redundant form by two subtractions to obtain a common multiplier parameter and output it to the first RSD multiplier module and the second RSD multiplier module;

[0042] The first RSD multiplier module is used to implement the multiplication operation of the common multiplier and the iterative divisor under the W-bit redundant number, and output it to the first truncation module;

[0043] The second RSD multiplier module is used to implement the multiplication operation of the common multiplier and the iterative dividend under the W-bit redundant number, and output it to the second truncation module;

[0044] The first truncation module is used to truncate the high W bits of the 2W-bit redundant number output by the first RSD multiplier module to obtain a new W-bit redundant number and output it to the first register;

[0045] The second truncation module is used to truncate the high W bits of the 2W-bit redundant number output by the second RSD multiplier module to obtain a new W-bit redundant number and output it to the second register and the shift register;

[0046] The input end of the first register is connected to the output end of the first truncation module, and the output end of the first register is connected to the input end of the first data selector;

[0047] The input end of the second register is connected to the output end of the second truncation module, and the output end of the second register is connected to the input end of the second data selector;

[0048] The shift register is used to right-shift the result obtained by the second truncation module, and the right shift number is twice the difference between the input bit width W and the most significant bit obtained by the RSD pre-processing module to obtain the final quotient value.

[0049] The RSD preprocessing module includes a precoding module, a coding mapping module, a most significant bit detection (Leading One Detector, LOD) module, a detection module, a data selector and an internal shift register;

[0050] The precoding module is used to precode the input redundant number D using an existing coding module (reference: Peter Kornerup. Correcting the normalization shift of redundant binary 622 representations. IEEE Transactions on Computers, 58(10): 1435–1439, 2009) to obtain detection tree parameters a, b, c and LOD parameter F, and output the detection tree parameters a, b, c to the detection module, and output the LOD parameter F to the most significant bit detection module;

[0051] The encoding mapping module is used to map the input redundant number D into a value that is the same as the input actual value but with all redundant bits before the most significant bit being 0, and then output it to the internal shift register.

[0052] The most significant bit detection module is used to find the most significant position of the input using a most significant bit detector LOD, and then output it to the data selector.

[0053] The detection module is used to detect deviations using a tree-like simplified structure (reference: J.D. Brunguera and T. Lang, "Leading-one prediction with concurrent position correction," in IEEE Transactions on Computers, vol. 48, no. 10, pp. 1083-1097, Oct. 1999). If a deviation exists, the output is 1, otherwise 0. The output of the detection module serves as the control end of the data selector.

[0054] The data selector is used to select between the output of the most significant bit detection module and the number obtained by subtracting one from the output of the most significant bit detection module according to the result 0 / 1 of the detection module, and obtain the correct most significant bit n D As the final output and output to the internal shift register.

[0055] The internal shift register is used to left-shift the result of the encoding mapping module to obtain the final normalized result, and the left shift number is the most significant bit obtained by the data selector.

[0056] The subtraction coding module is used to process the input number I of W redundant bits, and the bit-level data format is recorded as in is the first bit of the first redundant bit of I, is the second bit of the first redundant bit of I, is the first bit of the second redundant bit of 1, The second bit of the second redundant bit of 1, the output number is still W redundant bits, recorded as O, expressed as:

[0057] in,

[0058]

[0059]

[0060]

[0061]

[0062]

[0063] in is the first bit of the first redundant bit of O, The second bit of the first redundant bit of O, The first bit of the second redundant bit of O, The second bit of the second redundant bit is 0.

[0064] The first truncation module and the second truncation module have the same function, and are used to realize fast high-order truncation, that is, to quickly truncate the input of 2W redundant digits (the actual value is in W-1 digits) to W digits correctly without changing the actual value. The truncation rule is: the last W-1 digits of the input are not changed, and the new Wth redundant digit n new , recorded as (A redundant bit consists of two bits), which is determined only by the original W-th redundant bit and W+1-th redundant bit, respectively denoted as n{n + ,n -}and The formula is as follows:

[0065]

[0066]

[0067] The first RSD multiplier module and the second RSD multiplier module have the same structure, and both include a partial product generation module (PPG) and an accumulator. The partial product generation module uses a multiplier a i for When 0 and 1, the partial products are -B, 0, and B respectively, forming each partial product, where -B only requires swapping the corresponding parity bit of the multiplicand B; the accumulator uses a redundant adder (RSDA) under a tree structure to simplify the partial product, and uses the first truncation module to process the overflowed redundant bits.

[0068] The present invention is applicable to the field of modern cryptography, especially to the parameter calculation algorithm of the Verifiable Delay Function (VDF) with high requirements on delay. Therefore, further, the present invention also provides a method for accelerating the calculation of the Verifiable Delay Function (VDF) based on quadratic forms. The modulo operations in the continuous square operation process of the Verifiable Delay Function (VDF) are all implemented by the high-precision, low-latency large integer division acceleration device based on redundancy. The modulo operations involving data with a bit width of 1024 bits and a non-fixed modulus are accelerated at the hardware level. The number to be moduloed and the modulus are input into the device as the dividend and divisor respectively. The quotient output by the device is input into the computer to be multiplied by the modulus, and the product obtained by subtracting the modulus is then used to return the final remainder.

[0069] Beneficial effects: The data format involved in the entire device of the present invention adopts redundant representation, so that the delay of the underlying redundant adder is independent of the bit width. Therefore, when performing complex division operations, the critical path is low. At the same time, based on the Goldschmidt algorithm, the iteration cycle is small, and the total operation time of the entire device is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0071] Figure 1 This is a top-level architecture diagram.

[0072] Figure 2 This is a schematic diagram of the RSD preprocessing module.

[0073] Figure 3 It is a schematic diagram of the encoding mapping module.

[0074] Figure 4 This is the schematic diagram of the RSD multiplier module.

[0075] Figure 5 This is the schematic diagram of the RSD adder. DETAILED DESCRIPTION

[0076] The device in the present invention is a fast implementation of large number division based on the quadratic convergence Goldschmidt algorithm. The focus is on the iterative part of the algorithm. The top-level architecture diagram is given as follows: Figure 1 As shown. The overall data format uses the Redundant Signed Digit (RSD) representation, that is, a signed number can be represented by subtracting two unsigned numbers: where a i + 、a i - ∈{0, 1}, is the bit, It is a redundant bit.

[0077] Based on the above description, several key functional modules of the present invention are now introduced:

[0078] (1) RSD preprocessing module

[0079] For the Goldschmidt algorithm, in order to meet the convergence requirements, the input operand D0 needs to be preprocessed to satisfy the (0.5, 1] between. In the general form, only a leading one detector (LOD) is needed to calculate the most significant bit position n of the divisor D. D (The right side is the low bit), shift the divisor D left by WnD bits (W is the divisor bit width) can get the input D0 that meets the requirements, and its highest bit is 1.

[0080] Due to the particularity of redundant representation itself, a number with multiple significant digits can be used to represent a number with fewer actual significant digits, for example The actual value represented is 000011 (obviously the outputs after LOD are different), so the redundant representation needs to be converted into a normal form. However, this solution involves a conventional subtraction operation, which will lose its superiority in large number systems. Therefore, we borrow the existing solution for normalization operation in floating-point subtraction operation (reference: Peter Kornerup. Correcting the normalization shift of redundant binary622representations. IEEE Transactions on Computers, 58(10): 1435–1439, 2009) and make some improvements to reduce the critical path from a W-bit normal subtraction and most significant bit detection module to a single most significant bit detection module. The architecture is shown in Figure 2 These include:

[0081] 1. The precoding module is used to precode the input positive redundant divisor D (the encoding form is shown in the reference) to obtain the input of the detection module and the most significant bit detection module.

[0082] 2. The encoding mapping module is used to re-encode the input positive redundant divisor D so that the redundant bits before the most significant bit corresponding to the actual value of the divisor are all 0, such as Encoded As the input of the last shift register, the encoding structure is shown in Figure 3 .

[0083] 2. The Leading One Detector (LOD) module uses the existing LOD to find the most significant position n of the result after encoding in 1). t .

[0084] 3. Detection Module. As in this example, the actual value is 000011, and the corresponding most significant bit should be 2. However, 2) returns 3, indicating a one-bit deviation. This module uses the simplified tree structure described in the literature (J.D. Brunguera and T. Lang, "Leading-one prediction with concurrent position correction," in IEEE Transactions on Computers, vol. 48, no. 10, pp. 1083-1097, Oct. 1999) to detect this deviation and facilitate correction. If a deviation exists, the output is 1, otherwise it is 0.

[0085] 4. Two-choice data selector, using the result 0 / 1 of the detection module to detect the output n of the most significant bit of the module t and n t -1 and get the correct most significant bit n.

[0086] 5. Shift register, shift according to the value of the structure of the data selection module to obtain the final normalized redundant number D norm .

[0087] (2) Class reduction coding module

[0088] From Algorithm 2, we know that the iterative calculation involves a subtraction operation 2-D i+1 , when using this device, D i+1 is a redundant number, so a redundant subtractor can be used directly to perform this step. i+1 The actual value of the highest bit is 0, so it can be replaced by a 4-bit encoder to reduce the area. The encoding rules are as follows:

[0089] For the input number I of W redundant bits, that is, (Data storage form), the output number is still W-bit redundant number, recorded as O, that is in,

[0090]

[0091]

[0092]

[0093]

[0094]

[0095] (3) Fast high-level cutoff module

[0096] In hardware design, multipliers are reused during iterations, ensuring data bit width consistency. Therefore, truncation of the multiplier output is necessary. Considering that the remaining data bits are precision bits, truncation can be performed directly as long as the algorithm is correct. However, due to the aforementioned peculiarities of redundant representation, it is impossible to truncate the excess bits that actually correspond to zero bits. Therefore, a special truncation module is required to quickly process the high-order bits.

[0097] For redundant numbers that are actually within W-1 bits, no matter how many valid redundant bits are in front, when they are truncated to W bits, only a simple operation is required, that is, the last W-1 bits are unchanged, and the new W+1 redundant bits are recorded as It is only determined by the original Wth redundant bit and W+1 redundant bit, which are respectively denoted as n{n + ,n -}and The formula is as follows:

[0098]

[0099]

[0100] Specific examples are shown in Table 1:

[0101] Table 1

[0102]

[0103] (4)RSD multiplier module

[0104] In circuit design, a common multiplication operation mainly includes two steps: 1) generating partial products; 2) adding the partial products together using a fast ripple-carry adder (CPA) using a tree structure.

[0105] The first step is relatively simple, but the second step will cause the critical path to become longer as the bit width increases, resulting in a significant computational delay. Considering that the multiplication operation has always used redundant signed number representations in the iterative process of the present invention, the second step can be accelerated by utilizing its "carry-free" addition property without converting to a common format. The critical path can be reduced by pipelining and other operations at appropriate locations. The modified architecture is shown in the following figure. Figure 4 The RSD multiplier module mainly includes:

[0106] 1. Partial product generator (PPG), using a i for When , the partial products are -B, 0, and B, respectively, to form the partial products, where -B only requires the parity bits of B to be swapped accordingly.

[0107] 2. Accumulator (RSD adder, RSDA), using a tree structure to simplify the partial product, which uses redundant adders for accumulation, see Figure 5 .

[0108] In order to avoid uneven increase in the number of bits in the accumulation process, the fast high-bit truncation module in (2) is used.

[0109] Example

[0110] Take the large number division operation involved in the VDF algorithm implementation as an example. Considering that the divisor is the same for multiple division operations in the algorithm, simply setting N in this architecture to 1 allows the reciprocal of the divisor to be calculated. This reciprocal is then multiplied by the corresponding dividend using the used multiplier, and the product is the corresponding quotient.

[0111] The 2048-bit / 1024-bit division operation architecture is synthesized using the TSMC 28nm CMOS process library. The results are shown in Table 2 below:

[0112] Table 2

[0113]

[0114] The results show that the critical path of the architecture is 1.05ns and the single operation delay is 86.1ns.

[0115] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium is capable of storing a computer program that, when executed by the data processing unit, can run the invention content of a high-precision, low-latency large integer division acceleration device based on redundancy provided by the present invention and some or all of the steps in each embodiment. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0116] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, in essence or in other words, the part that contributes to the prior art, can be embodied in the form of a computer program, i.e., a software product. The computer program software product can be stored in a storage medium and includes several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, a MUU, or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0117] The present invention provides a high-precision, low-latency, large-integer division acceleration device based on redundancy. There are numerous methods and approaches for implementing this technical solution. The foregoing is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be considered within the scope of protection of the present invention, including but not limited to specific types of redundant representation, multiplier splitting and multiplexing, and specific algorithms for function iteration. Any components not specified in this embodiment can be implemented using existing technologies.

Claims

1. A high-precision, low-latency large integer division acceleration device based on redundancy, wherein the data format adopts the representation of redundant signed numbers RSD, characterized in that: It includes an RSD preprocessing module, a first data selector, a second data selector, a subtraction-like coding module, a first RSD multiplier module, a second RSD multiplier module, a first truncation module, a second truncation module, a first register, a second register and a shift register; The RSD preprocessing module is used to preprocess the input divisor to obtain a data type D that meets the requirements of the functional iteration algorithm. norm , that is, D norm The value of is greater than 0 and less than 1, and the most significant bit n D , D norm Output to the first data selector, n D Output to shift register; The first data selector is used to obtain the output D in the RSD preprocessing module according to the control signal norm and the data stored in the first register to obtain an iterative divisor, and output it to the subtraction-like encoding module and the first RSD multiplier module; The second data selector is used to select between the input dividend and the data stored in the second register according to the control signal to obtain an iterative dividend, and output it to the second RSD multiplier module; The subtraction-like encoding module is used to encode the iterative divisor in a redundant form by two subtractions to obtain a common multiplier parameter and output it to the first RSD multiplier module and the second RSD multiplier module; The first RSD multiplier module is used to implement the multiplication operation of the common multiplier and the iterative divisor under the W-bit redundant number, and output it to the first truncation module; The second RSD multiplier module is used to implement the multiplication operation of the common multiplier and the iterative dividend under the W-bit redundant number, and output it to the second truncation module; The first truncation module is used to truncate the high W bits of the 2W-bit redundant number output by the first RSD multiplier module to obtain a new W-bit redundant number and output it to the first register; The second truncation module is used to truncate the high W bits of the 2W-bit redundant number output by the second RSD multiplier module to obtain a new W-bit redundant number and output it to the second register and the shift register; The input end of the first register is connected to the output end of the first truncation module, and the output end of the first register is connected to the input end of the first data selector; The input end of the second register is connected to the output end of the second truncation module, and the output end of the second register is connected to the input end of the second data selector; The shift register is used to right-shift the result obtained by the second truncation module, and the right shift number is twice the difference between the input bit width W and the most significant bit obtained by the RSD pre-processing module to obtain the final quotient value.

2. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 1, characterized in that: The RSD preprocessing module includes a precoding module, a coding mapping module, a most significant bit detection module, a detection module, a data selector and an internal shift register; The precoding module is used to precode the input redundant number D to obtain detection tree parameters a, b, c and LOD parameter F, and output the detection tree parameters a, b, c to the detection module, and output the LOD parameter F to the most significant bit detection module.

3. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 2, characterized in that: The encoding mapping module is used to map the input redundant number D into a value that is the same as the input actual value but with all redundant bits before the most significant bit being 0, and then output it to the internal shift register.

4. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 3, characterized in that: The most significant bit detection module is used to find the most significant position of the input using a most significant bit detector LOD, and then output it to the data selector.

5. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 4, characterized in that: The detection module is used to detect deviations using a tree-type simplified structure, and outputs 1 if a deviation exists, otherwise 0. The output end of the detection module serves as the control end of the data selector.

6. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 5, characterized in that: The data selector is used to select between the output of the most significant bit detection module and the number obtained by subtracting one from the output of the most significant bit detection module according to the result 0 / 1 of the detection module, and obtain the correct most significant bit n D As the final output and output to the internal shift register.

7. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 6, characterized in that: The internal shift register is used to left-shift the result of the encoding mapping module to obtain the final normalized result, and the left shift number is the most significant bit obtained by the data selector.

8. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 7, characterized in that: The subtraction coding module is used to process the input number I of W redundant bits, and the bit-level data format is recorded as in is the first bit of the first redundant bit of I, is the second bit of the first redundant bit of I, is the first bit of the second redundant bit of 1, The second bit of the second redundant bit of 1, the output number is still W redundant bits, recorded as O, expressed as: in, in is the first bit of the first redundant bit of O, The second bit of the first redundant bit of O, The first bit of the second redundant bit of O, The second bit of the second redundant bit is 0.

9. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 8, characterized in that: The first truncation module and the second truncation module have the same function and are used to realize fast high-order truncation, that is, to quickly truncate the input of 2W redundant digits to W digits without changing the actual value. The truncation rule is: the last W-1 digits of the input are unchanged, and the new Wth redundant digit n is new , recorded as It is determined only by the original Wth redundant bit and W+1th redundant bit, which are denoted as n{n + ,n - }and The formula is as follows:

10. The high-precision, low-latency, large-integer division acceleration device based on redundancy according to claim 9, characterized in that: The first RSD multiplier module and the second RSD multiplier module have the same structure and both include a partial product generation module and an accumulator. The partial product generation module uses the multiplier a i for When 0 and 1, the partial products are -B, 0, and B respectively, forming each partial product, where -B only requires swapping the corresponding parity bit of the multiplicand B; the accumulator uses a redundant adder under a tree structure to simplify the partial product, and uses the first truncation module to process the overflowed redundant bits.

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