Method for Establishing a Wafer Chip Model Based on a Wafer Size with a Special Decimal Point

Abstract

The present application relates to a method for establishing a wafer chip model based on the wafer size with a special decimal point, including: providing a wafer image, which is divided into multiple chip regions, and the size specifications of the chip regions have a special decimal point; determining the coordinate position of the center point of the wafer image; calculating a reference area based on the rounding error formed by the special decimal point; scanning the wafer based on the reference area; and establishing a wafer chip model. By adopting the above technical solution, since the reference area is calculated based on the rounding error generated by the special decimal point of the chip size, there will be no large rounding error when the chip regions in the reference area are automatically established, thus avoiding the probe station error reporting situation caused by the error.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor device testing, and particularly to a method for establishing a wafer chip model based on a wafer size with a special decimal point. Background Art

[0002] In semiconductor manufacturing processes, there are tens of thousands of devices on a single wafer. Each device occupies a certain-sized area (chip size, wafer size) on the wafer. The device is tested by contacting its surface with a probe to determine whether the device is qualified.

[0003] In the prior art, the wafer size is usually a positive integer, such as 1571um * 1311um, which does not include a decimal point. At the same time, when a conventional probe station scans the wafer surface, the minimum size it can recognize is 1um, that is, the wafer size and the recognition accuracy of the probe station are of the same order of magnitude and are mutually adapted.

[0004] With the upgrading of chip manufacturing processes, wafer sizes with decimal points have gradually emerged, such as 1180.8um * 599.4um, resulting in the inability of existing probe stations to recognize the wafer sizes under this manufacturing process or large errors during the scanning process.

[0005] Chinese Patent Publication No. CN103065012A discloses a wafer Map display model and its usage method. By creating a dynamic link library, a wafer Map coordinate model is established, coordinates are assigned to each die, and it is determined whether the coordinate position is within the wafer range to automatically draw small squares representing the die to form a wafer Map. In subsequent processes such as measurement, detection results corresponding to the coordinates are assigned to each die, so that each die can correspond to multiple different detection results through the coordinates, can flexibly adapt to different detection parameters, and has good portability.

[0006] Chinese Patent Publication No. CN103646900A discloses an LED wafer testing method and testing system. After initial calibration, an image of the wafer is taken, and coordinates are assigned to each die to form a wafer map. The wafer map is divided into an outer circle and an inner circle according to the coordinates. Some outer circles are exempt from testing due to natural defects, the inner circle is sampled, and the part between the inner circle and the outer circle is fully tested. By optimizing the judgment method, frequent calibration is avoided, and the production capacity of the Mapping tester is improved. Summary of the Invention

[0007] Based on this, it is necessary to provide a method for establishing a wafer chip model based on a wafer size with a special decimal point to address the error problem caused by insufficient recognition accuracy of some probe stations.

[0008] A method for establishing a wafer chip model based on the wafer size with a special decimal point, comprising: providing a wafer image, the wafer image being divided into a plurality of chip regions, and the size specifications of the chip regions having a special decimal point; determining the coordinate position of the center point of the wafer image; calculating a reference region based on the rounding error formed by the special decimal point; scanning the wafer based on the reference region; and establishing a wafer chip model.

[0009] By adopting the above technical solution, since the reference region is calculated based on the rounding error generated by the special decimal point in the chip size, the chip regions within the reference region will not generate a large rounding error during automatic establishment, thereby avoiding the probe station reporting errors due to the error.

[0010] In one embodiment, the specific steps of calculating the reference region include: processing the special decimal point based on the counting retention method to determine the resulting rounding error; dividing the maximum scanning error allowed by the probe station by the rounding error to determine the number of chips to be scanned; and forming the reference region with the center point as the origin based on half of the number of chips to be scanned.

[0011] By adopting the above technical solution, dividing the maximum scanning error allowed by the probe station by the rounding error, the resulting reference region can not only ensure that the cumulative rounding error of the chip regions does not exceed the maximum scanning error, but also enable the reference region to have a larger area, reducing the chip regions that need to be manually divided in the non-reference region.

[0012] In one embodiment, the reference region is circular, and the radius of the reference region is greater than the sum of the sizes of half of the number of chips to be scanned in the x-axis direction and greater than the sum of the sizes of half of the number of chips to be scanned in the y-axis direction.

[0013] By adopting the above technical solution, limiting the radius range of the reference region and further determining the boundary position of the reference region can better define the position of the reference region and prevent the rounding error generated by the chip regions within the reference region from exceeding the maximum allowable error.

[0014] In one embodiment, the special decimal point is between 0.2 and 0.8.

[0015] By adopting the above technical solution, when the special decimal point is between 0.2 and 0.8, the error generated by using technical retention methods such as rounding is relatively large, and it is relatively more urgent to use this method to process the wafer. When the special decimal point is not within this range, the cumulative error generated may not be sufficient to cause the probe station to report an error, and no processing is required.

[0016] In one embodiment, in the step of determining the coordinate position of the center point of the wafer image, enter the wafer image interface multiple times, and record the initial coordinate position when entering the interface as the center point.

[0017] By adopting the above technical solution, when entering the wafer image interface multiple times, record the initial coordinate position when entering the interface each time, so as to confirm that this position is the center point, improve the accuracy of the center point, and further improve the accuracy of subsequent reference position setting.

[0018] In one embodiment, the scanning of the wafer specifically includes the steps of: scanning the wafer within the reference area along the x-axis direction and the y-axis direction respectively to obtain the chip images within the reference area; judging whether the error of the chip images within the reference area is less than the maximum scanning error.

[0019] By adopting the above technical solution, after the reference position is set, confirm whether the error between the size of the chip image and the designed chip size is less than the maximum scanning error during the re-scanning, so as to ensure that there will be no situation where subsequent processing processes cannot be carried out due to large errors.

[0020] In one embodiment, the establishment of the wafer chip model specifically includes the steps of: automatically establishing a chip model within the reference area; establishing a complete chip model on the entire wafer along the outer contour of the chip model within the reference area.

[0021] By adopting the above technical solution, the chip model within the reference area can be automatically established by the probe station after the scanning process. For the chip model located outside the reference area, along the outer contour of the reference area, according to the established chip model, the chip model can be continued to be established automatically or manually until the complete chip model is completed.

[0022] In one embodiment, the scanning accuracy of the probe station is 1um.

[0023] By adopting the above technical solution, even if the scanning accuracy of the probe station is not sufficient to support the chip size with special decimal points, it is still possible to establish a wafer model that meets the maximum error standard.

[0024] In one embodiment, the wafer is a 12-inch wafer.

[0025] By adopting the above technical solution, after the wafer size is increased from 6 inches and 8 inches to 12 inches, the original probe station cannot be upgraded synchronously, and it is still possible to establish a chip model on the 12-inch wafer through the method of the present application.

[0026] The present application also provides a wafer chip model, which is formed by using the method for establishing a wafer chip model based on a wafer size with a special decimal point as described above.

[0027] In summary, the method for establishing a wafer chip model based on a wafer size with a special decimal point according to the present application has at least one of the following beneficial effects:

[0028] 1. Provide a method for making an old probe station with low detection accuracy match an advanced process technology with high accuracy, and prevent the probe station from reporting an error due to inaccurate matching and thus being unable to establish a wafer chip model.

[0029] 2. By establishing a reference range smaller than the entire wafer area, the dimensional cumulative error between the chip model established within the reference range according to the chip model scanned with low accuracy and the actually established chip model with a special decimal point is less than the maximum allowable error of the probe station, enabling the probe station to automatically compensate for it. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a flowchart of the method for establishing a wafer chip model based on a wafer size with a special decimal point in an embodiment of the present application;

[0031] Figure 2 is a schematic diagram of a reference area in a wafer image in an embodiment of the present application.

[0032] Figure 3 is a schematic diagram of a wafer chip model in a wafer image in an embodiment of the present application.

[0033] Description of the reference numerals:

[0034] 10. Wafer; 11. Reference area; 11A. Radius of the reference area; 11B. Center point; 12. Chip model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] In order to make the above objects, features and advantages of the present application more obvious and understandable, the following detailed description of the specific embodiments of the present application will be made with reference to the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the spirit of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0036] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0037] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0038] In the present application, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0039] In the present application, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0040] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation.

[0041] Please refer to Figure 1 , Figure 1 which shows a processing flowchart of a method for establishing a wafer chip model 12 based on a wafer size with a special decimal point in an embodiment of the present application. The method for establishing a wafer chip model 12 based on a wafer size with a special decimal point includes steps such as providing a wafer image, determining the coordinate position of the center point 11B of the wafer image, calculating the reference area 11, scanning the reference area 11, and establishing the wafer chip model 12. The following will introduce them step by step.

[0042] S1: Provide a wafer image. The scanned wafer image is used for subsequent alignment and testing of the wafer 10 by the probe station. Specifically, a 12-inch wafer 10 with a thickness of about 200 um - 750 um formed by cutting is loaded into the probe station and scanned by a CCD image sensor.

[0043] Please refer to Figure 2 , Figure 2 which is a schematic diagram of the reference area 11 in the wafer image in an embodiment of the present application.

[0044] S2: Determine the coordinate position of the center point 11B of the wafer image. The center point 11B is used as the origin for forming the reference area 11 in subsequent steps. Specifically, when the wafer 10 is loaded on the probe station, each time it enters the scanning interface, the probe station can automatically locate the center position of the wafer 10 and set it as the coordinate origin. When the set position of the center point 11B deviates from the actual center point 11B position of the wafer 10, it will cause the reference area 11 formed with the center point 11B as the origin in the subsequent steps to also deviate, resulting in waste of part of the wafer 10 and the formation of the wafer 10 at some positions that are not suitable for chip sampling, leading to a reduction in the yield of the chips.

[0045] In some embodiments, the coordinate origin initially set when the probe station enters the scanning interface may have errors due to problems such as unstable loading and incomplete reset of the probe station. By repeatedly entering the scanning interface of the wafer 10 multiple times, when the coordinate origin each time entering the scanning interface is the same point, it can be confirmed that this coordinate origin is the center point 11B of the wafer 10.

[0046] S3: Calculate the reference area 11, which is used for subsequent scanning and positioning. Please continue to refer to Figure 2 , before introducing this step, for the convenience of understanding, it is necessary to first define and introduce some of the terms and concepts used.

[0047] Special decimal point: The decimal part with an absolute value less than 1 but not equal to 0. The chip size on the wafer 10 is usually described in the form of length multiplied by width. For example, if the chip size is set to 1180.8um * 599.4um, then the special decimal point on the length is 0.8um, and the special decimal point on the width is 0.4um.

[0048] Count retention method: Before performing specific numerical operations, by omitting several last digits of the original value and adjusting the retained last digit to make the finally obtained value closest to the original value, including common methods such as rounding, round half to even, and odd-even rounding.

[0049] Rounding error: It refers to the difference between the approximate value obtained by the operation and the exact value. For example, according to the rounding rule, for 1180.8um, the rounding error is 0.2um, and for 599.4um, the rounding error is 0.4um according to the rounding rule.

[0050] Next, continue to introduce the calculation of the reference area 11.

[0051] Based on the chip area size processed by the count retention method, obtain the rounding error of the target chip area size. The probe station has an automatic error compensation function. However, as the error value increases, the accuracy of the automatic compensation also decreases. To avoid insufficient accuracy of the automatic error compensation, the probe station has a maximum allowable scanning error.

[0052] Divide the maximum allowable scanning error of the probe station by the rounding error to determine the number of chips scanned in a certain direction, so that the cumulative rounding error generated by scanning this number of chips in this direction must be less than or equal to the maximum scanning error, avoiding the cumulative rounding error exceeding the maximum scanning error and causing an error in the later stage and being unable to be automatically compensated.

[0053] Specifically, the chip area is mainly composed of the sizes in two mutually perpendicular directions, namely the x-axis direction and the y-axis direction. Therefore, there will be two corresponding rounding errors and two different sets of scanned chip numbers.

[0054] Specifically in this embodiment, the chip size is 1180.8um * 599.4um, and its rounding errors are 0.2um and 0.4um respectively. The maximum scanning error allowed by the probe station is 50um. Then the number of chips allowed to be scanned in the two directions are 50 / 0.2 = 250 chips and 50 / 0.4 = 125 chips respectively. Select the group with the smaller number of scanned chips, and take half of the sum of the dimensions in the corresponding direction as the radius of the reference area 11. With the center point 11B of the wafer 10 as the center, a reference area 11 for scanning is established. The center of the reference area 11 is the two-dimensional initial coordinate of the wafer 10, that is, (0, 0), and the radius of the reference area 11 is 125 * 599 / 2 ≈ 37438um, which is approximately 1.47 inches. Obviously, if the rounding error of the other side of the chip model 12 is larger, when calculated with the other side, the radius of the reference area 11 is completely inconsistent. The specific calculation of the radius of the reference area needs to be based on the actual rounding error.

[0055] It should be noted that in other embodiments, if the rounding error generated by the special decimal point is small, such as 0.1, 0.05, and the cumulative rounding error generated by directly scanning the wafer 10 comprehensively is also less than 50um. At this time, the method of this application does not need to be used to establish the chip model 12, but the chip model 12 can be directly established after comprehensive scanning.

[0056] S4: Scan the reference area 11. After establishing the reference area 11, it is necessary to scan the inside of the reference area 11 to check whether the size of the reference area 11 meets the expectations.

[0057] The reference area 11 has the same center point 11B as the wafer 10, and the radius is smaller than that of the wafer 10. It is equivalent to scanning the wafer 10 with a smaller virtual wafer 10 area. Specifically in this embodiment, the size of the wafer 10 is 12 inches, but when scanning the reference area 11, the wafer 10 with a size of 8 inches, 6 inches, 4 inches or other sizes can be used according to the specific radius length of the reference area 11. That is, on the 12-inch wafer 10, it is reduced to a wafer 10 with a smaller size for scanning.

[0058] When scanning within the reference area 11, there will still be a rounding error because the scanning accuracy of the probe station is not completely consistent with the actual size of the chip. As long as the sum of the cumulative rounding errors is within the maximum scanning error allowed by the probe station, the probe station can still automatically perform error compensation during scanning.

[0059] It is understandable that even with automatic error compensation, it is still not possible to completely eliminate errors. The main reason is that the scanning accuracy of the probe station itself cannot match the advanced chip manufacturing process. During the upgrade process of the chip manufacturing process, some devices are restricted by issues such as technology blockade and replacement costs, so not all devices can be upgraded synchronously. And this application is precisely under such preconditions, exploring how to use a relatively low-order and backward probe station to achieve a relatively high-order and precise chip manufacturing process. Thus, the problems caused by the insufficient scanning accuracy of the probe station itself can be alleviated and avoided by establishing a reference area 11 and other means, but cannot be completely solved at the root cause.

[0060] S5: Establish a wafer chip model 12. Please refer to Figure 3 , Figure 3 This is a schematic diagram of the wafer chip model 12 in the wafer image in an embodiment of the present application.

[0061] After the scanning is completed, a chip model 12 can be established on the wafer 10. The established chip model 12 has a size of a normal chip model 12 with a special decimal point.

[0062] Specifically, by inputting the specific size and quantity of the chip model 12, the system can automatically generate the chip model 12 on the wafer 10 for subsequent detection and processing processes.

[0063] In some other embodiments, the establishment of the chip model 12 is semi-automatic. That is, when scanning within the reference area 11, part of the chip model 12 is automatically established synchronously. After the scanning is completed, in a manual manner, the chip model 12 is manually established for the wafer 10 located outside the reference area 11. Compared with the completely automatically established chip model 12, the wafer chip model 12 within the reference area 11 is obtained through automatic error compensation and has less error than directly establishing the chip model 12. Of course, outside the reference area 11, manually establishing the wafer chip model 12 is relatively more time-consuming and the labor cost is higher.

[0064] The present application also provides a wafer chip model 12 established by the above method. This wafer chip model 12 uses a probe station with relatively low scanning accuracy to achieve the establishment of a higher-order precision chip model 12.

[0065] The method for establishing the wafer chip model 12 based on the wafer size with a special decimal point in this application has the following implementation principle: When loading the wafer 10 on the probe station, confirm the coordinate position of the center point 11B of the wafer image, and establish a circular reference area 11 with the center point 11B as the center. The radius of the reference area 11 is calculated with reference to the maximum allowable scanning error of the probe station, the approximate size of the chip, and the rounding error caused by the special decimal point. Divide the maximum allowable scanning error by the rounding error to obtain the maximum allowable number of scanned chips, and multiply it by the approximate size corresponding to the chip to calculate the radius of the reference area 11. When scanning within the reference area 11, the cumulative error recognized by the probe station during scanning must be less than the maximum allowable scanning error of the probe station, so no error signal will be generated, enabling the subsequent process to proceed smoothly.

[0066] The significance of this application is that when the chip manufacturing process is upgraded to higher precision, the probe station is restricted by technology blockade and replacement cost and cannot be upgraded to a new device with the same precision synchronously. Under this premise, by setting the reference area 11, it is possible to avoid excessive errors caused by the inconsistent size precision between the probe station and the chip model 12, preventing the probe station from reporting errors and unable to perform subsequent steps such as model establishment. When the scanning range is controlled within the reference area 11, the probe station can still perform automatic error compensation on the chip model 12 within the reference area 11, thereby reducing the error problem caused by inconsistent precision. The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0067] The above-described embodiments only represent several implementation manners of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limitations on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application patent shall be subject to the appended claims.

Claims

1. A method for establishing a wafer chip model based on the wafer size with a special decimal point, characterized in that Including: S1. Provide a wafer image, which is divided into multiple chip regions, and the size specifications of the chip regions have a special decimal point; S2. Determine the coordinate position of the center point of the wafer image; S3. Calculate a reference area based on the rounding error formed by the special decimal point; S4. Scan the reference area; S5. Establish a wafer chip model; Among them, step S2 includes: Based on the counting retention method, process the special decimal point to determine the resulting rounding error; Divide the maximum scanning error allowed by the probe station by the rounding error to determine the number of chips to be scanned; Based on half of the number of chips to be scanned, with the center point as the origin, form the reference area.

2. The method for establishing a wafer chip model based on the wafer size with a special decimal point according to claim 1, wherein The reference area is circular, and the radius of the reference area is greater than the sum of the dimensions of half of the number of chips to be scanned in the x-axis direction and greater than the sum of the dimensions of half of the number of chips to be scanned in the y-axis direction.

3. The method for establishing a wafer chip model based on a wafer size with a special decimal point according to claim 1, wherein, The special decimal point is between 0.2 and 0.

8.

4. The method for establishing a wafer chip model based on a wafer size with a special decimal point according to claim 1, wherein In the step of determining the coordinate position of the center point of the wafer image, enter the wafer image interface multiple times, and record the initial coordinate position of entering the interface as the center point.

5. The method for establishing a wafer chip model based on a wafer size with a special decimal point according to claim 1, characterized in that Step S4 of scanning the reference area includes: Scan the wafer within the reference area along the x-axis direction and the y-axis direction respectively to obtain the chip images within the reference area; Judge whether the error of the chip images within the reference area is less than the maximum scanning error.

6. The method for establishing a wafer chip model based on a wafer size with a special decimal point according to claim 1, wherein Step S5 of establishing a wafer chip model includes: Automatically establish a chip model within the reference area; Establish a complete chip model on the entire wafer along the outer contour of the chip model within the reference area.

7. The method for establishing a wafer chip model based on the wafer size with a special decimal point according to claim 1, wherein The scanning accuracy of the probe station is 1um.

8. The method for establishing a wafer chip model based on the wafer size with a special decimal point according to claim 1, characterized in that The wafer is a 12-inch wafer.

9. A wafer chip model, characterized in that, Formed by using the method for establishing a wafer chip model based on the wafer size with a special decimal point as described in any one of claims 1 to 8.

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