Chip based on chiplet dual-layer stacked package structure
By using the Chiplet dual-layer stacked packaging structure, EMIB interconnect bridges and TSV vias are employed to achieve flexible interconnection between chips, solving the problems of difficult chip expansion and high cost in integrated circuits, and improving data interaction efficiency and chip performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV OF INFORMATION SCI & TECH
- Filing Date
- 2022-09-27
- Publication Date
- 2026-05-22
Smart Images
Figure CN115662979B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to chips with packaged structures, and more particularly to a chip based on a Chiplet dual-layer stacked package structure. Background Technology
[0002] For decades, Moore's Law has charted the course for the semiconductor industry, with each generation of integrated circuits achieving increased transistor density and reduced unit cost, and new silicon process nodes constantly being introduced. However, compared to historical rates, the pace of Moore's Law has slowed. Starting with the 16nm / 14nm nodes, integrated circuit manufacturing costs skyrocketed, the update cycle for a full-scale process node became increasingly longer, and the power consumption, performance, and area gains brought about by semiconductor technology advancements declined. The most advanced chips currently available contain billions of transistors, but chip scaling has become increasingly difficult. Considering that not all circuits need to be designed and manufactured using advanced process nodes, and that not all circuits on the same chip benefit from size scaling, the lower-cost, higher-yield approach of breaking down a large chip into multiple smaller chips and mixing and matching them as needed has emerged.
[0003] Whether it was the era when Moore's Law led the development of integrated circuits, or the current rise of chiplet technology, chip performance, interface, and power consumption are all pursuits of designers and chip manufacturers. How to maximize performance and minimize power consumption within a limited area has always been a key consideration. Summary of the Invention
[0004] Purpose of the invention: The purpose of this invention is to provide a chip based on a Chiplet dual-layer stacked packaging structure that stacks and interconnects functional chips and storage chips to improve data interaction efficiency.
[0005] Technical solution: The chip of the present invention includes a thermally conductive material layer, an upper interposer connection layer, a central processing unit module, a functional module, a lower interposer connection layer, a packaging substrate, and a packaging shell;
[0006] The lower interposer connection layer is connected to the package substrate via the first connection solder ball; the outer side of the package substrate is connected to the external circuit via the first connection solder ball.
[0007] The eight functional modules are located around the central processing unit module. The central processing unit module and the eight functional modules form a "nine-square grid" arrangement and are located between the lower interposer connection layer and the upper interposer connection layer.
[0008] A thermally conductive material layer is provided on the upper interposer connection layer;
[0009] The central processing unit module includes, from top to bottom, an upper CPU chip, a heat insulation layer, and a lower CPU chip. The upper CPU chip is interconnected with the lower CPU chip through a vertical interconnect layer. Each functional module includes, from top to bottom, a storage chip, a heat insulation layer, and a functional chip. The lower functional chip is interconnected with the upper storage chip through a TSV via.
[0010] The upper-layer CPU chip is connected to each memory chip, and to each pair of memory chips, through an upper-layer EMIB interconnect bridge. The lower-layer CPU chip is connected to each functional chip, and to each pair of functional chips, through a lower-layer EMIB interconnect bridge. The upper-layer EMIB interconnect bridge is located in the upper interposer connection layer, and the lower-layer EMIB interconnect bridge is located in the lower interposer connection layer.
[0011] The vertical interconnect layer is connected to the upper EMIB interconnect bridge and the lower EMIB interconnect bridge around the central processing unit module, respectively.
[0012] The thermally conductive material layer, the first connecting solder ball, the upper interposer connection layer, the central processing unit module, the functional module, and the lower interposer connection layer are all located inside the packaging shell.
[0013] Furthermore, the upper-layer EMIB interconnect bridge is distributed between the upper-layer CPU chip and each memory chip; the lower-layer EMIB interconnect bridge is distributed between the lower-layer CPU chip and each functional chip.
[0014] Furthermore, the vertical interconnect layer is distributed around the central processing unit module.
[0015] Furthermore, silicon material is filled between each upper EMIB interconnect bridge in the upper interposer interconnect layer; silicon material is also filled between each lower EMIB interconnect bridge in the lower interposer interconnect layer.
[0016] Furthermore, the TSV vias penetrate the functional chip, the memory chip, and the intermediate thermal insulation layer. Each TSV via is interconnected with the functional chip and the memory chip through a copper injection process. The signals from each TSV via extend upward to the upper EMIB interconnect bridge and downward to the lower EMIB interconnect bridge, respectively, to ensure interconnection between chips in the same layer.
[0017] In the aforementioned chip, the upper and lower CPU chips work simultaneously or in a time-sharing manner. The upper CPU chip is used for global allocation of data resources, while the lower CPU chip is used for instruction translation and transmission.
[0018] It also includes a chip in which neither the central processing unit module nor the functional module has a heat insulation layer; the upper CPU chip and each memory chip, and the lower CPU chip and the functional chip are interconnected through a common third interposer connection layer; the upper and lower chips are interconnected through the third interposer connection layer; signals are led out from the common third interposer connection layer through the silicon layer and connected to the package base plate through the second connection solder ball.
[0019] Compared with the prior art, the significant advantages of this invention are as follows:
[0020] 1. For functional chips, TSV vias enable stacking interconnection with upper-layer storage chips, improving the efficiency of data input and processing before data output. In addition, when dealing with large-volume data processing, data can be pre-stored through upper-layer storage chips to improve efficiency by reusing time.
[0021] 2. It adopts a dual-layer central processing unit structure and is equipped with a comprehensive interconnection network with the dual-layer CPU as the core. There are abundant interconnection resources between upper-layer cores, between lower-layer cores, and between upper and lower layers. The data interaction path between different cores is no longer singular and is more flexible.
[0022] 3. The dual-layer central processing unit structure of the present invention can work simultaneously or in a time-sharing manner. While the lower-layer CPU chip translates instructions and transmits them to the surrounding functional chips, the upper-layer CPU chip can simultaneously schedule overall data resources, thereby improving chip performance.
[0023] 4. This invention is based on a chiplet-based packaging structure. Different process nodes can be used for modules with different functions. Compared with the fact that each module in a SoC chip can only be based on the same process node, this invention can improve yield and save costs. In terms of performance, stacking and interconnecting functional chips and memory chips can improve the efficiency of data interaction. Attached Figure Description
[0024] Figure 1 for Figure 2 AA section view in the middle;
[0025] Figure 2 This is a schematic diagram showing the arrangement of the central processing unit module and functional modules after removing the packaging shell;
[0026] Figure 3 This is a schematic diagram showing the arrangement of EMIB interconnect bridges in the interposer connection layer;
[0027] Figure 4(a) shows a schematic diagram of the EMIB interconnect bridge distribution between the upper-layer CPU chip and the lower-layer CPU chip.
[0028] Figure 4(b) is a schematic diagram of the vertical interconnect layer distribution between the upper CPU chip and the lower CPU chip;
[0029] Figure 5 This is a schematic diagram of the interconnection between storage chips and functional chips;
[0030] Figure 6 for Figure 2 BB cross-section diagram in the middle;
[0031] Figure 7 This is a schematic diagram of another interconnection structure for dual CPUs to operate simultaneously according to the present invention. Detailed Implementation
[0032] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0033] In the dual-layer stacked packaging structure of this invention, each chiplet functional module is a dual-layer stacked structure, stacking two frequently interacting chips (the two CPU chips in this invention), or stacking functional chips and storage chips together, to improve the efficiency of data interaction. Regarding the overall chip structure layout, the CPU (Central Processing Unit) module is at the core, surrounded by functional modules, facilitating interaction between the CPU module and surrounding functional modules. When the chip of this invention is working normally, the upper and lower CPU chips work simultaneously or in a time-sharing manner. The upper CPU chip is mainly responsible for the global allocation of data resources, while the lower CPU chip is mainly responsible for instruction translation and transmission, thereby improving the overall performance of the chip. To achieve the above working mechanism, a comprehensive and flexible interconnection network structure is required. Therefore, interconnections must be implemented between the upper CPU chip and the surrounding storage chips, and between the lower CPU chip and the functional chips, and vertical interconnections must be implemented between the corresponding stacked chips. The specific implementation is as follows:
[0034] like Figure 1 As shown, the chip structure of the present invention includes an outermost packaging shell 101 for encapsulation, a bottom packaging substrate 102 for encapsulation, a top thermally conductive material layer 103, an upper interposer connection layer 104, a central processing unit module 105 (as shown in the figure, a three-layer structure), and a functional module (with the same structure as the central processing unit module, also a three-layer structure). Figure 1 The diagram shows a first functional module 106, a second functional module 107, a silicon layer 108 (the gray areas in the diagram are all silicon material), a lower interposer connection layer 109, and a first connection solder ball 110. The lower interposer connection layer 109 is connected to the underlying packaging substrate 102 via the first connection solder ball 110. The outer side of the packaging substrate (102) is connected to external circuits via the first connection solder ball (110).
[0035] like Figure 2 As shown, the central processing unit module 105 has eight functional modules arranged in a "nine-square grid" around its perimeter. Figure 1 Only functional modules 106 and 107 are shown in the image, and they are located between the upper interposer connection layer 104 and the lower interposer connection layer 109; a thermally conductive material layer 103 is provided above the upper interposer connection layer 104.
[0036] The thermally conductive material layer 103, the upper interposer connection layer 104, the central processing unit module 105, and the surrounding functional modules (a total of 8), the lower interposer connection layer 109, and the first connection solder ball 110 are all located inside the package shell 101.
[0037] like Figure 2 As shown, each module has a three-layer structure. The central processing unit module 105 is formed by stacking two CPU chips, and the first heat insulation layer 105-3 is disposed between the upper CPU chip 105-1 and the lower CPU chip 105-2. The surrounding eight functional modules are formed by stacking functional chips and storage chips. Taking the first functional module 106 as an example, it consists of the upper first storage chip 106-1, the middle sixth heat insulation layer 106-3, and the lower first functional chip 106-2.
[0038] like Figure 3 The diagram shows the specific distribution of the interposer connection layer and the EMIB interconnect bridges distributed within it. When the chip of this invention is operating normally, the construction of the required interconnect network mainly consists of two parts: interconnection between two stacked chips, and pairwise interconnection between chips within the same layer (between the upper-layer CPU chip and surrounding memory chips, and between pairs of memory chips; between the lower-layer CPU chip and surrounding functional chips, and between pairs of functional chips). The pairwise interconnections between chips within the same layer are achieved through EMIB interconnect bridges. The upper-layer EMIB interconnect bridge 301, used for interconnection between upper-layer chips, is distributed in the upper interposer connection layer 104 (both are in the same layer, not overlapping). Similarly, the lower-layer EMIB interconnect bridge 302, used for interconnection between lower-layer chips, is distributed in the lower interposer connection layer 109. (Combined with...) Figure 1 , Figure 2 , Figure 3 This allows for a clear understanding of the specific structure of the chip in this invention. The upper interposer connection layer 104 is distributed in... Figure 2The upper EMIB interconnect bridge 301 is positioned directly above the grid structure to ensure that it is precisely positioned between each pair of upper-layer chips. Similarly, the lower interposer layer 109 is positioned directly below the grid structure to ensure that the lower EMIB interconnect bridge 302 is precisely positioned between each pair of lower-layer chips. For the interconnection between the upper and lower stacked chips, there are two different types: for functional modules, the interconnection between the lower functional chip and the upper memory chip uses TSV vias (…). Figure 2 (The black solid dots in the diagram are all TSV vias); For the central processing unit module 105, the interconnection between the upper CPU chip 105-1 and the lower CPU chip 105-2 is achieved through the vertical interconnect layer 401.
[0039] Figure 4(b) shows a schematic diagram of the interconnection between the upper CPU chip 105-1 and the lower CPU chip 105-2 of the central processing unit module 105. Considering the complexity of the central processing unit chip structure, the interconnection between the two stacked chips is not achieved using TSV vias, but rather through the vertical interconnect layer 401 around the CPU chip.
[0040] according to Figure 3 As shown in Figure 4(a), the distribution of EMIB interconnect bridges in the interposer connection layer is as follows: the central processing unit (CPU) module is located at the very center. The upper CPU chip 105-1 needs to interconnect with the surrounding memory chips, and the lower CPU chip 105-2 needs to interconnect with the surrounding functional chips. Therefore, EMIB interconnect bridges are distributed on all four sides of both the upper and lower CPU chips 105-1 and 105-2, including the first EMIB interconnect bridge 301-1 distributed around the upper CPU chip and the second EMIB interconnect bridge 302-1 distributed around the lower CPU chip, as shown in Figure 4(a). Vertical interconnect layers are respectively set between the upper EMIB interconnect bridge 301 and the lower EMIB interconnect bridge 302, as shown in Figure 4(b) (the upper EMIB interconnect bridge is not shown). The CPU module achieves same-layer interconnection through the upper and lower EMIB interconnect bridges, while also achieving interconnection between the two stacked CPU chips through the vertical interconnect layer.
[0041] like Figure 5 The diagram shows the interconnection between the stacked chips of a functional module. For the functional module, the functional chip and the memory chip are stacked together, and the interconnection between them is achieved directly using TSV vias. The distribution of the TSV vias depends on the location of the functional module. Figure 5 for Figure 2The arrangement of the functional modules in the first row shows that the third functional module 201, according to its position in the 3x3 grid, needs to be interconnected with the fourth functional module 202 and the first functional module 106 in the second row. Figure 5 (Not shown in the figure). Therefore, for the third functional module 201, a row of first TSV through holes 201-1 is provided on its right side to facilitate interconnection with the fourth functional module 202, and a row of second TSV through holes 201-2 is provided on its upper side to facilitate interconnection with the first functional module 106. Similarly, the fourth functional module 202 needs to be interconnected with the third functional module 201 on the left, the fifth functional module 203 on the right, and the central processing module 105 (not shown in the figure), so a row of third TSV through holes 202-1, a row of fourth TSV through holes 202-2, and a row of fifth TSV through holes 202-3 are distributed on the three sides respectively. The overall schematic diagram of the TSV through holes for functional modules in different positions is shown in the figure. Figure 2 As indicated, each TSV via penetrates both the upper and lower layers of the chip (i.e., the upper functional chip and the lower storage chip) and the intermediate insulation layer. Interconnection between the upper and lower chips is achieved through copper injection. Based on this, the signals from each TSV via are extended upwards and downwards to the corresponding EMIB interconnect bridges to facilitate interconnection between chips in the same layer. Taking the third functional module 201 as an example, a column of first TSV vias 201-1 of the third functional module 201 is extended upwards to the third EMIB interconnect bridge 301-3. Similarly, a column of third TSV vias 202-1 of the fourth functional module 202 is extended upwards to the third EMIB interconnect bridge 301-3. Interconnection between the upper chip (i.e., the storage chip) of the third functional module 201 and the upper chip (i.e., the storage chip) of the fourth functional module 202 can be achieved in the third EMIB interconnect bridge 301-3. Similarly, extending to the sixth EMIB interconnect bridge 302-3 below, interconnection between the lower-level chips (i.e., functional chips) of the third functional module 201 and the lower-level chips (i.e., functional chips) of the fourth functional module 202 can be achieved. By analogy, other modules also achieve pairwise interconnection between chips of the same layer in the same manner, based on the top-to-bottom interconnection through TSV vias. Through the above-described interconnection methods, the interconnection network required for the normal operation of the chip of this invention is thus formed.
[0042] As can be seen from the above description of the chip proposed in this invention, the overall structure of the chip is a complex hierarchical structure, and therefore the implementation of the overall structure is completed layer by layer. For example... Figure 6 As shown, this is the row where the functional module is located. Figure 2The diagram in the first row shows the fourth functional module 202. Taking the fourth functional module 202 as an example, the middle layer is the fourth thermal insulation layer 202-6, below the fourth thermal insulation layer 202-6 is the fourth functional chip 202-5, and above it is the fourth storage chip 202-4. Above the fourth storage chip 202-4 is the upper interposer connection layer 104, in which the third EMIB interconnect bridge 301-3 and the fourth EMIB interconnect bridge 301-4 are distributed to realize the interconnection between the upper storage chips. Similarly, in the lower interposer connection layer 109, the fifth EMIB interconnect bridge 302-3 and the sixth EMIB interconnect bridge 302-4 are distributed to realize the interconnection between the lower functional chips. The third TSV via 202-1 penetrates the lower layer's fourth functional chip 202-5 vertically; the middle fourth thermal insulation layer 202-6 and the upper fourth storage chip 202-4 are interconnected by copper injection, extending the signal to the upper third EMIB interconnect bridge 301-3 and the lower fifth EMIB interconnect bridge 302-3, so as to realize the interconnection of the two stacked chips (i.e., functional chips and storage chips) and the interconnection between two chips in the same layer (i.e., functional chips and functional chips, storage chips and storage chips). Figure 1 The cross-sectional view shown is consistent with... Figure 6 In contrast, the implementation of the vertical interconnection of the central processing unit module 105 differs from that of the aforementioned functional modules; instead, it utilizes vertical interconnect layers. As shown in Figure 4(b), the vertical interconnect layers are distributed around the central processing unit module. The first vertical interconnect layer 401-1 (only a portion of the vertical interconnect layer is shown in the cross-sectional view) is connected to the upper first EMIB interconnect bridge 301-1 and the lower second EMIB interconnect bridge 302-1, respectively. The second vertical interconnect layer 401-2 is connected to the upper and lower EMIB interconnect bridges in the same manner. Thus, based on the interconnection between chiplets in the same layer via EMIB interconnect bridges, the interconnection between upper and lower CPU chips is achieved through the vertical interconnect layers.
[0043] like Figure 1 As shown, the function of the first package solder ball 110 on the bottom surface is to guide the signal from the lower interposer interconnect layer 109 to the package substrate 102 to facilitate packaging. When depositing the lower interposer interconnect layer 109, attention should be paid to the location of the EMIB interconnect bridges 302, as shown in the diagram. Figure 3As shown. EMIB interconnect bridges 302 need to be distributed between pairs of interconnecting chips. Except for the EMIB interconnect bridges 302, the lower interposer layer 109 is made of ordinary silicon material to reduce costs. When placing the lower-layer CPU chips and functional chips, their positions must correspond to the lower EMIB interconnect bridges (the lower-layer EMIB interconnect bridges 302 should be distributed between pairs of chips) to facilitate interconnection between the lower-layer CPU chips and functional chips, as well as between pairs of functional chips. The gaps between the lower-layer CPU chips and functional chips are filled with ordinary silicon material. After the lower-layer chip arrangement is completed, the thermal insulation layer arrangement and the upper-layer CPU chips and memory chips arrangement only need to be stacked according to the positions of the lower-layer chips, with the gaps also filled with ordinary silicon material. After the upper-layer chip arrangement is completed, TSV vias and vertical interconnect layers need to be set at the corresponding positions. Figure 1 As shown, the sixth TSV via 106-4 penetrates the upper first functional chip 106-1, the lower first storage chip 106-2, and the intermediate sixth thermal insulation layer 106-3 to achieve vertical interconnection. The vertical interconnect layer is arranged as shown in Figure 4(b), encircling the central processing unit module. It is embedded in the gaps and surrounded by silicon material, such as... Figure 1 The first vertical interconnect layer 401-1 is shown. Similar to the lower interposer layer 109, the EMIB interconnect bridges 301 in the upper interposer layer 104 are distributed between the two chips that need to be interconnected in the upper layer (the positions in the interposer layer other than the EMIB interconnect bridges are made of ordinary silicon material). The topmost layer is coated with a heat dissipation material 103 to help dissipate heat from the chip and ensure stable performance.
[0044] In terms of interconnection between chips within the same layer, the chip structure of this invention achieves interconnection through two interposer connection layers, specifically through EMIB interconnect bridges distributed within the interposer connection layers. The two interposer connection layers are respectively located on the top and bottom sides of the module. Furthermore, the interconnection between the two stacked chips is achieved through additional TSV vias and vertical interconnect layers. Based on the aforementioned dual-CPU operating mode, this invention also provides a chip with another structure, such as... Figure 7 As shown, with Figure 1Similarities between the two structures: Both are two-layer structures, with the upper layer containing distributed CPU and memory chips, and the lower layer containing distributed CPU and functional chips. Differences: A common third interposer layer 701 is placed between the two layers of chips for building the interconnect network. The heat insulation layer is omitted, and interconnections between upper and lower layer chips can be achieved through the common third interposer layer 701. Furthermore, communication interconnections between corresponding upper and lower chips do not require TSV vias and vertical interconnect layers; they can be directly interconnected via wires from the third interposer layer 701. Because... Figure 7 The two chip layers shown are arranged opposite each other, and all signal interfaces are led to a common third interposer connection layer 701. Therefore, before packaging, the signals must be led out through the third interposer connection layer 701 and to the packaging substrate 704; as shown Figure 7 As shown, the signal is led out from the third interposer interconnect layer 701 via the surrounding silicon layer 702, and connected to the package substrate 704 via the second interconnect solder ball 703 to achieve packaging.
Claims
1. A chip based on a Chiplet dual-layer stacked package structure, characterized in that, It includes a thermally conductive material layer (103), an upper interposer connection layer (104), a central processing unit module (105), a functional module, a lower interposer connection layer (109), a packaging substrate (102), and a packaging shell (101). The lower interposer connection layer (109) is connected to the package substrate (102) through the first connection solder ball (110); the outer side of the package substrate (102) is connected to the external circuit through the first connection solder ball (110); The eight functional modules are respectively located around the central processing unit module (105). The central processing unit module (105) and the eight functional modules form a "nine-square grid" arrangement and are located between the lower interposer connection layer (109) and the upper interposer connection layer (104). A thermally conductive material layer (103) is provided on the upper interposer connection layer (104); The central processing unit module (105) includes, from top to bottom, an upper CPU chip, a heat insulation layer, and a lower CPU chip. The upper CPU chip is interconnected with the lower CPU chip through a vertical interconnect layer. Each functional module includes, from top to bottom, a storage chip, a heat insulation layer, and a functional chip. The lower functional chip is interconnected with the upper storage chip through a TSV via. The upper-layer CPU chip is connected to each memory chip and to each pair of memory chips via upper-layer EMIB interconnect bridges. The lower-layer CPU chip is connected to each functional chip and to each pair of functional chips via lower-layer EMIB interconnect bridges. The upper-layer EMIB interconnect bridges are located in the upper interposer connection layer (104), and the lower-layer EMIB interconnect bridges are located in the lower interposer connection layer (109). The vertical interconnect layer is connected to the upper EMIB interconnect bridge and the lower EMIB interconnect bridge around the central processing unit module, respectively. The thermally conductive material layer (103), the first connecting solder ball (110), the upper interposer connecting layer (104), the central processing unit module (105), the functional module and the lower interposer connecting layer (109) are all located inside the packaging shell (101).
2. The chip based on the Chiplet dual-layer stacked packaging structure according to claim 1, characterized in that, The upper-layer EMIB interconnect bridge is distributed between the upper-layer CPU chip and each memory chip; the lower-layer EMIB interconnect bridge is distributed between the lower-layer CPU chip and each functional chip.
3. The chip based on the Chiplet dual-layer stacked packaging structure according to claim 1, characterized in that, The vertical interconnect layer is distributed around the central processing unit module (105).
4. The chip based on the Chiplet dual-layer stacked package structure according to claim 1, characterized in that, Silicon material is filled between each upper EMIB interconnect bridge in the upper interposer interconnect layer (104); silicon material is filled between each lower EMIB interconnect bridge in the lower interposer interconnect layer (109).
5. The chip based on the Chiplet dual-layer stacked packaging structure according to claim 1, characterized in that, The TSV vias penetrate the functional chip, the memory chip, and the intermediate thermal insulation layer. Each TSV via is interconnected with the functional chip and the memory chip through a copper injection process. The signals from each TSV via extend upward to the upper EMIB interconnect bridge and downward to the lower EMIB interconnect bridge, respectively, to ensure interconnection between chips in the same layer.
6. The chip based on the Chiplet double-layer stacked package structure according to any one of claims 1-5, characterized in that, The upper and lower CPU cores work simultaneously or in a time-sharing manner. The upper CPU core is used for global allocation of data resources, while the lower CPU core is used for instruction translation and transmission.
7. The chip based on the Chiplet double-layer stacked package structure as described in any one of claims 1-5, characterized in that, The central processing unit module (105) and the functional module have no heat insulation layer. The upper CPU chip and each memory chip, and the lower CPU chip and the functional chip are interconnected through a common third interposer connection layer (701). The upper and lower chips are also interconnected through the third interposer connection layer (701). The signal is led out from the common third interposer connection layer (701) through the silicon layer (702) and connected to the package base plate (704) through the second connection solder ball (703).