A Fast SVPWM Method for a Simplified n-Level Inverter

Abstract

The present invention discloses a simplified fast SVPWM method for an n-level inverter. By calculating the neutral point voltage, the expressions of the three-phase output voltages to the ground are directly obtained. On this basis, by modifying the zero-sequence component and changing the saddle wave to a flat-topped wave, the optimization of the inverter switching times is completed, making the inverter switching times theoretically optimal. Then, through simple transformation according to the characteristics of the n-level inverter, the three-phase switching states and their duty cycles can be directly obtained. The SVPWM algorithm is changed from the traditional geometric solution to an algebraic solution, eliminating a large number of cumbersome steps such as judging the triangle where the vector is located, calculating the duty cycles of the three vectors, determining the "0 vector", and generating the switching sequence. This method is simple and easy to implement, and without traversing the three vectors closest to the given voltage vector, the minimization of the switching times of the multi-level inverter is completed.

Description

Technical Field

[0001] The present invention belongs to the technical field of inverters, and particularly relates to a fast SVPWM method for a simplified n-level inverter. Background Technique

[0002] Multilevel inverters are widely used because of their lower power transistor voltage, fewer switching times, and lower dv / dt. The SVPWM algorithm also has advantages such as high voltage utilization rate and being more suitable for digital implementation, so it is very common in two-level inverters. However, due to the more complex geometric structure brought by the larger number of hexagon layers in multilevel inverters, it is very complicated to transplant the traditional SVPWM algorithm to an n-level inverter. Moreover, as the number of levels of the inverter increases, the complexity of the SVPWM algorithm will increase geometrically.

[0003] In response to this situation, the literature [1] "AHMED, IRFAN, BORGHATE, VIJAY B., MATSA, AMARENDRA, et al. Simplified Space Vector Modulation Techniques for Multilevel Inverters [J]. IEEE Transactions on Power Electronics, 2016, 31(12): 8483-8499. DOI: 10.1109 / TPEL.2016.2520078." proposes that a small part of the modulation degree can be sacrificed to reduce the overlapping part of the sub-hexagons, thereby simplifying the algorithm. However, as the number of levels of the inverter increases, the complexity of this method will still increase.

[0004] Document [2] "LI,JUNJIE,JIANG,JIANGUO,QIAO,SHUTONG.A Space Vector PulseWidth Modulation for Five-Level Nested Neutral Point Piloted Converter[J].IEEE Transactions on Power Electronics, 2017, 32(9): 5991-6004. DOI: 10.1109 / TPEL.2016.2618931." and literature [3] "WANG, CUI, ZHONG, QING-CHANG, ZHU, NINGFEI, etal. Space Vector Modulation in the 45°C coordinatesα′β′ for Multilevel Converters[J]. IEEE Transactions on Power Electronics, 2021, 36(6): 6525-6536. DOI: 10.1109 / TPEL.2020.3040216." Methods based on the 60° coordinate system and the 45° coordinate system are proposed respectively, which average the vector nodes of the voltage modulation hexagon into integers, simplify the calculation and can be extended to any n-level inverter. However, the conversion from the 60° (45°) coordinate system to the ABC coordinate system and from the ABC coordinate system to the 60° (45°) coordinate system cannot be avoided.

[0005] Reference [4] "DENG, YI, WANG, YEBIN, TEO, KOON HOO, et al. A Simplified Space Vector Modulation Scheme for Multilevel Converters [J]. IEEE Transactions on Power Electronics, 2016, 31 (3): 1873-1886. DOI: 10.1109 / TPEL.2015.2429595." By multiplying the αβ axis by different proportional coefficients, the coordinates of the vector nodes are converted into integers, which has a simpler structure than the 60° (45°) coordinate system. However, the subsequent steps of determining the triangle where the given vector is located, calculating the duty cycle of the three vectors, determining the "0 vector", and generating the switching sequence are still unavoidable.

[0006] Meanwhile, although the above-mentioned solutions can simplify the SVPWM calculation of multilevel inverters to varying degrees, traversing the redundant switching states of vectors is required to achieve auxiliary control objectives (such as minimizing the number of inverter switches) by leveraging the flexibility provided by the redundant switching combinations of multilevel inverters. This significantly increases the complexity of the SVPWM algorithm when the number of levels is large, making it difficult to fully utilize the flexibility offered by multilevel inverters. Summary of the Invention

[0007] To overcome the deficiencies of the prior art, the present invention provides a simplified fast SVPWM method for an n-level inverter. By calculating the neutral point voltage, the expressions of the three-phase output voltages with respect to ground are directly obtained. On this basis, by modifying the zero-sequence component and changing the saddle wave to a flat-topped wave, the optimization of the number of inverter switches is completed, theoretically achieving the optimal number of inverter switches. Then, through simple transformations according to the characteristics of the n-level inverter, the three-phase switching states and their duty cycles can be directly obtained. The SVPWM algorithm is changed from the traditional geometric solution to an algebraic solution, eliminating a large number of cumbersome steps such as determining the triangle where the vector is located, calculating the duty cycles of the three vectors, determining the "0 vector", and generating the switching sequence. This method is simple and easy to implement, and while not requiring traversing the three vectors closest to the given voltage vector, it minimizes the number of switches of the multilevel inverter.

[0008] The technical solution adopted by the present invention to solve its technical problems includes the following steps:

[0009] Step 1: Obtain the three-phase output voltages with respect to ground that the inverter expects to output according to Equation (1):

[0010]

[0011] In the formula, U AN ', U BN ' and U CN ' are the three-phase output voltages with respect to ground of ABC that are expected to be output, U AO , U BO , U CO respectively represent the voltages between the output terminals of the three-phase inverter and the load neutral point, min is the minimum value among U AO , U BO , U CO , is the amplitude of the given voltage vector , and θ is the phase angle of ;

[0012] Step 2: Modify Equation (1) according to whether a zero-sequence component needs to be added to the voltage with respect to ground. The modified output voltages with respect to ground are U AN-F , U BN-F and U CN-F, and its calculation is shown in Equations (2a)-(2c):

[0013]

[0014]

[0015]

[0016] Step 3: Obtain the three-phase switching states and three-phase duty cycles of the inverter according to Equation (3):

[0017] L M-low = int((n - 1)U MN-F / U dc )

[0018] L M-high = int((n - 1)U MN-F / U dc ) + 1 (3)

[0019] DutyM = (n - 1)U MN-F / U dc - int((n - 1)U MN-F / U dc )

[0020] In the formula, the subscript M represents any one of the three phases {A, B, C}; int is the floor function; n is the number of levels of the multilevel inverter, U dc is the DC bus voltage of the inverter; U MN-F is the voltage of phase M to ground; L M-low and L M-high are the two switching states of phase M; DutyM is the duty cycle of the L M-high switching state of phase M;

[0021] Step 4: Transform Equation (3) so that the action times of the two redundant states of the 0 vector meet the modulation requirements;

[0022] When continuous modulation is adopted, substitute DutyM into Equation (4) to obtain the output three-phase duty cycle DutyM'; if discontinuous modulation is adopted, select (5a) or (5b) for output according to requirements;

[0023]

[0024]

[0025]

[0026] In Equation (4), max(DutyA, DutyB, DutyC) is the maximum value among DutyA, DutyB, and DutyC; min(DutyA, DutyB, DutyC) is the minimum value among DutyA, DutyB, and DutyC; in Equations (5a) and (5b), max(DutyA', DutyB', DutyC') is the maximum value among DutyA', DutyB', and DutyC'; min(DutyA', DutyB', DutyC') is the minimum value among DutyA', DutyB', and DutyC'.

[0027] Step 5: Select a suitable triangular carrier wave according to the modulation mode;

[0028] When continuous modulation is adopted, the triangular carrier wave is an isosceles triangle; when discontinuous modulation is adopted, the triangular carrier wave is a right triangle; and set L A-low 、L B-low and L C-low as the three-phase switch states at the starting moment of the carrier wave period, and control the switching of the three-phase switch states through the set duty cycle and carrier wave.

[0029] Preferably, the 0 vector is the central vector of the sub-hexagon where the given voltage vector in the multi-level SVPWM algorithm is located.

[0030] The beneficial effects of the present invention are as follows:

[0031] Compared with the original multi-level inverter SVPWM algorithm, this method is simpler and easier to implement, and without traversing the three vectors closest to the given voltage vector, it minimizes the switching times of the multi-level inverter. Description of the Drawings

[0032] Figure 1 is the system flow chart of the present invention.

[0033] Figure 2 is the structure diagram of the two-level inverter in the embodiment of the present invention.

[0034] Figure 3 is the structure diagram of the H-bridge cascaded multi-level inverter in the embodiment of the present invention.

[0035] Figure 4 is the schematic diagram of the waveform of the voltage of phase A to the ground and the additional switching times when the output voltage to the ground is a saddle wave in the embodiment of the present invention.

[0036] Figure 5 is the schematic diagram of the waveform of the voltage of phase A to the ground and the additional switching times when the output voltage to the ground is a flat top wave in the embodiment of the present invention.

[0037] Figure 6 It is a schematic diagram of the change of the three-phase output switch state in one SVPWM cycle of an embodiment of the present invention.

[0038] Figure 7 This is a comparison chart of hardware resource consumption of algorithms in embodiments of the present invention.

[0039] Figure 8 This is a comparison chart of the number of switches in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0041] In order to overcome the defects of the prior art, the present invention directly obtains the expression of the three-phase output voltage to ground by calculating the neutral point voltage. Then, a simple change is made according to the characteristics of the n-level inverter to directly obtain the three-phase switch state and its duty cycle. The SVPWM algorithm is changed from a traditional geometric solution to an algebraic solution. A large number of tedious steps in geometric solution are omitted. The steps of determining the triangle where the vector is located, calculating the duty cycle of the three vectors, and generating the switching sequence are omitted, which greatly reduces the execution complexity of the SVPWM algorithm.

[0042] Afterwards, in order to utilize the redundant switch combination of MLI, the reasons for the extra switching times of MLI SVPWM were analyzed, and the irrationality of the three-phase voltage to ground output by SVPWM was pointed out. And by modifying the zero-sequence component of the output, the output voltage to ground was changed from saddle wave to flat-top wave while maintaining the phase voltage and line voltage unchanged, achieving the global optimal number of MLI switches. This avoids the traversal operation of NTVs by traditional SVPWM in order to achieve the auxiliary control target (minimum switching frequency). It is more suitable for the application of more level MLI.

[0043] The complexity of the algorithm proposed in the present invention remains consistent and will not increase with the increase in the number of inverter levels.

[0044] A simplified n-level inverter fast SVPWM method comprises the following steps:

[0045] Step 1: According to formula (1), the three-phase voltage to ground of the inverter is obtained:

[0046]

[0047] Where U AN '、U BN 'and U CN ' is the expected output voltage between ABC and ground, U AO , U BO , U CO Respectively represent the voltage between the output terminal of the three-phase inverter and the neutral point of the load, min is UAO , U BO , U CO The minimum value in is the magnitude of the given voltage vector , and θ is the phase angle of ;

[0048] Step 2: Modify Equation (1) according to whether the zero-sequence component needs to be added to the voltage relative to the ground. The modified output voltages relative to the ground are U AN-F , U BN-F and U CN-F , and their calculations are shown in Equations (2a)-(2c):

[0049]

[0050]

[0051]

[0052] Step 3: Obtain the three-phase switching states and three-phase duty cycles of the inverter according to Equation (3):

[0053] L M-low = int((n - 1)U MN-F / U dc )

[0054] L M-high = int((n - 1)U MN-F / U dc ) + 1 (3)

[0055] DutyM = (n - 1)U MN-F / U dc - int((n - 1)U MN-F / U dc )

[0056] In the formula, the subscript M represents any one of the three phases {A, B, C}; int is the floor function; n is the number of levels of the multi-level inverter, U dc is the DC bus voltage of the inverter; U MN-F is the voltage relative to the ground of phase M; L M-low and L M-high are the two switching states of phase M; DutyM is the duty cycle of the L M-high switching state of phase M;

[0057] Step 4: Transform Equation (3) so that the action times of the two redundant states of the 0 vector meet the modulation requirements;

[0058] When continuous modulation is adopted, substitute DutyM into Equation (4) to obtain the output three-phase duty cycle DutyM'; if discontinuous modulation is adopted, select (5a) or (5b) for output according to requirements;

[0059]

[0060]

[0061]

[0062] In Equation (4), max(DutyA, DutyB, DutyC) is the maximum value among DutyA, DutyB, and DutyC; min(DutyA, DutyB, DutyC) is the minimum value among DutyA, DutyB, and DutyC; in Equations (5a) and (5b), max(DutyA', DutyB', DutyC') is the maximum value among DutyA', DutyB', and DutyC'; min(DutyA', DutyB', DutyC') is the minimum value among DutyA', DutyB', and DutyC';

[0063] Step 5: Select a suitable triangular carrier according to the modulation mode;

[0064] When continuous modulation is adopted, the triangular carrier is an isosceles triangle; when discontinuous modulation is adopted, the triangular carrier is a right triangle; and set L A-low , L B-low and L C-low as the three-phase switch states at the starting moment of the carrier period, and control the switching of the three-phase switch states through the set duty cycle and carrier. Specific embodiment:

[0066] First, take a two-level inverter as an example to illustrate the principle of the SVPWM algorithm based on neutral point voltage calculation. As Figure 1 shown is the structural schematic diagram of a three-phase two-level inverter connected to a three-phase symmetrical load. In the figure, ABC are the connection points of the three-phase load and the inverter. L s and R s are the single-phase inductance and resistance of the load respectively; U ea , U eb and U ec are the three-phase back electromotive forces; U o is the true neutral point voltage; point N represents the ground. Then the following equations can be listed:

[0067]

[0068] In the formula, the subscripts M and m both represent any one of the three phases {A, B, C}. UMN is the relative voltage of phase M. U MO is the phase voltage of phase M. is the given voltage vector amplitude; θ is the given voltage vector phase angle. θ m is the angle between the axis of phase M and phase A, θ a = 0; θ b = 2π / 3; θ c = 4π / 3. i m represents the phase current of phase M. U em represents the back electromotive force of phase M.

[0069] Adding the three phases of U AO , U BO and U CO according to Equation (6), we can get:

[0070]

[0071] Substituting Equation (7) into Equation (6), we can get Equation (8):

[0072]

[0073] And the three-phase phase voltages in Equation (8) satisfy:

[0074] U A0 + U B0 + U C0 = 0 (9)

[0075] Solving Equation (8) and substituting Equation (9), the voltages of the three phases output to the ground are:

[0076]

[0077] Since the matrix of Equation (8) is not full rank, there is a general solution term in Equation (10), where c and ξ are arbitrary real numbers, and they are the coefficients of the general solution term.

[0078] It can be seen from Equation (10) that the three-phase voltages output to the ground by the inverter are essentially the three-phase phase voltages plus the general solution term ξ. ξ is the zero-sequence component. That is, by outputting U AN , U BN and U CN in (10), it is equivalent to outputting In this way, the SVPWM algorithm can be completed.

[0079] It should be noted that U AO , U BO , U COIt may be negative. For a two-level inverter, this obviously cannot be directly used as the output voltage to ground and needs to be modified by changing the value of ξ. Calculate U according to Equation (6). AO and U BO and U CO and modify Equation (10) to obtain Equation (1);

[0080] Obviously, the actual effect of the output voltage according to Equation (1) is the same as that of Equation (9). And the minimum value of the three-phase voltage output by Equation (1) is 0.

[0081] For a two-level inverter, divide U AN ', U BN ' and U CN ' by U dc to convert them into three-phase duty cycles and then SVPWM can be output.

[0082] Since the n-level inverter only equally divides the bus voltage U dc into (n - 1) parts in the form of diode clamping, etc. Since the desired output voltage to ground U AN ', U BN ' and U CN ' have been obtained, it is very easy to control the switching state of the n-level inverter according to the characteristics of the n-level inverter to make it equivalently output U AN ', U BN ' and U CN '.

[0083] Take the H-bridge cascaded multilevel inverter as an example for illustration. Figure 2 This is the structure of the H-bridge cascaded inverter. Figure 2 The output voltage u h of each H-bridge module in it can be E, -E or 0. Therefore, the bus voltage can be expressed as:

[0084] U dc = 2pE = (n - 1)E (11)

[0085] where p is the number of cascaded h-bridges per phase and n is the number of levels of the inverter.

[0086] In a real system, the 0 potential should be the point N' in the figure and does not need to be grounded. However, this may cause the three-phase voltages to ground to be negative. For the convenience of understanding, assume that the potential of point N' is U dc / 2, then the 0 potential becomes point N. Still use M to represent the three phases A, B, and C, then the relationship between U MN and U MN' is:

[0087] U MN = U MN' + U dc / 2 (12)

[0088] As can be seen from Equation (10), U MN and U MN' are equivalent. Therefore, using U MN to replace U MN' .

[0089] Thus, according to the characteristics of the n-level inverter, the output voltage to ground of the H-bridge cascaded n-level inverter can be defined as:

[0090]

[0091] In Equation (13), S m (S m = 0, 1,... n-1) is the switching state of the m-phase, and n is the number of inverter levels.

[0092] Since Equation (1) directly gives the output voltage to ground, the modulation of the multilevel inverter is thus transformed into selecting the two switching states closest to U MN ', and then the duty cycle can be obtained and directly output.

[0093] The selected switching states and duty cycle are shown as follows:

[0094] L M-low ' = int((n - 1)U MN ' / U dc )

[0095] L M-high ' = int((n - 1)U MN ' / U dc ) + 1 (14)

[0096] DutyM = (n - 1)U MN ' / U dc - int((n - 1)U MN ' / U dc )

[0097] In Equation (14), L M-low ' and L M-high ' are respectively the two switching states used by any one phase in the three-phase for multilevel SVPWM. DutyM is the duty cycle of L M-high . int is the floor function. Obviously, in Equation (14), the three-phase switching state combination (S equivalent to the "0 vector" of the two-level inverter (i.e., the center vector node of the sub-hexagon where a is located in the traditional multilevel SVPWM algorithm) is (L b , S c ) is (L A-low,L B-low ,L C-low ). The entire output process of SVPWM is also similar to the five-segment SVPWM of a two-level inverter.

[0098] After that, by simply transforming the three-phase duty cycles, continuous modulation or discontinuous modulation output can be completed, which will be elaborated in the subsequent part. However, directly outputting after the transformation according to Equation (14) does not utilize the flexibility provided by the multilevel inverter, resulting in the switching frequency not being optimal. This is actually caused by the saddle-wave shape of the three-phase voltages to ground. The reasons for the increased switching times caused by the saddle-wave shape and the improvement scheme will be described in detail below.

[0099] Although in each SVPWM modulation cycle, the switching times of the three-phase inverter are determined by the selected modulation mode and cannot be changed. However, the L M-low ' output at the starting moment of each SVPWM cycle may be different. This brings additional switching times. Therefore, as long as it is ensured that the number of changes in L A-low ', L B-low ', L C-low ' is minimized in each fundamental wave cycle, the minimization of the inverter switching times can be guaranteed.

[0100] Taking n = 11 as an example, the functional relationship between U AN ' and θ at this time can be drawn as A-low shown in Figure 3 . The output voltage to ground and the switching state switching graph of phases BC are only different in phase from that of A, so they will not be given here.

[0101] From Figure 3 , it can be obtained that the variation range of U MN ' is . It is only related to the given and cannot be changed by modifying the zero-sequence component.

[0102] This also means that L M-low ' will definitely complete a change process from 0 to and from back to 0 in each fundamental wave cycle. It is precisely this process that brings additional switching times.

[0103] However, obviously, the level switching process of L M-low ' from 0 to and from back to 0 directly obtained from Equation (14) is not optimal, which is caused by the saddle shape at the top of U MN '.

[0104] If you want to minimize the number of switching times, you can consider modifying the zero-sequence component to reduce U AN ',U BN 'and U CN 'The saddle wave shape is changed to a flat-top wave. Figure 3 The concave part of the saddle wave in the middle A phase is always maintained at (As shown by the dotted line in the figure). In this way, L M-low 'achieve It then maintains for a period of time, and then decreases monotonically until it becomes 0. Instead of switching multiple times between the two peaks of the saddle wave before monotonically decreasing to 0 as shown in the figure, the number of additional switching times can be minimized.

[0105] If you want to AN ',U BN 'and U CN To change the saddle wave shape of ' into a flat-top wave, it is necessary to increase the zero-sequence component of the output when θ is between the two peaks of the saddle wave of each phase (the area with dotted lines in the figure) so that the phase-to-ground voltage is constant In this way, it is necessary to set the output voltage to ground U AN ',U BN 'and U CN 'Change to U in formula (2a)-(2c) AN-F , U BN-F and U CN-F :

[0106] According to formula (2), For example, n=11, we can get U AN-F The function characteristics of θ are as follows Figure 4 shown. Figure 4 The use of U AN-F Replace U AN ' A-low ' waveform.

[0107] It can be seen that Figure 4 Middle U AN-F There is only one monotonically increasing interval and one monotonically decreasing interval. Therefore L A-low The number of switching times should be less than Figure 3 This is also true for the other two phases. Under other modulation indices, the three-phase voltage output by substituting (2) into (14) will generally have fewer additional switching times than (1) into (14). Only when the given modulation indices just satisfies (15), the switching times of the two are the same. Because when (15) is satisfied, L M-low 'Will be in U MN ' remains unchanged between the two peaks.

[0108]

[0109] Thus, using U AN-F , U BN-F and U CN-F to replace U AN ', U BN ' and U CN ', the new three-phase switch states and duty cycle formulas can be summarized as Equation (3);

[0110] Directly outputting according to Equation (3) will result in unequal action times for two "0 vectors" (i.e., the switch combinations (L A-low , L B-low , L C-low ) and (L A-high , L B-high , L C-high ). Therefore, it needs to be modified to Equation (4). In Equation (4), max(DutyA, DutyB, DutyC) is the maximum value among DutyA, DutyB, and DutyC; min(DutyA, DutyB, DutyC) is the minimum value among DutyA, DutyB, and DutyC.

[0111] In this way, the switch states of the three-phase output will naturally transition from (L A-low , L B-low , L C-low ) to (L A-high , L B-high , L C-high ) and then symmetrically switch to (L A-low , L B-low , L C-low ). This is the continuous modulation mode. At this time, the required triangular carrier is an isosceles triangle (i.e., the counter of the EPWM module of the DSP needs to be in the up-down counting mode).

[0112] If you want to set the modulation mode to discontinuous modulation, then Equation (4) needs to be modified to Equation (5a) or (5b);

[0113] For discontinuous modulation, the required triangular carrier is a right triangle (i.e., the counter of the EPWM module of the DSP needs to be in the up counting or down counting mode).

[0114] The discontinuous modulation of Equation (5a) will not have the switch state combination (L A-low , L B-low , L C-low ), and Equation (5b) will not have (L A-high , L B-high , L C-high ).

[0115] Figure 5Shows the switching situation of the three-phase output switch states in the continuous modulation mode when DutyA > DutyB > DutyC. T in the figure s is a complete triangular carrier cycle, that is, an SVPWM modulation cycle. The three-phase switch states and their corresponding times are also marked with ①, ②, ③, and ④ in the figure.

[0116] Thus, the flowchart of the system can be summarized as Figure 6 shown.

[0117] According to the above control strategy, DSP28335 is used as the main control chip to test the DSP resources consumed by the algorithm. The built-in clock module of the DSP is used to record the execution time of the SVPWM algorithm. The SVPWM algorithm is executed continuously 6000 times, and the average value of the execution time is calculated. All DSP programs are actually transplanted to the ROM for operation during actual writing, and both the IQmath library and the fastRTSLibrary library are used.

[0118] The memory allocation function of the CCS9.0 software is used to observe the program storage space occupancy of the method of this patent. As a comparison, the program execution time and the size of the program storage space occupied by the method proposed in the literature [4] are also tested. The results of the comparative test are as Figure 7 shown.

[0119] From Figure 7 it can be seen the superiority of the algorithm proposed in this paper.

[0120] The proposed scheme and the scheme in the literature [4] are compared and simulated by MATLAB / Simulink. The number of inverter switches in a fundamental wave cycle under different modulation degrees is counted. The fundamental wave frequency is given as 100Hz, and the switching frequency is 10KHz. The results are as Figure 8 shown.

Claims

1. A fast SVPWM method for a simplified n-level inverter, characterized in that, it includes the following steps: Step 1: Obtain the three-phase voltages to ground expected to be output by the inverter according to Equation (1): Wherein, U AN ', U BN ' and U CN ' are the three-phase ABC line-to-ground voltages of the desired output, U AO , U BO , U CO respectively represent the voltages between the output terminals of the three-phase inverter and the load neutral point, min is the minimum value of U AO , U BO , U CO , is the amplitude of the given voltage vector , and θ is the phase angle of ; Step 2: Modify Equation (1) according to whether the zero-sequence component needs to be added to the relative ground voltage. The modified output voltages to the ground are U AN-F , U BN-F and U CN-F , and their calculations are shown in Equations (2a)-(2c): Step 3: Obtain the three-phase switching states and three-phase duty cycles of the inverter according to Equation (3): Wherein, the subscript M represents any one of the three phases {A, B, C}; int is the floor function; n is the number of levels of the multi-level inverter, U dc is the bus voltage of the inverter; U MN-F is the voltage of phase M to ground; L M-low and L M-high are the two switching states of phase M; DutyM is the duty cycle of the switching state of phase M L M-high ; Step 4: Transform Equation (3) so that the action times of the two redundant states of the 0 vector meet the modulation requirements; When continuous modulation is adopted, substitute DutyM into Equation (4) to obtain the output three-phase duty cycle DutyM'; If discontinuous modulation is adopted, select (5a) or (5b) for output according to requirements; In Equation (4), max(DutyA, DutyB, DutyC) is the maximum value among DutyA, DutyB, and DutyC; min(DutyA, DutyB, DutyC) is the minimum value among DutyA, DutyB, and DutyC; in Equations (5a) and (5b), max(DutyA', DutyB', DutyC') is the maximum value among DutyA', DutyB', and DutyC'; min(DutyA', DutyB', DutyC') is the minimum value among DutyA', DutyB', and DutyC'; Step 5: Select a suitable triangular carrier according to the modulation mode; When continuous modulation is adopted, the triangular carrier is an isosceles triangle; when discontinuous modulation is adopted, the triangular carrier is a right triangle; and L A-low 、L B-low and L C-low are set as the three-phase switch states at the starting moment of the carrier period, and the switching of the three-phase switch states is controlled by the set duty ratio and carrier wave.

2. A fast SVPWM method for a simplified n-level inverter according to claim 1, characterized in that, the 0 vector is the central vector of the sub-hexagon where the given voltage vector is located in the multi-level SVPWM algorithm.

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