Semiconductor device and power conversion device

Abstract

The semiconductor device according to the present disclosure includes: a sense source electrode (19) provided independently of the source electrode (9); and a diode (25) provided between the sense source electrode (19) and the drift layer (2), having a rising voltage lower than the operating voltage of a pn diode including the sense well region (13) or the dummy sense well region (23) and the drift layer (2), capable of passing a current flowing from the sense source electrode (19) to the drain electrode (10), and in a dummy sense region (62) where the dummy sense well region (23) and the diode (25) are arranged, the diode (25) is arranged to be mixedly present in a region (FA) where the dummy sense well region (23) is opposed to the gate electrode (7) with the gate insulating film (26) therebetween, i.e., the opposed region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a power conversion device using the semiconductor device. Background Art

[0002] As a conventional semiconductor device, there is a semiconductor device such as a vertical n-type channel silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) having a built-in current detection element. In this semiconductor device, a source pad is electrically connected to a source region of a MOSFET having a plurality of main units provided thereunder, and a sense pad is electrically connected to a source region of a MOSFET having a plurality of sense units provided thereunder. A sense outer well is formed so as to surround a sense well of the MOSFET constituting the sense unit in a top view. Further, a sense pad well is formed so as to surround the sense outer well in a top view.

[0003] On the surface of the sense outer well, a plurality of n-type capacitor lower electrode regions are selectively formed. A gate insulating film is formed on the upper part of the sense outer well. A gate electrode is partially formed on the upper part of the gate insulating film. A region including the sense well constitutes a MOSFET. The sense outer well, the capacitor lower electrode region, the gate insulating film, and the gate electrode act as a capacitor between the gate electrode and the sense pad.

[0004] In the conventional semiconductor device, when an overcurrent is detected in the sense unit as a current detection element, the sense unit and the main unit are cut off to protect these units. On the other hand, the number of sense units is arranged to be smaller than that of the main units in order to avoid a decrease in electrical efficiency. Therefore, the transistor capacitance is small, and the gate insulating film may be damaged due to a surge voltage such as static electricity. Therefore, in the conventional semiconductor device, by providing the sense outer well, the capacitor lower electrode region, the gate insulating film, and the gate electrode, when they are viewed in an alternating current, they act as a capacitor having a low input resistance. Therefore, the capacitance (i.e., electrostatic capacitance) of the capacitor is increased by adjusting the number of units, the electric field in the gate insulating film when static electricity is applied is relaxed, and insulation breakdown is suppressed (for example, Patent Document 1).

[0005] In addition, it is known that a pn diode is built in a semiconductor device such as a MOSFET. In particular, in the case of a semiconductor device made of silicon carbide, crystal defects are likely to occur due to the operation of the pn diode. Therefore, in other conventional semiconductor devices, an SBD (Schottky Barrier Diode) is formed in such a way that a part near the sensing unit in the wide-area well region is missing, and the Schottky electrode is connected to the sensing electrode instead of the source electrode. Thereby, in the sensing unit, crystal defects due to pn current are suppressed. Furthermore, by forming SBDs in both the vicinity of the main unit and the vicinity of the sensing unit with respect to the wide-area well region and connecting them to the source electrode and the sensing electrode respectively, crystal defect generation is suppressed not only in the sensing unit but also in the main unit (for example, Patent Document 2).

[0006] Prior Art Documents

[0007] Patent Documents

[0008] Patent Document 1: WO2013-042406 (paragraphs 0002, 0003, 0013 to 0029, 0060, and Figures 1 to 3 )

[0009] Patent Document 2: WO2014-162969 (paragraphs 0004, 0005, 0147, 0151, 0152, Figure 15 and Figure 17 ) Summary of the Invention

[0010] In the semiconductor device described in Patent Document 1, crystal defects spread when a pn diode including a sensing outer well and a drift layer is energized, and there is a possibility that the element resistance increases in this part and the conduction loss increases. In particular, when the area of the sensing outer well is increased to increase the electrostatic capacitance, the probability of element degradation due to the energization of the pn diode becomes high.

[0011] In Patent Document 2, although it is described that an SBD diode is formed in the wide-area well region corresponding to the sensing pad well in Patent Document 1, the region corresponding to the sensing outer well is not considered.

[0012] The present disclosure has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device that can ensure a desired electrostatic capacitance and suppress an increase in conduction loss due to the spread of crystal defects.

[0013] The semiconductor device according to the present disclosure includes: a semiconductor layer having a first main surface and a second main surface facing the first main surface; a source electrode provided on the first main surface side; and a drain electrode provided on the second main surface side. The semiconductor device controls the current flowing between the source electrode and the drain electrode by the voltage applied to the gate electrode. Among them, the semiconductor device includes: a sense source electrode provided independently of the source electrode on the first main surface side of the semiconductor layer; a drift layer of a first conductivity type that constitutes a main part of the semiconductor layer; a sense well region of a second conductivity type selectively provided on the surface layer of the drift layer and electrically connected to the sense source electrode; a sense source region of the first conductivity type selectively provided on the surface layer of the sense well region and electrically connected to the sense source electrode; a dummy sense well region of the second conductivity type selectively provided independently of the sense well region on the surface layer of the drift layer and electrically connected to the sense source electrode, without forming a channel; a gate insulating film provided between the dummy sense well region and the gate electrode; and a diode provided between the sense source electrode and the drift layer. The rising voltage is lower than the operating voltage of the pn diode including the sense well region or the dummy sense well region and the drift layer, and can conduct the current flowing from the sense source electrode to the drain electrode. In the dummy sense region where the dummy sense well region and the diode are arranged, the diode is arranged to be mixed with the region where the dummy sense well region faces the gate electrode across the gate insulating film, that is, the opposing region.

[0014] According to the present disclosure, in the dummy sense region where the dummy sense well region and the diode are arranged, the diode is arranged to be mixed with the region where the dummy sense well region faces the gate electrode across the gate insulating film, that is, the opposing region. Therefore, it is possible to ensure a desired electrostatic capacitance in the dummy sense region and suppress an increase in conduction loss due to the expansion of crystal defects, and the reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a top view schematic diagram showing the whole of the semiconductor device of Embodiment 1.

[0016] Figure 2 It is a cross-sectional schematic diagram of the main region in the semiconductor device of Embodiment 1.

[0017] Figure 3 It is a cross-sectional schematic diagram of the sense region in the semiconductor device of Embodiment 1.

[0018] Figure 4 It is a diagram showing an example of the arrangement pattern of the sense region in the semiconductor device of Embodiment 1.

[0019] Figure 5 It is a diagram showing another example of the arrangement pattern of the sense region in the semiconductor device of Embodiment 1.

[0020] Figure 6 It is a diagram showing another example of the configuration pattern of the sensing region in the semiconductor device of Embodiment 1.

[0021] Figure 7 It is a diagram showing another example of the configuration pattern of the sensing region in the semiconductor device of Embodiment 1.

[0022] Figure 8 It is a circuit diagram showing the semiconductor device of Embodiment 1.

[0023] Figure 9 It is a schematic cross-sectional view of the sensing region in the semiconductor device according to the modified example of Embodiment 1.

[0024] Figure 10 It is a diagram showing an example of the configuration pattern of the sensing region in the semiconductor device according to the modified example of Embodiment 1.

[0025] Figure 11 It is a diagram showing another example of the configuration pattern of the sensing region in the semiconductor device according to the modified example of Embodiment 1.

[0026] Figure 12 It is a diagram showing another example of the configuration pattern of the sensing region in the semiconductor device according to the modified example of Embodiment 1.

[0027] Figure 13 It is a schematic cross-sectional view of the sensing region in the semiconductor device of Embodiment 2.

[0028] Figure 14 It is a schematic cross-sectional view of the sensing region in the semiconductor device according to the modified example of Embodiment 2.

[0029] Figure 15 It is a schematic cross-sectional view of the boundary region in the semiconductor device of Embodiment 3.

[0030] Figure 16 It is a schematic cross-sectional view of the boundary region in the semiconductor device of Embodiment 4.

[0031] Figure 17 It is a schematic cross-sectional view of the sensing region in the semiconductor device of Embodiment 5.

[0032] Figure 18 It is a schematic cross-sectional view of the sensing region in the semiconductor device according to the modified example of Embodiment 5.

[0033] Figure 19 It is a schematic cross-sectional view of the sensing region in the semiconductor device according to another modified example of Embodiment 5.

[0034] Figure 20 It is a block diagram showing a power conversion system to which the power conversion device of Embodiment 6 is applied.

[0035] (Symbol Explanation)

[0036] 1: Semiconductor substrate; 2: Drift layer; 3: Well region; 4: Source region; 5: Schottky junction; 6: Gate insulating film; 7: Gate electrode; 8: Interlayer insulating film; 9: Source electrode; 10: Drain electrode; 13: Sensing well region; 14: Sensing source region; 15: Schottky junction; 16: Sensing gate insulating film; 18: Sensing interlayer insulating film; 19: Sensing source electrode; 23: dummy sensing well region; 24: dummy sensing source region; 25: Schottky junction; 26: dummy sensing gate insulating film; 28: dummy sensing interlayer insulating film; 31: Region between source electrodes; 33: Boundary well region; 35: Schottky junction; 38: Insulating film; 41: Groove; 50: Main region; 60: Sensing region; 61: Active sensing region; 62: dummy sensing region; 70: Boundary region; 101: Semiconductor device; 201: Semiconductor device; 301: Semiconductor device; 401: Semiconductor device; 501: Semiconductor device; Power supply 700; Power conversion device 800; Main conversion circuit 801; Drive circuit 802; Control circuit 803; Load 900. Detailed Embodiment

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In addition, the drawings are schematically shown, and the sizes and the mutual relationships of the positions of the images respectively shown in different drawings are not necessarily correctly described and may be appropriately changed. Further, in the following description, the same reference numerals are attached to the same components for illustration, and their names and functions are also the same or similar. Therefore, the detailed description thereof may sometimes be omitted.

[0038] In addition, in each drawing, in order to represent a specific region and the boundary between the regions, a dotted line may sometimes be shown, but they are only shown for the convenience of explanation or to make the drawings easier to understand and do not limit the content of each embodiment at all.

[0039] In addition, in the following description, terms such as "upper", "lower", "side", "bottom", "front", and "back" that mean specific positions and directions may sometimes be used, but these terms are appropriately used terms for making the content of the embodiments easier to understand and are not related to the direction in actual implementation.

[0040] In the present disclosure, when using terms such as "on ~" and "under ~" to express the mutual relationship of components, it does not prevent the existence of spacers between the components. For example, in the case of describing "B provided on A", it includes the case where another component C is provided between A and B and the case where it is not provided. In addition, in the present disclosure, when using terms such as "on ~" and "under ~" to express, it also includes the concept of up and down considering the stacked structure. For example, in the case of describing "B provided on A covering the groove", it includes the meaning that B exists in the direction opposite to the groove surface as viewed from A, and within this meaning, it also includes the horizontal direction and the inclined direction.

[0041] In the following description, regarding the conductivity type of impurities, the case where the first conductivity type is set to n-type and the second conductivity type is set to p-type is described, but the first conductivity type can also be set to p-type and the second conductivity type can be set to n-type. In addition, the current flowing from the drain to the source of the MOSFET is called the forward current, and the current flowing from the source to the drain is called the reverse current.

[0042] In addition, terms such as "MOS" were previously used for the metal / oxide / semiconductor junction structure and adopted the initials of Metal-Oxide-Semiconductor. However, in the case of a field-effect transistor having an MOS structure in particular (hereinafter simply referred to as "MOS transistor"), from the viewpoints of recent integration and improvement of manufacturing processes, etc., the materials of the gate insulating film and the gate electrode have been improved.

[0043] For example, in the MOS transistor, from the viewpoint of mainly self-aligning the formation of the source / drain, polysilicon is used as the material of the gate electrode instead of metal. In addition, from the viewpoint of improving electrical characteristics, a material with a high dielectric constant is used as the material of the gate insulating film, but this material is not necessarily limited to oxides.

[0044] Therefore, the term "MOS" is not necessarily limited to being used for the metal / oxide / semiconductor stacked structure, and this specification is not premised on such a limitation. That is, in view of common technical knowledge, here "MOS" means that it not only includes the abbreviation derived from this etymology, but also has the meaning of widely including the stacked structure of a conductor / insulator / semiconductor.

[0045] Embodiment 1.

[0046] <Structure>

[0047] Figure 1 is a top view schematically showing the overall semiconductor device 101 according to Embodiment 1 of the present disclosure. As Figure 1As shown, the semiconductor device 101 of Embodiment 1 has a main region 50, a sensing region 60, and a boundary region 70. In the sensing region 60, an active sensing region 61 and a dummy sensing region 62 are included.

[0048] Figure 2 is a cross-sectional schematic diagram showing a cross-section of a part of the main region 50. As Figure 2 shown, the semiconductor device 101 includes a semiconductor substrate 1, a drift layer 2, a well region 3, a source region 4, a Schottky junction 5, a gate insulating film 6, a gate electrode 7, an interlayer insulating film 8, a source electrode 9, and a drain electrode 10 in the main region 50. In addition, hereinafter, a region made of a semiconductor material including the semiconductor substrate 1, the drift layer 2, the well region 3, the source region 4, etc. may sometimes be referred to as a semiconductor layer.

[0049] An n-type drift layer 2 is provided on the n-type semiconductor substrate 1. The drift layer 2 occupies most of the semiconductor layer and constitutes the main part of the semiconductor layer. On the surface layer of the drift layer 2, a p-type well region 3 is selectively provided. On the surface layer of the well region 3, an n-type source region 4 is selectively provided.

[0050] A gate insulating film 6 is formed on the well region 3 and the source region 4 so as to face the well region 3 and the source region 4. A gate electrode 7 is partially formed on the gate insulating film 6. The gate electrode 7 is disposed so as to face the well region 3, the source region 4, and the drift layer 2 with the gate insulating film 6 interposed therebetween.

[0051] In the main region 50, an interlayer insulating film 8 is provided on the gate electrode 7 so as to cover the gate electrode 7. A source electrode 9 (first main electrode) is provided on the interlayer insulating film 8 so as to cover the interlayer insulating film 8. The source electrode 9 is electrically connected to the well region 3, the source region 4, and the drift layer 2 through a contact hole formed in the interlayer insulating film 8. The source electrode 9 is ohmically connected to the well region 3 and the source region 4.

[0052] On the semiconductor substrate 1, a drain electrode 10 (second main electrode) is provided on the surface opposite to the surface where the source electrode 9 is provided. The source electrode 9 is provided on the front (first main surface) side of the semiconductor layer (semiconductor substrate 1), and the drain electrode 10 is provided on the back (second main surface) side facing the front of the semiconductor layer (semiconductor substrate 1).

[0053] The main region 50 has a MOSFET structure. That is, when a positive voltage of a certain value or more is applied to the gate electrode 7 relative to the source electrode 9, a channel is formed in a region where the well region 3 on the drift layer 2 is in contact with the gate electrode 7 via the gate insulating film 6. As a result, the source region 4 and the drift layer 2 are in a conductive state. In this way, the semiconductor device 101 controls the current flowing between the source electrode 9 and the drain electrode 10 by controlling the voltage applied to the gate electrode 7.

[0054] A plurality of unit cells, which are the minimum unit structure forming the above-mentioned MOSFET structure, are arranged in the main region 50. The unit cells may be arranged in a stripe shape (comb shape) or in a lattice shape.

[0055] In the main region 50, a Schottky junction 5 is provided between the source electrode 9 and the drift layer 2, at a portion where the source electrode 9 and the drift layer 2 are in contact. A Schottky barrier diode (SBD) is formed by the Schottky junction 5. The SBD (second diode) is a diode whose rise voltage is lower than the operating voltage of the pn diode including the well region 3 and the drift layer 2. In addition, the SBD is a unipolar diode that can only be energized in one direction, which does not allow a forward current to flow but only allows a return current to flow. The SBD can also be formed in a dispersed manner at multiple locations in the main region 50.

[0056] Figure 3 (a) is a schematic cross-sectional view showing a cross section of a portion of the sensing region 60. Figure 3 As shown in (a), the semiconductor device 101 includes a semiconductor substrate 1, a drift layer 2, a sense well region 13, a sense source region 14, a Schottky junction 15, a sense gate insulating film 16, a gate electrode 7, a sense interlayer insulating film 18, a sense source electrode 19, and a drain electrode 10 in an active sense region 61. In addition, a semiconductor substrate 1, a drift layer 2, a dummy sense well region 23, a Schottky junction 25, a dummy sense gate insulating film 26, a gate electrode 7, a dummy sense interlayer insulating film 28, a sense source electrode 19, and a drain electrode 10 are arranged in a dummy sense region 62.

[0057] In addition, hereinafter, the sensing well region 13 and the dummy sensing well region 23 including the well region 3 are sometimes referred to as respective well regions, etc. The gate insulating film 6, the sensing gate insulating film 16, and the dummy sensing gate insulating film 26 are sometimes collectively referred to as respective gate insulating films, etc. The interlayer insulating film 8, the sensing interlayer insulating film 18, and the dummy sensing interlayer insulating film 28 are sometimes collectively referred to as respective interlayer insulating films, etc. The source electrode 9 and the sensing source electrode 19 are sometimes collectively referred to as respective source electrodes, etc.

[0058] like Figure 3As shown in (a), on the surface layer of the drift layer 2, independently of the well region 3, a p-type sensing well region 13 (first semiconductor region) is selectively provided. On the surface layer of the sensing well region 13, an n-type sensing source region 14 (second semiconductor region) is selectively provided. In addition, on the surface layer of the drift layer 2, independently of the well region 3 and the sensing well region 13, a p-type dummy sensing well region 23 (third semiconductor region) is selectively provided. The sensing well region 13 is not interrupted by the dummy sensing well region 23 and is formed as a single piece and disposed at one location in a plan view. The dummy sensing well region 23 is disposed around the sensing well region 13 so as to sandwich or surround the sensing well region 13. In a plan view, the total area of the dummy sensing well region 23 is larger than that of the sensing well region 13.

[0059] On the sensing well region 13 and the sensing source region 14, a sensing gate insulating film 16 is formed facing the sensing well region 13 and the sensing source region 14. On the dummy sensing well region 23, a dummy sensing gate insulating film 26 is formed facing the dummy sensing well region 23.

[0060] On the sensing gate insulating film 16 and the dummy sensing gate insulating film 26, a gate electrode 7 is partially formed. In the active sensing region 61, the gate electrode 7 is disposed so as to face the sensing well region 13, the sensing source region 14, and the drift layer 2 with the sensing gate insulating film 16 interposed therebetween. In addition, in the dummy sensing region 62, the gate electrode 7 is disposed so as to face the dummy sensing well region 23 and the drift layer 2 with the dummy sensing gate insulating film 26 interposed therebetween.

[0061] In addition, the gate electrode 7 is connected in the main region 50, the sensing region 60, and the boundary region 70, respectively. That is, the gate electrode 7 is connected to each other in a cross section not shown in Figure 2 、 Figure 3 (a).

[0062] In the active sensing region 61, a sensing interlayer insulating film 18 is provided on the gate electrode 7 so as to cover the gate electrode 7. In addition, in the dummy sensing region 62, a dummy sensing interlayer insulating film 28 is provided on the gate electrode 7 so as to cover the gate electrode 7.

[0063] On the sensing interlayer insulating film 18 and the dummy sensing interlayer insulating film 28, a sensing source electrode 19 (third main electrode) is provided so as to cover these interlayer insulating films. The sensing source electrode 19 is formed independently of the source electrode 9. Specifically, the sensing source electrode 19 is formed physically separated from the source electrode 9. In a plan view, the total area of the sensing source electrode 19 is smaller than that of the source electrode 9.

[0064] The sensing source electrode 19 is electrically connected to the sensing well region 13, the sensing source region 14, the dummy sensing well region 23 and the drift layer 2 via a contact hole formed in the sensing interlayer insulating film 18 or the dummy sensing interlayer insulating film 28. The sensing source electrode 19 is ohmically connected to the sensing well region 13, the sensing source region 14 and the dummy sensing well region 23.

[0065] In addition, the dummy sensing well region 23 is not ohmically connected to the source electrode 9. Preferably, the dummy sensing well region 23 is not connected to the source electrode 9.

[0066] In the semiconductor substrate 1, a drain electrode 10 is provided on the surface opposite to the surface provided with the sensing source electrode 19. The sensing source electrode 19 is provided on the front surface (first main surface) side of the semiconductor layer (semiconductor substrate 1), and the drain electrode 10 is provided on the back surface (second main surface) side opposite to the front surface of the semiconductor layer (semiconductor substrate 1). The drain electrode 10 extends from the main region 50 to the sensing region 60, that is, it is provided on the entire back surface of the semiconductor substrate 1.

[0067] The active sensing region 61 has a MOSFET structure. That is, when a positive voltage of a certain value or more is applied to the gate electrode 7 relative to the sensing source electrode 19, a channel is formed in the region where the sensing well region 13 is in contact with the gate electrode 7 via the sensing gate insulating film 16. As a result, the sensing source region 14 and the drift layer 2 are in a conductive state. On the other hand, in the dummy sensing region 62, a source region is not formed in the dummy sensing well region 23. Therefore, even if a positive voltage of a certain value or more is applied to the gate electrode 7 relative to the sensing source electrode 19, a current path flowing from the drain electrode 10 to the sensing source electrode 19 is not formed in the dummy sensing region 62.

[0068] A plurality of unit cells, which are the smallest unit structure forming the above-mentioned MOSFET structure, are arranged in the active sensing region 61. A plurality of unit cells, which are the smallest unit structure including the dummy sensing well region 23, etc., are arranged in the dummy sensing region 62. The unit cells may be arranged in a stripe shape (comb shape) or in a lattice shape.

[0069] In the active sensing region 61, between the sensing source electrode 19 and the drift layer 2, a Schottky junction 15 is provided at the portion where the sensing source electrode 19 and the drift layer 2 are in contact. Further, in the dummy sensing region 62, between the sensing source electrode 19 and the drift layer 2, a Schottky junction 25 is formed at the portion where the sensing source electrode 19 and the drift layer 2 are in contact. An SBD is formed by the Schottky junction 15 or the Schottky junction 25. This SBD is a diode whose rising voltage is lower than the operating voltage of a pn diode including the sensing well region 13 or the dummy sensing well region 23 and the drift layer 2. Further, the SBD is a unipolar type diode that allows only reverse current to flow and does not allow forward current to flow. The SBD may also be formed at a plurality of locations in a dispersed manner within the sensing region 60.

[0070] In addition, regarding the Schottky junction 15 and the Schottky junction 25, for convenience, they are separately named according to the formation positions, but substantially have the same structure and function. Therefore, the Schottky junction 15 and the Schottky junction 25 may sometimes be collectively referred to as the Schottky junction 25 or the like. Further, the junction formed at the boundary between the active sensing region 61 and the dummy sensing region 62 may be either the Schottky junction 15 or the Schottky junction 25.

[0071] The dummy sensing region 62, as Figure 3 shown in (a), has a counter region FA in which the dummy sensing well region 23 faces the gate electrode 7 across the dummy sensing gate insulating film 26. The Schottky junction 25 and the counter region FA are arranged to coexist in a mixed manner within the dummy sensing region 62.

[0072] As Figure 1 shown, around the sensing region 60, a boundary region 70 is provided so as to surround the sensing region 60. The boundary region 70 is a region different from the main region 50 and the sensing region 60. Although not shown in Figure 2 and Figure 3 (a), in the boundary region 70, a boundary well region 33 provided on the surface layer of the drift layer 2 is disposed.

[0073] In addition, the cross-section of the semiconductor device 101 is not limited to Figure 3 the example shown in (a), and may also be, for example, a structure as shown in Figure 3 (b).

[0074] Figure 4 is Figure 1 an enlarged view of the sensing region 60 and its peripheral portion, and is a diagram showing an example of the arrangement pattern of each region within the sensing region 60. In addition, in Figure 4In [the figure], for simplicity, the upper surface of the semiconductor layer with the gate insulating films, gate electrodes 7, interlayer insulating films, and sense source electrodes 19 removed is shown. Additionally, Figure 4 The A-A' cross-section of Figure 3 corresponds to

[0075] In Figure 4 the unit cells that make up the active sensing region 61 and the dummy sensing region 62 are arranged in a striped (comb-shaped) pattern. In the active sensing region 61, the Schottky junction 15 is surrounded by the sensing well region 13 and the sense source region 14. Additionally, in the dummy sensing region 62, the Schottky junction 25 is surrounded by the dummy sensing well region 23.

[0076] Figure 5 is Figure 1 an enlarged view of the sensing region 60 and its surrounding portion shown in Figure 5 and is a diagram showing another example of the arrangement pattern of the regions within the sensing region 60. Furthermore, in Figure 5 for simplicity, the upper surface of the semiconductor layer with the gate insulating films, gate electrodes 7, interlayer insulating films, and sense source electrodes 19 removed is also shown. Additionally, Figure 5 the B-B' cross-section of Figure 3 corresponds to

[0077] In Figure 5 similar to Figure 4 the unit cells that make up the active sensing region 61 and the dummy sensing region 62 are arranged in a striped (comb-shaped) pattern. On the other hand, different from Figure 4 in the active sensing region 61, the sensing well region 13 and the sense source region 14 are surrounded by the Schottky junction 15. Additionally, in the dummy sensing region 62, the dummy sensing well region 23 is surrounded by the Schottky junction 25.

[0078] Figure 6 is Figure 1 an enlarged view of the sensing region 60 and its surrounding portion shown in Figure 6 and is a diagram showing another example of the arrangement pattern of the regions within the sensing region 60. Furthermore, Figure 6 for simplicity, the upper surface of the semiconductor layer with the gate insulating films, gate electrodes 7, interlayer insulating films, and sense source electrodes 19 removed is also shown. Additionally, Figure 6 the A-A' cross-section of Figure 3 corresponds to

[0079] In Figure 6In [the figure], they are arranged in a unit cell shape that constitutes the active sensing region 61 and the dummy sensing region 62. In the active sensing region 61, the Schottky junction 15 is surrounded by the sensing well region 13 and the sensing source region 14. Further, in the dummy sensing region 62, the Schottky junction 25 is surrounded by the dummy sensing well region 23.

[0080] Figure 7 is Figure 1 an enlarged view of the sensing region 60 and its peripheral part shown in [the figure], and is a figure showing another example of the arrangement pattern of each region within the sensing region 60. Further, in Figure 7 [the figure], the upper surface of the semiconductor layer with each gate insulating film, gate electrode 7, each interlayer insulating film, the sensing source electrode 19, etc. removed is also shown for simplicity. Further, Figure 7 the A-A' cross-section of Figure 3 corresponds to

[0081] In Figure 7 [the figure], the structure of the sensing region 60 is substantially the same as the structure shown in Figure 4 [the figure]. As a point different from Figure 4 [the figure], in Figures 4 to 6 [the figure], the sensing well region 13 and the dummy sensing well region 23 of the sensing region 60 are separated from the boundary well region 33 of the boundary region 70. In contrast, in Figure 7 [the figure], the sensing well region 13 and the dummy sensing well region 23 of the sensing region 60 are different in terms of being connected to the boundary well region 33 of the boundary region 70.

[0082] In Figures 4 to 7 [the figure], the Schottky junction 25 is periodically provided within the dummy sensing region 62. Further, in Figure 4 , Figure 6 and Figure 7 [the figure], the Schottky junction 25 is provided at a plurality of locations in a dispersed manner within the dummy sensing region 62.

[0083] On the dummy sensing well region 23, a gate electrode 7 is formed as shown in Figure 3 [the figure]. Therefore, the opposed region FA shown in Figure 3 [the figure] is alternately repeated with the Schottky junction 25 as shown in Figures 4 to 7 [the figure] in a plan view. Preferably, the Schottky junction 25 is alternately repeated within the dummy sensing region 62 in the direction from the boundary region 70 toward the active sensing region 61. Further, the Schottky junction 25 is arranged within the dummy sensing region 62 so as to be 2 times or less the arrangement interval of the Schottky junction 5 in the main region 50. Preferably, the Schottky junction 25 is arranged within the dummy sensing region 62 at an interval of 1 [μm] or more and 100 [μm] or less.

[0084] Regarding the semiconductor device 101, the configuration pattern of each region within the sensing region 60 can be Figures 4 to 7 any of the patterns. In addition, Figures 4 to 7 merely for illustration, the configuration pattern is not limited to Figures 4 to 7 the examples shown, and can also be other configuration patterns similar to them.

[0085] The semiconductor substrate 1, the drift layer 2, the well region 3, the source region 4, the sensing well region 13, the sensing source region 14, and the dummy sensing well region 23 are each formed of silicon carbide (SiC). As the materials for the gate insulating film 6, the interlayer insulating film 8, the sensing gate insulating film 16, the sensing interlayer insulating film 18, the dummy sensing gate insulating film 26, and the dummy sensing interlayer insulating film 28, for example, silicon dioxide (SiO2) can be used. As the material for the gate electrode 7, for example, polysilicon can be used. As the materials for the source electrode 9, the sensing source electrode 19, and the drain electrode 10, nickel, titanium, aluminum, gold, platinum, copper, and molybdenum and their alloys can be used.

[0086] <Manufacturing Method>

[0087] Next, the manufacturing method of the semiconductor device 101 will be described. First, a substrate having a semiconductor substrate 1 and a drift layer 2 epitaxially grown on the upper surface of the semiconductor substrate 1 is prepared. The n-type impurity concentration of the drift layer 2 is lower than the n-type impurity concentration of the semiconductor substrate 1. The thickness and impurity concentration of the drift layer 2 are arbitrarily set according to the designed breakdown voltage of the semiconductor device 101. For example, the thickness of the drift layer 2 can be made 1 [μm] to 200 [μm], and the impurity concentration can be made 1.0×10 14 [cm -3 to 1.0×10 16 [cm -3 .

[0088] Next, using an implantation mask (e.g., photoresist, silicon oxide film) patterned by photolithography, ions of impurities (dopants) are implanted into the surface of the drift layer 2. Thus, a p-type well region 3, a sensing well region 13, and a dummy sensing well region 23, and an n-type source region 4 and a sensing source region 14 are formed. The ion implantation for forming each region can be performed in any order.

[0089] For example, the thickness and impurity concentration of each region can be set as follows. That is, the thickness of the well region 3, the sensing well region 13, and the dummy sensing well region 23 can be made 0.1 [μm] to 2 [μm], for example. In addition, the p-type impurity concentration of these regions exceeds the n-type impurity concentration of the drift layer 2, and the maximum impurity concentration can be made 1.0×10 15 [cm -3 to 1.0×1019 [cm -3 .

[0090] The thickness of the source region 4 is set to be smaller than that of the well region 3, and the thickness of the sense source region 14 is set to be smaller than that of the sense well region 13. The thicknesses of the source region 4 and the sense source region 14 can be, for example, 0.05 [μm] to 1 [μm]. The n-type impurity concentration of the source region 4 exceeds the p-type impurity concentration of the well region 3, and the n-type impurity concentration of the sense source region 14 exceeds the p-type impurity concentration of the sense well region 13. The maximum impurity concentration of the source region 4 and the sense source region 14 can be, for example, 1.0×10 16 [cm -3 to 1.0×10 20 [cm -3 .

[0091] After the above ion implantation, in order to activate the impurities implanted into the drift layer 2, heat treatment of the substrate (also referred to as activation annealing) is performed.

[0092] Next, on the upper surface of the semiconductor layer, an insulating film serving as a base for the gate insulating film 6, the sense gate insulating film 16, and the dummy sense gate insulating film 26 is formed, for example, by a thermal oxidation method or a deposition method. Thereafter, for example, high-temperature heat treatment, nitridation treatment, oxidation treatment, etc. can also be performed. By performing these treatments, the characteristics of each gate insulating film and the characteristics of the interface between each well region and each gate insulating film as the part where the channel is formed can be improved.

[0093] Next, a conductive layer such as polysilicon is deposited on the insulating film formed as described above. Moreover, an etch mask formed by photolithographic processing on the conductive layer is used to selectively etch the conductive layer. Thereby, the gate electrode 7 is formed.

[0094] Next, on the gate electrode 7, an insulating film serving as a base for the interlayer insulating film 8, the sense interlayer insulating film 18, and the dummy sense interlayer insulating film 28 is formed, for example, by CVD method. Moreover, for example, by selectively removing each insulating film using a dry etching method, the gate insulating film 6, the sense gate insulating film 16, the dummy sense gate insulating film 26, and the interlayer insulating film 8, the sense interlayer insulating film 18, and the dummy sense interlayer insulating film 28 are formed. At this time, contact holes are formed between each gate insulating film and each interlayer insulating film.

[0095] Next, on the interlayer insulating film 8, the sense interlayer insulating film 18, and the dummy sense interlayer insulating film 28, a metal material serving as a base for the source electrode 9 and the sense source electrode 19 is deposited, for example, by sputtering. Moreover, for example, by performing patterning using lift-off and wet etching, the source electrode 9 and the sense source electrode 19 are formed.

[0096] The source electrode 9 is connected to the well region 3 and the source region 4 through an ohmic contact via a contact hole, and is connected to the drift layer 2 through a Schottky contact. In addition, the sense source electrode 19 is connected to the sense well region 13, the sense source region 14, and the dummy sense well region 23 through an ohmic contact via a contact hole, and is connected to the drift layer 2 through a Schottky contact. Thus, a Schottky junction 5 is formed at the portion where the source electrode 9 and the drift layer 2 are in contact, and a Schottky junction 15 and a Schottky junction 25 are formed at the portion where the sense source electrode 19 and the drift layer 2 are in contact.

[0097] Next, a drain electrode 10 that makes an ohmic contact with the semiconductor substrate 1 is formed on the back surface of the semiconductor substrate 1. In addition, the semiconductor substrate 1 may be thinned by grinding or the like, and then, a drain electrode 10 that makes an ohmic contact with the back surface of the drift layer 2 is formed.

[0098] Through the above processes, it is possible to obtain Figure 1 the semiconductor device 101 of Embodiment 1 as shown in

[0099] <Feature>

[0100] Next, the current detection operation and the like in the semiconductor device 101 will be described. Figure 8 is a circuit diagram schematically showing the structure of the semiconductor device 101 as a circuit. As can be seen from Figure 8 the forward current flowing in from the drain electrode 10 flows to the source electrode 9 via the main region 50, and at the same time, also flows to the sense source electrode 19 via the sense region 60. Therefore, a galvanometer is connected to the sense source electrode 19 to measure the current flowing in the sense region 60, and based on this measurement result, it is possible to estimate by calculation the current flowing through the entire semiconductor device 101 including the main region 50. In addition, by diverting a part of the current flowing in from the drain electrode 10 to the sense region 60 and using the measurement result of the current in the sense region 60, compared with the case of directly measuring the current flowing in the main region 50, it is possible to detect the current flowing through the semiconductor device 101 with low loss.

[0101] In addition, in a conventional semiconductor device, in order to suppress the loss caused by the current flowing in the sense region, it is necessary to reduce the area of the sense region to reduce the proportion of the diverted current. However, when reducing the area of the sense region, the electrostatic capacitance also becomes smaller, so there is a possibility that the semiconductor device may be damaged due to a surge voltage such as static electricity applied by a human body during operation.

[0102] Therefore, the semiconductor device 101 of Embodiment 1 is as shown in Figure 3As shown, a dummy sensing region 62 is provided with a dummy sensing well region 23 having a total area larger than that of the sensing well region 13. In a facing region FA where the dummy sensing well region 23 and the gate electrode 7 face each other with the dummy sensing gate insulating film 26 interposed therebetween, a capacitor is formed between the sensing source electrode 19 and the gate electrode 7. Therefore, by designing the area of the dummy sensing region 62 to be large, the electrostatic capacitance of this capacitor can be increased, the electric fields in the sensing gate insulating film 16 and the dummy sensing gate insulating film 26 when applying static electricity can be alleviated, and the dielectric breakdown of these gate insulating films can be suppressed. That is, the electrostatic tolerance of the semiconductor device 101 can be improved.

[0103] In addition, in the dummy sensing region 62, when a positive voltage equal to or higher than a certain level is applied to the gate electrode 7 with respect to the sensing source electrode 19, an inversion layer is formed in a region where the dummy sensing well region 23 is in contact with the gate electrode 7 with the dummy sensing gate insulating film 26 interposed therebetween. Therefore, the electrostatic capacitance can be further increased by the amount of charge of the minority carriers forming the inversion layer.

[0104] As Figure 3 shown, etc., a source region is not formed in the dummy sensing well region 23. Therefore, even when a voltage is applied to the gate electrode 7, although an inversion layer is formed at the interface between the dummy sensing well region 23 and the gate electrode 7 as described above, a conduction path connecting from the drift layer 2 to the sensing source electrode 19 is not formed. Therefore, in the sensing region 60, a forward current does not flow into the dummy sensing region 62 but only flows into the active sensing region 61. Therefore, by designing the size of the active sensing region 61 to be small, the proportion of the current flowing into the sensing region 60 in the entire semiconductor device 101 can be made smaller than that in the main region 50, and the loss can be suppressed.

[0105] Therefore, by providing the dummy sensing region 62, current loss in the sensing region 60 can be suppressed, and a desired electrostatic capacitance can be ensured to improve the electrostatic tolerance of the semiconductor device 101.

[0106] In addition, the following problems can be cited as problems peculiar to semiconductor devices using silicon carbide. In semiconductor devices such as MOSFETs, a pn diode including a well region and a drift layer is built in. In the MOSFET structure, a forward current flows. In contrast, in the pn diode, a reverse current, i.e., a backflow current (hereinafter referred to as bipolar conduction), sometimes flows. When bipolar conduction occurs in the pn diode, minority carriers injected into the drift layer recombine with majority carriers in the drift layer, thereby generating energy. As a result, there is a possibility of so-called bipolar degradation in which the periodic structure of the semiconductor is disordered, i.e., crystal defects acquire energy and expand, deteriorating the element. When bipolar degradation occurs, the element resistance for the forward current increases, and the conduction loss in the case of applying the same current density becomes large. In wide-bandgap semiconductors such as silicon carbide, bipolar degradation is likely to become a problem because the energy generated during the above recombination is greater than that in silicon or the like.

[0107] Regarding the suppression of bipolar degradation, there is a technique such as synchronous rectification. This is a technique of applying a voltage to the gate electrode in synchronization with the timing when a backflow current flows in the semiconductor device, and causing the backflow current to flow in the formed channel. By synchronous rectification, bipolar conduction of the pn diode can be suppressed in the region where the MOSFET structure in which the channel is formed exists (the main region 50, the active sensing region 61, etc. of the semiconductor device 101).

[0108] However, in a region where no channel is formed (such as the dummy sensing region 62 of the semiconductor device 101), even if the above synchronous rectification is performed, the pn diode still conducts bipolar conduction. Regarding the dummy sensing region 62, as described above, in order to suppress the current flowing in the sensing region 60 to a low level, it is designed so that the current does not flow through the channel. Therefore, in synchronous rectification, bipolar conduction in the dummy sensing region 62 cannot be suppressed. Furthermore, since the dummy sensing well region 23 is formed to have a larger area than the sensing well region 13, the probability of element bipolar degradation is also high when the pn diode conducts in the dummy sensing well region 23.

[0109] Therefore, the semiconductor device 101 of Embodiment 1 is provided with an SBD including a Schottky junction 25 formed at a portion where the sensing source electrode 19 is in contact with the drift layer 2, as shown in Figure 3 etc. The turn-on voltage of this SBD is lower than the operating voltage of the pn diode including the dummy sensing well region 23 and the drift layer 2. As a result, the backflow current flows into the SBD and hardly flows into the pn diode, so bipolar degradation can be suppressed.

[0110] As described above, bipolar degradation can be suppressed in the portion near the SBD, but the possibility of bipolar degradation remains in the portion far from the SBD. On the other hand, when the number and area of the SBD are increased too much, the capacitance in the dummy sensing region 62 will decrease. Therefore, the semiconductor device 101 of Embodiment 1 is configured such that Figure 3 the opposed region FA and the SBD (Schottky junction 25) shown are mixedly present within the dummy sensing region 62. Preferably, the SBD (Schottky junction 25) is Figures 4 to 7 configured to be alternately repeated with the opposed region FA as shown in a plan view. Thereby, the capacitor formed between the sensing source electrode 19 and the gate electrode 7 in the opposed region FA and the SBD are respectively arranged in the dummy sensing region 62 with good balance. Therefore, it is possible to suppress the decrease in capacitance in the dummy sensing region 62 and suppress bipolar degradation.

[0111] Preferably, the SBD is alternately repeated in the dummy sensing region 62 in the direction from the boundary region 70 toward the active sensing region 61. Thereby, the SBD is uniformly arranged at necessary portions in the dummy sensing region 62, so that it is possible to suppress the decrease in capacitance in the dummy sensing region 62 and suppress bipolar degradation.

[0112] In the semiconductor device 101, a Schottky junction 5 is formed in the main region 50, and a Schottky junction 15 is formed in the active sensing region 61. That is, in the semiconductor device 101, SBDs are provided not only in the dummy sensing region 62 but also in the main region 50 and the active sensing region 61. Thereby, even without synchronous rectification, bipolar conduction of the pn diode can be suppressed throughout the semiconductor device 101.

[0113] Preferably, the interval for arranging the SBD is set as follows. In the main region 50, the distance between the pn junction (the portion where the well region 3 and the drift layer 2 are in contact) with the farthest distance to the nearest SBD (Schottky junction 5) and this nearest SBD is defined as the distance x. In addition, in the dummy sensing region 62, the distance between the pn junction (the portion where the dummy sensing well region 23 and the drift layer 2 are in contact) with the farthest distance to the nearest SBD (Schottky junction 25) and this nearest SBD is defined as the distance y. At this time, the distance y in the dummy sensing region 62 is designed to be 2 times or less of the distance x in the main region 50. That is, in the dummy sensing region 62, the SBDs are arranged to be 2 times or less of the arrangement interval of the SBDs in the main region 50.

[0114] Regarding the reverse current, based on the distances defined as the above-mentioned distance x and distance y, the maximum value (hereinafter referred to as the maximum unipolar current value) that can flow through the SBD without energizing the pn diode is determined. In the dummy sensing region 62, when the maximum value Y of the distance y is set to achieve the desired maximum unipolar current value, if the distance y is further increased from the maximum value Y, the pn diode starts to conduct electricity, and the current flowing through the pn diode increases rapidly. For this reason, the configuration interval of the SBD is set as described above.

[0115] Preferably, the SBDs are arranged at intervals of 1 [μm] or more and 100 [μm] or less within the dummy sensing region 62. By arranging at such intervals, it is possible to suppress the reduction of the electrostatic capacitance in the dummy sensing region 62 and suppress bipolar degradation.

[0116] The SBDs may also be Figures 4 to 7 as shown, periodically arranged within the dummy sensing region 62. In addition, the SBDs may also be Figure 4 、 Figure 6 、and Figure 7 as shown, arranged in a dispersed manner at multiple locations within the dummy sensing region 62. Preferably, within the dummy sensing region 62, the SBDs are arranged such that the distance between the pn junction (i.e., the pn junction farthest from the SBD) of the farthest SBD and the nearest SBD becomes half or less of the configuration interval of the SBD. By having such a configuration, it is possible to suppress the reduction of the electrostatic capacitance in the dummy sensing region 62 and suppress bipolar degradation.

[0117] The semiconductor device 101 of Embodiment 1 is preferably Figure 1 as shown, the active sensing region 61 (sensing well region 13) is arranged as a single block without being divided by the dummy sensing region 62 (dummy sensing well region 23) in a top view. The reason is as follows. Regarding the forward current flowing through the active sensing region 61, a part of it diffuses and returns to the surrounding dummy sensing region 62. Therefore, when the active sensing region 61 is configured to be divided by the dummy sensing region 62, the part of the forward current that diffuses and returns to the dummy sensing region 62 increases, and it seems that the resistance of the sensing region 60 is low, and there is a possibility that the current flowing through the main region 50 cannot be correctly known, so it is desired to avoid this.

[0118] Regarding the semiconductor device 101 of Embodiment 1, the dummy sense well region 23 is not ohmically connected to the source electrode 9. The reason is as described below. The dummy sense well region 23 is ohmically connected to the sense source electrode 19. Therefore, when the dummy sense well region 23 and the source electrode 9 are ohmically connected, the sense source electrode 19 and the source electrode 9 are electrically connected via the dummy sense well region 23, and current flows between the two electrodes, which may prevent the current flowing through the semiconductor device 101 from being correctly detected. Thus, it is desired to avoid this situation.

[0119] As described above, according to the present Embodiment 1, it is possible to suppress the reduction of the electrostatic capacitance and suppress the bipolar degradation in the dummy sense region 62. Therefore, it is possible to ensure the desired electrostatic capacitance in the dummy sense region 62 and suppress the increase in conduction loss due to the expansion of crystal defects. Thus, the reliability of the semiconductor device 101 can be improved.

[0120] <Modification Example>

[0121] Next, a modification example of the semiconductor device 101 according to Embodiment 1 will be described. Figure 9 (a) is a cross-sectional schematic view showing a part of the sense region 60 according to the modification example of Embodiment 1. Figure 9 The structure shown in (a) is the same as that of Figure 3 (a) except for the dummy sense well region 23. In the Figure 9 structure of (a), the dummy sense well region 23 is provided without an interval below the gate electrode 7, and the drift layer 2 does not contact the dummy sense gate insulating film 26. In addition, the cross-section of the semiconductor device 101 is not limited to the Figure 9 example shown in (a). For example, it may also be a structure as shown in Figure 9 (b).

[0122] Figure 10 is Figure 1 an enlarged view of the sense region 60 and its peripheral part shown in, and is a diagram showing an example of the arrangement pattern of each region in the sense region 60. In addition, in Figure 10 , for simplicity, the upper surface of the semiconductor layer after removing each gate insulating film, gate electrode 7, each interlayer insulating film, sense source electrode 19, etc. is shown. Additionally, Figure 10 the C-C' cross-section of Figure 9 corresponds to (a).

[0123] In Figure 10In [the figure], the unit cells that make up the active sensing region 61 and the dummy sensing region 62 are arranged in a stripe (comb) shape. In the active sensing region 61, the Schottky junction 15 is surrounded by the sensing well region 13 and the sensing source region 14. Further, in the dummy sensing region 62, the Schottky junction 25 is surrounded by the dummy sensing well region 23.

[0124] Figure 11 is Figure 1 an enlarged view of the sensing region 60 and its peripheral part shown in [the figure], and is a figure showing another example of the arrangement pattern of the respective regions within the sensing region 60. Further, in Figure 11 [the figure], for simplicity, the upper surface of the semiconductor layer with the respective gate insulating films, the gate electrode 7, the respective interlayer insulating films, the sensing source electrode 19, etc. removed is also shown. Further, Figure 11 the D-D' cross section of Figure 9 corresponds to

[0125] In Figure 11 [the figure], similar to Figure 10 [the figure], the unit cells that make up the active sensing region 61 and the dummy sensing region 62 are arranged in a stripe (comb) shape. On the other hand, different from Figure 10 [the figure], in the active sensing region 61, the sensing well region 13 and the sensing source region 14 are surrounded by the Schottky junction 15. Further, in the dummy sensing region 62, the dummy sensing well region 23 is surrounded by the Schottky junction 25.

[0126] Figure 12 is Figure 1 an enlarged view of the sensing region 60 and its peripheral part shown in [the figure], and is a figure showing another example of the arrangement pattern of the respective regions within the sensing region 60. Further, in Figure 12 [the figure], for simplicity, the upper surface of the semiconductor layer with the respective gate insulating films, the gate electrode 7, the respective interlayer insulating films, and the sensing source electrode 19, etc. removed is also shown. Further, Figure 12 the C-C' cross section of Figure 9 corresponds to

[0127] In Figure 12 [the figure], the unit cells that make up the active sensing region 61 and the dummy sensing region 62 are arranged in a lattice shape. In the active sensing region 61, the Schottky junction 15 is surrounded by the sensing well region 13 and the sensing source region 14. Further, in the dummy sensing region 62, the Schottky junction 25 is surrounded by the dummy sensing well region 23.

[0128] In Figures 10 to 12 [the figure], the Schottky junction 25 is periodically provided within the dummy sensing region 62. Further, in Figure 10 and Figure 12In this case, the Schottky junctions 25 are disposed at a plurality of positions in a dispersed manner within the dummy sensing region 62.

[0129] In the structure of the modified example, as Figures 10 to 12 shown, the area of the dummy sensing well region 23 opposed to the gate electrode 7 is larger than Figures 4 to 7 the structure shown. That is, since the area of the dummy sensing well region 23 opposed to the gate electrode 7 can be enlarged, the electrostatic capacitance per unit area between the sensing source electrode 19 and the gate electrode 7 can be further increased.

[0130] In the Figures 10 to 12 related to the modified example, similarly to Figures 4 to 7 , the SBD (Schottky junction 25) is alternately and repeatedly provided with the Figure 9 opposed region FA shown in a plan view. Therefore, a decrease in the electrostatic capacitance in the dummy sensing region 62 can be suppressed, and bipolar degradation can be suppressed. In addition, the same effect as in the case of the Figures 4 to 7 shown structure can be obtained.

[0131] In addition, in the above, as the arrangement pattern of each region within the sensing region 60, those of the first embodiment and its modified example Figures 4 to 7 , Figures 10 to 12 are described, but are not limited thereto. For example, in each arrangement pattern, the number of unit cells may be several. In addition, the arrangement pattern may be other arrangement patterns similar to these. For example, it may be a shape of a lattice-shaped unit cell in which Figure 6 or Figure 12 is arranged to be offset from each other for each column, or a honeycomb shape in which a plurality of hexagonal unit cells are arranged.

[0132] In addition, the arrangement pattern of each region is not limited to a periodic structure such as Figures 4 to 7 , Figures 10 to 12 . For example, various examples are considered such as not making all the connection portions between the drift layer 2 and the sensing source electrode 19 Schottky junctions, arranging SBDs every other one, or mixing SBDs arranged every other one and SBDs arranged every two to form an irregular pattern. Even in such an arrangement pattern, by mixing and disposing SBDs and the opposed region FA within the dummy sensing region 62 or alternately and repeatedly disposing SBDs and the opposed region FA, the above-described effects can be obtained.

[0133] In addition, in the present embodiment, as Figure 2 shown, the drift layer 2 is disposed between the well regions 3 below the gate electrode 7 in contact with the gate insulating film 6. In addition, as Figure 3 , Figure 9As shown, between the sense well regions 13 below the gate electrode 7, a drift layer 2 is provided in contact with the sense gate insulating film 16. The region including the drift layer 2 between the well regions and in contact with the gate insulating film is also referred to as a JFET region or the like. In the semiconductor device 101 of Embodiment 1, these JFET regions are n-type like the drift layer 2 and have the same impurity concentration as the drift layer 2. The impurity concentration of the JFET region is not limited to this, and can also be set to be higher than the n-type impurity concentration of the drift layer 2.

[0134] Embodiment 2.

[0135] Figure 13 FIG. is a cross-sectional schematic view showing a part of the sensing region 60 of the semiconductor device 201 according to Embodiment 2. The semiconductor device 201 of Embodiment 2 is different from the semiconductor device 101 of Embodiment 1 and has a dummy sense source region 24. The dummy sense source region 24 is an n-type region selectively formed on the surface layer of the dummy sense well region 23. The dummy sense source region 24 is ohmically connected to the sense source electrode 19. The dummy sense source region 24 faces the dummy sense gate insulating film 26 and is opposed to the gate electrode 7 with the dummy sense gate insulating film 26 interposed therebetween. Other structures are the same as those of the semiconductor device 101 of Embodiment 1.

[0136] In addition, hereinafter, the sense source region 14 and the dummy sense source region 24, including the source region 4 therein, may be referred to as each source region or the like.

[0137] Next, a method for manufacturing the semiconductor device 201 will be described. In the method for manufacturing the semiconductor device 101 that can be described in Embodiment 1, the dummy sense source region 24 can be formed by the same method as that for forming the source region 4 and the sense source region 14. In addition, the dummy sense source region 24 can also be formed in a process independent of the process for forming the source region 4 and the sense source region 14. For other parts, it can be manufactured in the same manner as the semiconductor device 101.

[0138] The semiconductor device 201 of Embodiment 2 includes a dummy sense source region 24 disposed under the gate electrode 7 in the dummy sensing region 62. As a result, the electrostatic capacitance of the capacitor formed between the sense source electrode 19 and the gate electrode 7 increases. The electrostatic capacitance increases approximately to the extent that a channel is formed in the region where the dummy sense source region 24 is disposed. Since the change in the electrostatic capacitance with respect to the gate potential does not vary significantly, the electrostatic capacitance in the dummy sensing region 62 can be stably ensured.

[0139] Next, a modification of the semiconductor device 201 according to Embodiment 2 will be described. Figure 14is a cross-sectional schematic diagram showing a part of the sensing region 60 according to a modification of Embodiment 2. In Figure 13 's structure, a dummy sensing well region 23 is provided between the dummy sensing source regions 24 under the gate electrode 7 in contact with the dummy sensing gate insulating film 26. In contrast, in Figure 14 's structure, the dummy sensing source regions 24 are provided under the gate electrode 7 without a gap, and the dummy sensing well region 23 is not in contact with the dummy sensing gate insulating film 26. That is, in Figure 14 's structure, in the counter region FA, at a position facing the gate electrode 7 across the dummy sensing gate insulating film 26, the dummy sensing source regions 24 are provided, and the dummy sensing well region 23 is not in contact with the dummy sensing gate insulating film 26. For other parts, it is the same as the structure shown in Figure 13 .

[0140] In the structure of the modification, as shown in Figure 14 , the portion in contact with the gate electrode 7 across the dummy sensing gate insulating film 26 is filled with the dummy sensing source regions 24. Therefore, for the structure of the modification, the area of the dummy sensing source regions 24 is larger than that of Figure 13 's structure. Therefore, the electrostatic capacitance per unit area between the sensing source electrode 19 and the gate electrode 7 can be further increased.

[0141] In addition, in the semiconductor device 201 of Embodiment 2 and its modification, the same effects as those described in Embodiment 1 can also be obtained.

[0142] Embodiment 3.

[0143] Figure 15 is a cross-sectional schematic diagram showing a cross-section of the boundary region 70 of the semiconductor device 301 according to Embodiment 3. As shown in Figure 15 , in addition to the structure of the semiconductor device 101 or the semiconductor device 201, the semiconductor device 301 further includes a source electrode intermediate region 31, a boundary well region 33, and a Schottky junction 35 provided in the boundary region 70.

[0144] In the boundary region 70, the source electrode 9 and the sensing source electrode 19 are separated, and a source electrode intermediate region 31 is formed between the source electrode 9 and the sensing source electrode 19. A p-type boundary well region 33 is provided on the surface layer of the drift layer 2 under the source electrode intermediate region 31. The boundary well region 33 may also be formed by dividing it into multiple regions.

[0145] In the semiconductor device 301 of Embodiment 3, the boundary well region 33 is not connected to the well region 3, the sense well region 13, and the dummy sense well region 23. Further, the boundary well region 33 is not ohmically connected to the source electrode 9 and the sense source electrode 19 but is Schottky-connected. Schottky junctions 35 are respectively formed at portions where the boundary well region 33 is in contact with the source electrode 9 and the sense source electrode 19. The Schottky junctions 35 may also be formed at a plurality of portions. Other structures are the same as those of the semiconductor device 101 or the semiconductor device 201.

[0146] Next, a method for manufacturing the semiconductor device 301 will be described. In the method for manufacturing the semiconductor device 101 described in Embodiment 1, the boundary well region 33 can be formed by the same method simultaneously with the formation of the well region 3 and the sense well region 13. In addition, the boundary well region 33 may also be formed in a process independent of the processes for forming the well region 3 and the sense well region 13.

[0147] After forming a metal material that serves as a base for the source electrode 9 and the sense source electrode 19 over the interlayer insulating film 8, the sense interlayer insulating film 18, and the dummy sense interlayer insulating film 28, patterning is performed by lift-off and wet etching to separately form the source electrode 9 and the sense source electrode 19. At this time, a source electrode interval region 31 is formed between the source electrode 9 and the sense source electrode 19.

[0148] The source electrode 9 is connected to the boundary well region 33 by Schottky contact, and the sense source electrode 19 is connected to the boundary well region 33 by Schottky contact. Thereby, Schottky junctions 35 are formed at portions where the source electrode 9 is in contact with the boundary well region 33 and at portions where the sense source electrode 19 is in contact with the boundary well region 33. For other portions, the manufacturing can be performed in the same manner as the semiconductor device 101.

[0149] The boundary region 70 is an area that is necessarily required when a sense region 60 is provided in the semiconductor device. The reason is that it is necessary to separate the source electrode 9 and the sense source electrode 19. As described above, the source electrode 9 and the sense source electrode 19 are separated by lift-off and wet etching. Therefore, considering process variations, the source electrode interval region 31 is designed to have a relatively large area.

[0150] On the other hand, when the area of the drift layer 2 exposed on the surface of the semiconductor layer is too large, there is a possibility of discharging by applying a high electric field to the surface of the semiconductor layer. Therefore, it is necessary to dispose the boundary well region 33 below the source electrode interval region 31. In addition, as long as the above-described discharge can be prevented, it is sufficient, and thus it is not necessary to completely fill the surface of the semiconductor layer with the boundary well region 33 in the boundary region 70.

[0151] However, in the boundary region 70, the source electrode 9 or the sense source electrode 19 is not provided, so an SBD cannot be provided in the region 31 between the source electrodes. Here, in the boundary region 70, the distance between the pn junction (the portion where the boundary well region 33 and the drift layer 2 are in contact) that is farthest from the nearest SBD ( Figure 15 the Schottky junction 5 or the Schottky junction 25 in) and this nearest SBD is defined as the distance z. At this time, the distance z becomes a relatively large value, and there is a possibility that the pn diode including the boundary well region 33 and the drift layer 2 conducts electricity. In addition, since the ratio of the area of the boundary well region 33 to the area of the entire semiconductor device is relatively large, the probability of element bipolar degradation is also relatively high.

[0152] Therefore, as shown in the semiconductor device 301 of Embodiment 3 Figure 15 shown, the boundary well region 33 is not connected to each well region and is not ohmically connected to each source electrode. That is, the boundary well region 33 floats from each well region and each source electrode. Therefore, bipolar conduction of the pn diode including the boundary well region 33 and the drift layer 2 can be prevented.

[0153] In addition, as shown in Figure 15 shown, in the surface layer on the side close to the boundary well region 33 in the well region 3 and the dummy sense well region 23 adjacent to the boundary well region 33, no channel is formed. In other words, no JFET region is formed at the position where the boundary well region 33 is in contact. In this way, it is preferable that no forward current flows near the boundary well region 33. Since the boundary well region 33 floats, the potential is unstable and the resistance around it is likely to change. Therefore, by preventing a forward current from flowing through the boundary well region 33, the element characteristics can be stabilized.

[0154] Embodiment 4.

[0155] Figure 16 is a cross-sectional schematic view showing a cross-section of the boundary region 70 of the semiconductor device 401 according to Embodiment 4. As shown in the semiconductor device 401 Figure 16 shown, in addition to the structure of the semiconductor device 101 or the semiconductor device 201, it further includes a region 31 between source electrodes, a boundary well region 33, and an insulating film 38 provided in the boundary region 70. As a difference from the semiconductor device 301 of Embodiment 3, an insulating film 38 is added instead of forming the Schottky junction 35.

[0156] In the boundary region 70, the insulating film 38 is formed on the boundary well region 33 and the drift layer 2 so as to cover the boundary well region 33. The insulating film 38 is formed between the boundary well region 33 and the source electrode 9 and between the boundary well region 33 and the sense source electrode 19. The boundary well region 33 is configured to be separated from the source electrode 9 and the sense source electrode 19 by the insulating film 38 without being Schottky-connected thereto.

[0157] Next, a method for manufacturing the semiconductor device 401 will be described. In the method for manufacturing the semiconductor device 101 described in the first embodiment, after forming the insulating film serving as the base of the interlayer insulating film on the gate electrode 7, when selectively removing the insulating film to form the interlayer insulating film 8, the sense interlayer insulating film 18, and the dummy sense interlayer insulating film 28, the insulating film is left on the boundary well region 33 to form the insulating film 38. Alternatively, the insulating film 38 can be formed by depositing an insulating film on the semiconductor layer by CVD or the like and then patterning after activation annealing and before forming the source electrode 9 and the sense source electrode 19. For other parts, the semiconductor device 101 can be manufactured in the same manner.

[0158] In the semiconductor device 401 of the fourth embodiment, the insulating film 38 is formed between the boundary well region 33 and the source electrode 9 and between the boundary well region 33 and the sense source electrode 19. Therefore, compared with the semiconductor device 301, the boundary well region 33 is further electrically separated from the source electrode 9 and the sense source electrode 19. Therefore, in the pn diode including the boundary well region 33 and the drift layer 2, the suppression effect of bipolar conduction can be improved.

[0159] Embodiment 5.

[0160] Figure 17 FIG. is a cross-sectional schematic view showing a part of the sensing region 60 of the semiconductor device 501 according to the fifth embodiment. In the semiconductor device 501 of the fifth embodiment, the formation position of the SBD, the method for forming the gate structure, etc. are different from those of the semiconductor device 101 of the first embodiment. Other structures are the same as those of the semiconductor device 101 of the first embodiment.

[0161] The semiconductor device 501 is as Figure 17As shown, in the active sensing region 61, a groove (first groove) 41 is formed in the surface layer of the semiconductor layer between the sensing well region 13 and the sensing source region 14, penetrating through the sensing well region 13 and the sensing source region 14 to reach the drift layer 2. Further, in the dummy sensing region 62, a groove (first groove) 41 is formed in the surface layer of the semiconductor layer between the dummy sensing well regions 23, penetrating through the dummy sensing well region 23 to reach the drift layer 2. In these grooves 41, a sensing source electrode 19 is provided. In at least one of the bottom surface or the side surface of the groove 41 of the semiconductor device 501, the sensing source electrode 19 is Schottky-connected to the drift layer 2. That is, in at least one of the bottom surface or the side surface of the groove 41, an SBD is formed at a portion where the sensing source electrode 19 and the drift layer 2 face each other.

[0162] Further, in the active sensing region 61, a sensing gate insulating film 16 and a gate electrode 7 are provided in a groove that penetrates through the sensing well region 13 and the sensing source region 14 to reach the drift layer 2 from the surface of the semiconductor layer. The sensing gate insulating film 16 is in contact with the sensing well region 13 and the sensing source region 14 on the side surface of the groove. The gate electrode 7 faces the sensing well region 13 and the sensing source region 14 with the sensing gate insulating film 16 interposed therebetween.

[0163] Next, a method for manufacturing the semiconductor device 501 will be described. In the method for manufacturing the semiconductor device 101 described in the first embodiment, after forming each well region and each source region on the drift layer 2, the surface of the semiconductor layer is selectively etched using a patterned etching mask to form a groove that penetrates through the sensing well region 13 and the sensing source region 14 to reach the drift layer 2. Thereafter, in the active sensing region 61, a sensing gate insulating film 16 is formed on the bottom surface and the side surface of the groove, and a gate electrode 7 is formed so as to fill the inside of the groove.

[0164] Further, after forming each well region and each source region on the drift layer 2, the surface of the semiconductor layer is selectively etched using a patterned etching mask to form the above-described groove 41. After forming each interlayer insulating film, in the active sensing region 61 and the dummy sensing region 62, a sensing source electrode 19 is formed inside the groove 41 so as to fill the groove. The sensing source electrode 19 is connected to each well region and each source region by an ohmic contact and is connected to the drift layer 2 by a Schottky contact. Thus, Schottky junctions 15 and 25 are formed at portions where the sensing source electrode 19 and the drift layer 2 are in contact with each other. For other portions, it can be manufactured in the same manner as the semiconductor device 101.

[0165] In the semiconductor device 501 of Embodiment 5, an SBD (Schottky junction 15 or Schottky junction 25) is formed in the groove 41 at the portion where the sense source electrode 19 and the drift layer 2 are in contact. On the other hand, in the semiconductor device 101 of Embodiment 1, the SBD is formed at a position sandwiched by each well region. Therefore, in the semiconductor device 501 compared to the semiconductor device 101, the resistance of the path from the sense source electrode 19 via the SBD to the drain electrode 10 becomes lower. Therefore, in the pn diode including each well region and the drift layer 2, the suppression effect of bipolar conduction can be improved.

[0166] In addition, the semiconductor device 501 has a disadvantage that the process of forming the groove 41 is increased compared to the semiconductor device 101 of Embodiment 1. However, as described in Figure 17 , when the portion where the MOSFET structure is formed in the active sensing region 61 is of a so-called trench type, these trenches can also be formed simultaneously with the groove 41, thereby substantially eliminating the disadvantage of the increased process. In addition, by becoming a trench type, compared to a so-called planar type such as the semiconductor device 101, the on-resistance can be reduced, and the advantages can be increased.

[0167] <Modification Example>

[0168] Next, a modification example of the semiconductor device 501 according to Embodiment 5 will be described. Figure 18 FIG. is a cross-sectional schematic view showing a part of the sensing region 60 according to the modification example of Embodiment 5. In Figure 18 the shown structure, in the dummy sensing region 62, a dummy sensing gate insulating film 26 and a gate electrode 7 are provided in a groove (second groove) that penetrates the dummy sensing well region 23 from the surface of the semiconductor layer and reaches the drift layer 2. The dummy sensing gate insulating film 26 is in contact with the dummy sensing well region 23 on the side surface of the groove. The gate electrode 7 faces the dummy sensing well region 23 across the dummy sensing gate insulating film 26 on the side surface of the groove. Other structures are the same as those in Figure 17 the shown structure.

[0169] In Figure 18 the shown structure, not only the active sensing region 61 but also the structure of the dummy sensing region 62 becomes a trench type. The trench gate structure in the dummy sensing region 62 can be formed simultaneously or at different timings in the same manner as the trench gate structure in the active sensing region 61.

[0170] Figure 18 In the shown structure, since a capacitor formed between the sense source electrode 19 and the gate electrode 7 can be formed in the groove, compared to Figure 17 the shown structure, the capacitance per unit area can be increased.

[0171] Figure 19 This is a cross-sectional schematic diagram showing a part of the sensing region 60 related to another modification of Embodiment 5. In Figure 19 the shown structure, in addition to Figure 18 the shown structure, an n-type dummy sensing source region 24 similar to that described in Embodiment 2 is formed in the dummy sensing region 62. The dummy sensing source region 24 is selectively formed on the surface layer of the dummy sensing well region 23 and is ohmically connected to the sensing source electrode 19. In addition, in the dummy sensing region 62, the dummy sensing gate insulating film 26 and the gate electrode 7 are disposed in a groove (second groove) that penetrates the dummy sensing source region 24 from the surface of the semiconductor layer and reaches the dummy sensing well region 23.

[0172] In Figure 19 the structure, in the opposing region FA, at a position facing the gate electrode 7 across the dummy sensing gate insulating film 26, there is the dummy sensing source region 24, and compared to Figure 18 the shown structure, the capacitance per unit area can be increased.

[0173] In addition, in Figure 19 the shown structure, the depth of the groove in which the dummy sensing gate insulating film 26 and the gate electrode 7 are formed becomes less than the depth at which the dummy sensing well region 23 is formed in the thickness direction of the drift layer 2. Therefore, the dummy sensing gate insulating film 26 does not contact the drift layer 2 at the bottom and side surfaces of the groove. Therefore, even if the dummy sensing source region 24 is provided, no forward current flows in the dummy sensing region 62, and the loss in the sensing region 60 is not increased.

[0174] In addition, in the above, it has been described that except for the structure in which the groove 41 is formed and the sensing source electrode 19 is buried therein, the gate structures of the active sensing region 61 and the dummy sensing region 62 are trench types, but it is not limited thereto. For example, the structure of forming the groove 41 may not be adopted, and in the structures described in Embodiments 1 to 4, a trench-type gate structure may be adopted for one or both of the active sensing region 61 and the dummy sensing region 62. In addition, in the main region 50, a structure in which a groove is formed and the source electrode 9 is buried therein or a trench-type gate structure may be adopted.

[0175] In addition, each unit cell and the groove 41 constituting the trench-type gate structure may be arranged in a striped (comb-shaped) manner or in a lattice shape, and there is no limitation on the arrangement shape.

[0176] Embodiment 6.

[0177] This embodiment is an example in which the semiconductor device according to any one of the above-described Embodiments 1 to 5 is applied to a power conversion device. The present disclosure is not limited to a specific power conversion device, but hereinafter, as Embodiment 6, a case where the present disclosure is applied to a three-phase inverter will be described.

[0178] Figure 20 A block diagram showing the configuration of a power conversion system to which the power conversion device of this embodiment is applied.

[0179] Figure 20 The power conversion system shown includes a power source 700, a power conversion device 800, and a load 900. The power source 700 is a DC power source that supplies DC power to the power conversion device 800. The power source 700 can include various power sources. For example, it can include a DC system, a solar cell, a storage battery, or a rectifier circuit and an AC / DC converter connected to an AC system. In addition, the power source 700 can also include a DC / DC converter that converts the DC power output from the DC system into predetermined power.

[0180] The power conversion device 800 is a three-phase inverter connected between the power source 700 and the load 900, and converts the DC power supplied from the power source 700 into AC power and supplies the AC power to the load 900. The power conversion device 800, as Figure 20 shown, includes: a main conversion circuit 801 that converts the input DC power into AC power and outputs it; a drive circuit 802 that outputs drive signals for driving the respective switching elements of the main conversion circuit 801; and a control circuit 803 that outputs control signals for controlling the drive circuit 802 to the drive circuit 802.

[0181] The load 900 is a three-phase motor driven by the AC power supplied from the power conversion device 800. In addition, the load 900 is not limited to a specific use and is a motor mounted on various electrical devices, and is used, for example, as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioning device.

[0182] Hereinafter, the power conversion device 800 will be described in detail. The main conversion circuit 801 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, the DC power supplied from the power source 700 is converted into AC power and supplied to the load 900. There are various examples of the specific circuit structure of the main conversion circuit 801, but the main conversion circuit 801 of the present embodiment is a two-level three-phase full-bridge circuit, which can include six switching elements and six freewheeling diodes anti-parallel to the respective switching elements. In at least any one of the switching elements and the freewheeling diodes of the main conversion circuit 801, the semiconductor device according to any one of the above-described Embodiments 1 to 5 is applied. Among them, the MOSFET structure disposed in the main region 50 can be used as the switching element, and the SBD disposed in the main region 50 can be used as the freewheeling diode. Regarding the six switching elements, every two switching elements are connected in series to form upper and lower branches, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the output terminals of each upper and lower branch, that is, the three output terminals of the main conversion circuit 801 are connected to the load 900.

[0183] In addition, the semiconductor device according to Embodiments 1 to 5 has an integrated structure in which the switching element and the freewheeling diode are built in one chip. Therefore, by using the MOSFET structure disposed in the main region 50 as the switching element of the main conversion circuit 801 and using the SBD disposed in the main region 50 as the freewheeling diode, the mounting area can be reduced as compared with the case of using two or more different chips in which the switching element and the freewheeling diode are formed individually.

[0184] The drive circuit 802 generates drive signals for driving the switching elements of the main conversion circuit 801 and supplies them to the gate electrodes of the switching elements of the main conversion circuit 801. Specifically, in accordance with the control signals from the control circuit 803 described later, drive signals that turn the switching elements on and drive signals that turn the switching elements off are output to the gate electrodes of the respective switching elements. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal becomes a voltage signal (off signal) lower than the threshold voltage of the switching element.

[0185] The control circuit 803 controls the switching elements of the main conversion circuit 801 in such a way as to supply the desired power to the load 900. Specifically, according to the power to be supplied to the load 900, the time (on-time) during which each switching element of the main conversion circuit 801 should be in the on state is calculated. For example, the main conversion circuit 801 can be controlled by PWM control that modulates the on-time of the switching elements according to the voltage to be output. Further, at each time point, a control instruction (control signal) is output to the drive circuit 802 in such a way that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state. The drive circuit 802 outputs an on signal or an off signal as a drive signal to the gate electrode of each switching element in accordance with this control signal.

[0186] In the power conversion device according to the present embodiment, as the switching elements of the main conversion circuit 801, the semiconductor devices according to any one of Embodiments 1 to 5 are applied. Therefore, by using a highly reliable semiconductor device that reduces the static capacitance and suppresses the bipolar degradation, the reliability of the power conversion device can be improved.

[0187] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described. However, the present disclosure is not limited thereto, and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is assumed, but it may also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the present disclosure can also be applied to a single-phase inverter. Further, when supplying power to a DC load or the like, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0188] In addition, the power conversion device to which the present disclosure is applied is not limited to the case where the load is a motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can further be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0189] <Finally>

[0190] In Embodiments 1 to 6 according to the present disclosure described above, the case where the semiconductor material is silicon carbide has been described. However, other semiconductor materials can also be used. That is, the semiconductor layer including the semiconductor substrate 1, the drift layer 2, each well region, and each source region can be formed of other semiconductor materials. As other semiconductor materials, for example, so-called wide-bandgap semiconductors having a wider bandgap than silicon can be cited. As wide-bandgap semiconductors other than silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, gallium oxide, diamond, etc. can be cited. When these wide-bandgap semiconductors are used, the same effects can be obtained.

[0191] In the above-described embodiment, an example in which an SBD is provided in the main region 50 and the sensing region 60 has been described, but it is not limited thereto. Instead of providing the SBD, an n-type channel diode may be formed on the p-type well region in such a manner as to connect the source region and the drift layer. The channel diode is designed such that it operates as a unipolar diode at a gate voltage below the threshold voltage and the rising voltage is lower than the operating voltage of a pn diode including the p-type well region and the n-type drift layer. The channel diode functions as a unipolar diode that allows only the reverse current to flow and does not allow the forward current to flow. Thus, even when reverse conduction is applied to the channel diode formed on the well region of the MOSFET during the reverse operation, the same effect as in the case where the SBD is provided can be obtained.

[0192] Furthermore, in each of the above-described embodiments illustrated in this specification, the materials, materials, dimensions, shapes, relative arrangement relationships, or implementation conditions of the respective components may be described, but they are illustrative in all respects and are not limited to the descriptions of the respective embodiments. Therefore, countless variations that are not illustrated are envisioned within the scope of each embodiment. For example, it includes cases where any component is deformed, added, or omitted, and further cases where at least one component in at least one embodiment is extracted and combined with the components of other embodiments.

[0193] In addition, as long as there is no contradiction, a component described as having "one" in each of the above-described embodiments may also have "more than one". Furthermore, each component is a conceptual unit and includes cases where one component includes multiple structures and cases where one component corresponds to a part of a certain structure.

[0194] In addition, none of the descriptions in this specification should be considered as prior art.

[0195] Furthermore, the respective embodiments can be freely combined or appropriately deformed and omitted.

Claims

1. A semiconductor device comprising: A semiconductor layer having a first main surface and a second main surface facing the first main surface; A source electrode provided on the first main surface side; And A drain electrode provided on the second main surface side, The semiconductor device controls the current flowing between the source electrode and the drain electrode by a voltage applied to the gate electrode, Wherein the semiconductor device comprises: A sense source electrode independently provided from the source electrode and provided on the first main surface side of the semiconductor layer; A drift layer of a first conductivity type constituting a main part of the semiconductor layer; A sense well region of a second conductivity type selectively provided on the surface layer of the drift layer and electrically connected to the sense source electrode; A sense source region of a first conductivity type selectively provided on the surface layer of the sense well region and electrically connected to the sense source electrode; A dummy sense well region of a second conductivity type selectively provided on the surface layer of the drift layer independently of the sense well region and electrically connected to the sense source electrode, without forming a channel; A gate insulating film provided between the dummy sense well region and the gate electrode; and A diode provided between the sense source electrode and the drift layer, having a turn-on voltage lower than the operating voltage of a pn diode including the sense well region or the dummy sense well region and the drift layer, and capable of conducting the current flowing from the sense source electrode to the drain electrode, In a dummy sense region where the dummy sense well region and the diode are arranged, the diode is arranged to be mixed with a facing region, which is a region facing the gate electrode with the gate insulating film interposed between the dummy sense well region, in the facing region.

2. The semiconductor device according to claim 1, wherein The diode is arranged alternately and repeatedly with the facing region in a plan view.

3. The semiconductor device according to claim 1, wherein, Comprising: A sense region including an active sense region where the sense well region is arranged and the dummy sense region; and A main region as a region different from the sense region, The main region has: A well region of a second conductivity type selectively provided on the surface layer of the drift layer and electrically connected to the source electrode; A source region of a first conductivity type selectively provided on the surface layer of the well region and electrically connected to the source electrode; And A second diode provided between the source electrode and the drift layer, having a turn-on voltage lower than the operating voltage of a pn diode including the well region and the drift layer, and capable of conducting the current flowing from the source electrode to the drain electrode, The diode is arranged in the dummy sense region so as to be 2 times or less the arrangement interval of the second diode in the main region.

4. The semiconductor device according to any one of claims 1 to 3, wherein The diode is arranged in the dummy sense region at an interval of 1 μm or more and 100 μm or less.

5. The semiconductor device according to any one of claims 1 to 3, wherein, Comprising: A sense region including an active sense region where the sense well region is arranged and the dummy sense region; And A boundary region, which is a region different from the sense region and is provided around the sense region, The diode and the counter region are alternately and repeatedly arranged in a direction from the boundary region toward the active sensing region.

6. The semiconductor device according to any one of claims 1 to 3, wherein the diodes are periodically arranged within the dummy sensing region.

7. The semiconductor device according to any one of claims 1 to 3, wherein within the dummy sensing region, the distance between the pn junction farthest from the diode and the diode is less than or equal to half of the arrangement interval of the diodes.

8. The semiconductor device according to any one of claims 1 to 3, wherein within the counter region, the drift layer is not provided at a position facing the gate electrode with the gate insulating film interposed therebetween.

9. The semiconductor device according to claim 8, wherein a dummy sensing source region of a first conductivity type is further provided, which is selectively provided on the surface layer of the dummy sensing well region, is electrically connected to the sensing source electrode, and faces the gate electrode with the gate insulating film interposed therebetween.

10. The semiconductor device according to claim 9, wherein within the counter region, the dummy sensing source region is provided at a position facing the gate electrode with the gate insulating film interposed therebetween, and the dummy sensing well region does not contact the gate insulating film.

11. The semiconductor device according to any one of claims 1 to 3, wherein the sensing well region is provided as a single block in a plan view.

12. The semiconductor device according to any one of claims 1 to 3, wherein the dummy sensing well region is not ohmically connected to the source electrode.

13. The semiconductor device according to any one of claims 1 to 3, wherein a boundary well region of a second conductivity type is further provided, which is provided on the surface layer of the drift layer between the source electrode and the sensing source electrode, the boundary well region is not ohmically connected to the source electrode and the sensing source electrode, and is not connected to any of the sensing well region and the dummy sensing well region.

14. The semiconductor device according to claim 13, wherein the boundary well region is Schottky-connected to the source electrode and the sensing source electrode.

15. The semiconductor device according to claim 13, wherein an insulating film is further provided, which is formed between the boundary well region and the source electrode and between the boundary well region and the sensing source electrode.

16. The semiconductor device according to any one of claims 1 to 3, wherein the sensing source electrode is provided in a first groove that penetrates the dummy sensing well region and reaches the drift layer, the diode is formed at a portion where the sensing source electrode and the drift layer face each other on the bottom surface or side surface of the first groove.

17. The semiconductor device according to any one of claims 1 to 3, wherein the gate insulating film and the gate electrode are provided in a second groove that penetrates from the surface of the semiconductor layer into the dummy sensing well region, The gate electrode faces the dummy sense well region across the gate insulating film on at least one of the bottom surface and the side surface of the second groove.

18. The semiconductor device according to claim 17, wherein the depth of the second groove is equal to or less than the depth of the dummy sense well region in the thickness direction of the drift layer.

19. The semiconductor device according to claim 17, wherein a dummy sense source region of a first conductivity type is further provided, the dummy sense source region is provided on the surface layer of the dummy sense well region and is electrically connected to the sense source electrode, the gate insulating film and the gate electrode are provided in the second groove that penetrates the dummy sense source region and reaches the dummy sense well region, the gate insulating film does not contact the drift layer on the bottom surface and the side surface of the second groove, the gate electrode faces the dummy sense source region across the gate insulating film.

20. The semiconductor device according to any one of claims 1 to 3, wherein the diode includes a Schottky junction portion formed by Schottky junction of the sense source electrode and the drift layer.

21. The semiconductor device according to any one of claims 1 to 3, wherein the diode includes a channel diode of a first conductivity type formed on the dummy sense well region.

22. The semiconductor device according to any one of claims 1 to 3, wherein a wide bandgap semiconductor is used as the semiconductor material in the semiconductor layer.

23. A semiconductor device includes: a semiconductor layer having a drift layer of a first conductivity type; a main region having a MOSFET structure in which a source electrode and a gate electrode are provided on one main surface side of the semiconductor layer and a drain electrode is provided on the other main surface side; a sense region, which is a region different from the main region, having a MOSFET structure in which a sense source electrode independently formed from the source electrode is provided on the one main surface side of the semiconductor layer; a dummy sense well region of a second conductivity type, selectively provided on the surface layer of the drift layer in the sense region and not forming a channel; a gate insulating film provided between the dummy sense well region and the gate electrode; and a diode formed between the sense source electrode and the drift layer, having a rising voltage lower than the operating voltage of a pn diode including the dummy sense well region and the drift layer, and capable of conducting a current flowing from the sense source electrode to the drain electrode, in the sense region, the diode is provided such that a region where it faces the dummy sense well region across the gate insulating film and the gate electrode, i.e., the facing region, is mixedly present.

24. A power conversion device includes: a main conversion circuit having the semiconductor device according to any one of claims 1 to 23, the main conversion circuit converting the input power and outputting it; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

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