Silicon Carbide Semiconductor Device and Power Conversion Device

Abstract

By suppressing the generation of a large current in the body diode of a field-effect transistor, variations in device characteristics are suppressed. The silicon carbide semiconductor device includes: a silicon carbide semiconductor substrate; a semiconductor layer formed on the upper surface of the silicon carbide semiconductor substrate; and a back electrode formed on the lower surface of the silicon carbide semiconductor substrate. A region having a first resistivity value is defined as a first resistance region, and a region having a second resistivity value greater than the first value is defined as a second resistance region. The second resistance region is a region that straddles the boundary between the active region and the terminal region, i.e., the region boundary, in a plan view.

Description

Technical Field

[0001] The technology disclosed in the specification of this application relates to a silicon carbide semiconductor device and a power conversion device. Background Art

[0002] Wide-bandgap semiconductor materials such as silicon carbide (SiC) have a higher breakdown voltage tolerance than silicon (Si) materials. Therefore, by using a wide-bandgap semiconductor material as the substrate material, the impurity concentration of the substrate can be increased and the resistance of the substrate can be reduced compared to the case of using a silicon material. By reducing the resistance of such a substrate, the loss during the switching operation of the power element can be reduced. In addition, wide-bandgap semiconductor materials have higher thermal conductivity and better mechanical strength than silicon materials, so they are expected to be materials that can realize small, low-loss, and high-efficiency power devices.

[0003] It is known that a metal-oxide-semiconductor field-effect transistor (MOSFET) using silicon carbide (hereinafter sometimes referred to as "SiC-MOSFET") has a parasitic diode called a body diode between the source and drain. When a forward current flows here, the resistance value of the element changes (for example, refer to Non-Patent Document 1).

[0004] The reason for this is that due to the recombination energy when minority carriers injected via the body diode recombine with majority carriers, stacking faults as surface defects expand starting from basal plane dislocations existing in the silicon carbide substrate.

[0005] In addition, for example, Non-Patent Document 2 describes the following method: In a PN diode of silicon carbide, a buffer layer is formed on the silicon carbide substrate to promote the recombination of holes and electrons in the buffer layer and prevent stacking faults from expanding starting from basal plane dislocations existing in the silicon carbide substrate.

[0006] Prior Art Documents

[0007] Non-Patent Documents

[0008] Non-Patent Document 1: IEEE ELECTRON DEVICE LETTERS, VOL.28, No.7, "A New Degradation Mechanism in High-Voltage SiC Power MOSFETs", JULY 2007

[0009] Non-Patent Document 2: Journal of Applied Physics, "Short minority carrier lifetimes in highly nitrogen-doped 4H-SiC epilayers for suppression of the stacking fault formation in PiN diodes", Vol. 120, pp. 115101, 2016 Summary of the Invention

[0010] However, in the structure with an introduced buffer layer as shown in Non-Patent Document 2, if there is a portion where a large current is generated, it is necessary to significantly thicken the buffer layer accordingly. Therefore, it becomes disadvantageous from the perspective of productivity. Additionally, in Non-Patent Document 2, the case of a large current being generated in the body diode of a field-effect transistor is not disclosed.

[0011] The technology disclosed in the specification of the present application is completed in view of the problems described above, and is a technology for suppressing variations in element characteristics when a large current is generated in the body diode of a field-effect transistor.

[0012] The first aspect of the technology disclosed in the specification of the present application relates to a silicon carbide semiconductor device, comprising: a silicon carbide semiconductor substrate of a first conductivity type; a semiconductor layer of the first conductivity type, formed on the upper surface of the silicon carbide semiconductor substrate; and a back electrode, formed on the lower surface of the silicon carbide semiconductor substrate. The region where a field-effect transistor is formed on the surface layer and the upper surface of the semiconductor layer is set as an active region, the region surrounding the active region in a top view is set as a terminal region, the region where the resistivity between the silicon carbide semiconductor substrate and the back electrode is a first value is set as a first resistance region, and the region where the resistivity between the silicon carbide semiconductor substrate and the back electrode is a second value greater than the first value is set as a second resistance region. The second resistance region is a region that straddles the boundary between the active region and the terminal region, i.e., the region boundary, in a top view.

[0013] The second aspect of the technology disclosed in the specification of the present application relates to a silicon carbide semiconductor device, comprising: a silicon carbide semiconductor substrate; a semiconductor layer formed on the upper surface of the silicon carbide semiconductor substrate; and a back electrode formed on a part of the lower surface of the silicon carbide semiconductor substrate. The region where a field effect transistor is formed on the surface layer and the upper surface of the semiconductor layer is set as an active region, the region surrounding the active region in a top view is set as a terminal region, the region where the back electrode is formed in a top view is set as a first region, and the region where the back electrode is not formed in a top view is set as a second region. The second region is a region that straddles the boundary between the active region and the terminal region, i.e., the region boundary, in a top view.

[0014] The third aspect of the technology disclosed in the specification of the present application relates to a power conversion device, comprising: a conversion circuit having the above silicon carbide semiconductor device, and the conversion circuit converts the input power and outputs it; a drive circuit that outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

[0015] The first aspect of the technology disclosed in the specification of the present application comprises: a silicon carbide semiconductor substrate of a first conductivity type; a semiconductor layer of the first conductivity type formed on the upper surface of the silicon carbide semiconductor substrate; and a back electrode formed on the lower surface of the silicon carbide semiconductor substrate. The region where a field effect transistor is formed on the surface layer and the upper surface of the semiconductor layer is set as an active region, the region surrounding the active region in a top view is set as a terminal region, the region where the resistivity between the silicon carbide semiconductor substrate and the back electrode is a first value is set as a first resistance region, and the region where the resistivity between the silicon carbide semiconductor substrate and the back electrode is a second value greater than the first value is set as a second resistance region. The second resistance region is a region that straddles the boundary between the active region and the terminal region, i.e., the region boundary, in a top view. According to such a structure, it is possible to suppress the local generation of a large current near the boundary between the active region and the terminal region, so that the variation of the element characteristics can be suppressed.

[0016] The second aspect of the technology disclosed in the specification of the present application includes: a silicon carbide semiconductor substrate; a semiconductor layer formed on the upper surface of the silicon carbide semiconductor substrate; and a back electrode formed on a part of the lower surface of the silicon carbide semiconductor substrate. The region where a field effect transistor is formed on the surface layer and the upper surface of the semiconductor layer is set as an active region, the region surrounding the active region in a top view is set as a terminal region, the region where the back electrode is formed in a top view is set as a first region, and the region where the back electrode is not formed in a top view is set as a second region. The second region is a region that straddles the boundary between the active region and the terminal region, that is, the region boundary, in a top view. According to such a structure, it is possible to suppress the local generation of a large current near the boundary between the active region and the terminal region, so that the variation of element characteristics can be suppressed.

[0017] The third aspect of the technology disclosed in the specification of the present application relates to a power conversion device, which includes: a conversion circuit having the above-mentioned silicon carbide semiconductor device, and the conversion circuit converts the input power and outputs it; a drive circuit that outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit. According to such a structure, it is possible to suppress the local generation of a large current near the boundary between the active region and the terminal region of the silicon carbide semiconductor device provided in the power conversion device, so that the variation of element characteristics can be suppressed.

[0018] In addition, the objects, features, aspects, and advantages related to the technology disclosed in the specification of the present application will become clearer through the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a top view schematically showing an example of the structure of a SiC-MOSFET according to an embodiment.

[0020] Figure 2 It is a cross-sectional view schematically showing an example of the structure of the peripheral part of a SiC-MOSFET according to an embodiment.

[0021] Figure 3 It is a top view showing an example of the region where an ohmic contact region is formed according to an embodiment.

[0022] Figure 4 It is a top view schematically showing a modified example of the structure of a SiC-MOSFET according to an embodiment.

[0023] Figure 5 It is a top view schematically showing a modified example of the structure of a SiC-MOSFET according to an embodiment.

[0024] Figure 6Is a top view showing an example of a region where an ohmic contact region is formed in the case of a pad for gate wiring, that is, a gate wiring electrode, which is exemplified. Figure 4 Is a top view showing an example of a region where an ohmic contact region is formed in the case of a pad for gate wiring, that is, a gate wiring electrode, which is exemplified.

[0025] Figure 7 Is a top view showing an example of a region where an ohmic contact region is formed in the case of a pad for gate wiring, that is, a gate wiring electrode, which is exemplified. Figure 5 Is a top view showing an example of a region where an ohmic contact region is formed in the case of a pad for gate wiring, that is, a gate wiring electrode, which is exemplified.

[0026] Figure 8 Is a cross-sectional view schematically showing a modified example of the structure of the peripheral portion of a SiC-MOSFET according to an embodiment.

[0027] Figure 9 Is a cross-sectional view schematically showing an example of the structure of the peripheral portion of a SiC-MOSFET according to an embodiment.

[0028] Figure 10 Is a cross-sectional view schematically showing a modified example of the structure of the peripheral portion of a SiC-MOSFET according to an embodiment.

[0029] Figure 11 Is a cross-sectional view schematically showing an example of the structure of the peripheral portion of a SiC-MOSFET according to an embodiment.

[0030] Figure 12 Is a cross-sectional view schematically showing a modified example of the structure of the peripheral portion of a SiC-MOSFET according to an embodiment.

[0031] Figure 13 Is a diagram schematically showing an example of the structure of a power conversion system including a power conversion device according to an embodiment.

[0032] Figure 14 Is a cross-sectional view schematically showing an example of the structure of a SiC-MOSFET known to the inventor.

[0033] (Symbol description)

[0034] 2, 2A, 2B: Gate wiring electrodes; 3: Source electrode; 4: Surface protective film; 5: Active region; 6: Terminal region; 7: Low-resistance region; 8: High-resistance region; 10: p-well region; 11: Source region; 12: Contact region; 13: Gate insulating film; 14: Gate electrode; 15: Interlayer insulating film; 16: Terminal well region; 17: High-concentration terminal well region; 18: Extended terminal well region; 19: Field insulating film; 20, 320, 520, 620, 720: Back electrodes; 20a, 20b, 220, 420, 721, 722: Back electrode layers; 21, 21A, 21B, 21C, 221: Ohmic contact regions; 22: Non-ohmic contact region; 30: Silicon carbide epitaxial substrate; 31: Silicon carbide single crystal substrate; 32: Buffer layer; 33: Drift layer; 34: Epitaxial growth layer; 40, 340: Ion implantation regions; 40a, 40b, 40c, 40d: Ion implantation layers; 100, 101, 110, 120, 200, 201, 300, 301, 400: SiC-MOSFETs; 2100: Power supply; 2200: Power conversion device; 2201: Conversion circuit; 2202: Drive circuit; 2203: Control circuit; 2300: Load. Detailed implementation manners

[0035] Hereinafter, with reference to the accompanying drawings, the implementation manners will be described. In the following implementation manners, for technical explanations, detailed features and the like are also shown, but they are examples, and not all of these are necessarily features required for the implementation manners to be practicable.

[0036] In addition, the accompanying drawings are schematic diagrams. For ease of explanation, structures are appropriately omitted or simplified in the accompanying drawings. Also, the sizes and the mutual relationships of positions of the structures and the like shown separately in different accompanying drawings are not necessarily correctly recorded and may be appropriately changed. In addition, in drawings such as top views that are not cross-sectional views, in order to facilitate understanding of the content of the implementation manners, hatching may sometimes be added.

[0037] In addition, in the following descriptions, it is assumed that the same reference numerals are attached to the same components and illustrated, and their names and functions are also the same. Therefore, for the sake of avoiding repetition, detailed descriptions thereof may sometimes be omitted.

[0038] In addition, in the following descriptions, when it is described that a certain component or the like is "provided with", "includes", or "has", unless otherwise specified, it is not an exclusive expression excluding the existence of other components.

[0039] In addition, in the descriptions given below, even when ordinal numbers such as "first" or "second" are used, these terms are examples appropriately used to facilitate understanding of the content of the embodiments, and are not limited to the order or the like that can be generated by these ordinal numbers.

[0040] In addition, in the descriptions given below, expressions indicating an equal state, such as "identical", "equal", "uniform", or "homogeneous", etc., include cases indicating a strictly equal state and cases where differences occur within the range of tolerances or where the same degree of function can be obtained, unless otherwise specified.

[0041] In addition, in the descriptions given below, even when terms indicating a specific position or direction such as "upper", "lower", "left", "right", "side", "bottom", "front", or "back" are used, these terms are examples appropriately used to facilitate understanding of the content of the embodiments and are not related to the actual position or direction during implementation.

[0042] In addition, in the descriptions given below, when it is described as "the upper surface of..." or "the lower surface of...", etc., it includes not only the upper surface itself or the lower surface itself of the constituent element that is the object, but also a state in which other constituent elements are formed on the upper surface or the lower surface of the constituent element that is the object. That is, for example, when it is described as "B provided on the upper surface of A", it does not prevent another constituent element "C" from being interposed between A and B. Similarly, for example, when it is described as "B covering A", it does not prevent another constituent element "C" from being interposed between A and B.

[0043] <First Embodiment>

[0044] Hereinafter, the silicon carbide semiconductor device of the present embodiment will be described.

[0045] Hereinafter, the "active region" of the semiconductor device is defined as the region through which the main current flows when the semiconductor device is in the conducting state, and the "terminal region" of the semiconductor device is defined as the region around the active region. In addition, the "outer side" of the semiconductor device refers to the direction from the central part of the semiconductor device toward the peripheral part, and the "inner side" of the semiconductor device refers to the direction opposite to the "outer side". In addition, regarding the conduction type of impurities, the "first conduction type" is assumed to be n-type and the "second conduction type" is assumed to be p-type for description, but conversely, the "first conduction type" may be set to p-type and the "second conduction type" may be set to n-type.

[0046] Here, terms such as "MOS" were previously used for a stacked structure of metal / oxide / semiconductor.

[0047] However, in a field effect transistor having a MOS structure (hereinafter sometimes simply referred to as "MOS transistor"), the materials of the gate insulating film and the gate electrode are improved from the viewpoints of recent integration and improvement of manufacturing processes, etc.

[0048] For example, in a MOS transistor, mainly from the viewpoint of self-matching formation of the source and drain, polysilicon is used as the material of the gate electrode instead of metal.

[0049] In addition, from the viewpoint of improving electrical characteristics, a material with a high dielectric constant is used as the material of the gate insulating film, but this material is not necessarily limited to oxides.

[0050] Therefore, the term "MOS" is not necessarily a term used only for a metal / oxide / semiconductor stacked structure, and this specification is not premised on such a limitation.

[0051] That is, in view of common technical knowledge, here "MOS" means not only an abbreviation derived from its etymology, but also has a meaning that widely includes a stacked structure of a conductor / insulator / semiconductor.

[0052] In addition, in the following description, the expression "A and B are electrically connected" means that current can flow bidirectionally between the components constituting A and the components constituting B.

[0053] <Regarding the structure of a silicon carbide semiconductor device>

[0054] The semiconductor device of this embodiment is a SiC-MOSFET that is a silicon carbide semiconductor device based on a substrate made of silicon carbide (SiC). Figure 1 It is a top view schematically showing an example of the structure of the SiC-MOSFET of this embodiment.

[0055] As Figure 1 Illustrated, the SiC-MOSFET is formed on the upper surface of the silicon carbide epitaxial substrate 30 in a top view, and at its central part, there are provided a gate wiring electrode 2 as a pad for applying a gate voltage from an external control circuit (not shown here) and a source electrode 3 as a pad.

[0056] In addition, in Figure 1 The illustrated end part of the silicon carbide epitaxial substrate 30 in a top view, a surface protective film 4 is provided. In Figure 1 Among them, the position of the end part inside the surface protective film 4, that is, the contour line of the surface protective film 4 is shown by a dotted line.

[0057] Figure 2 It is a cross-sectional view schematically showing an example of the structure of the peripheral part of the SiC-MOSFET100 of this embodiment. Figure 2 With Figure 1corresponds to the a-a' cross-section in

[0058] As Figure 2 an example, the SiC-MOSFET 100 is formed using a silicon carbide epitaxial substrate 30. The silicon carbide epitaxial substrate 30 includes a silicon carbide single crystal substrate 31 and an epitaxial growth layer 34 formed on the upper surface of the silicon carbide single crystal substrate 31.

[0059] The silicon carbide single crystal substrate 31 is a semiconductor substrate made of n-type (first conductivity type) silicon carbide. In addition, the epitaxial growth layer 34 is a semiconductor layer made of silicon carbide formed by epitaxial growth on the upper surface of the silicon carbide single crystal substrate 31. In the present embodiment, a silicon carbide epitaxial substrate 30 having a 4H polytype is used. The epitaxial growth layer 34 includes a buffer layer 32 and a drift layer 33 formed on the upper surface of the buffer layer 32 and having an impurity concentration lower than that of the buffer layer 32.

[0060] The buffer layer 32 is formed on the surface (i.e., the upper surface) on the first direction side in the thickness direction of the silicon carbide single crystal substrate 31. The buffer layer 32 recombines holes injected from the upper surface side of the device, reducing the hole density reaching the silicon carbide single crystal substrate 31. In addition, the buffer layer 32 may have a function of converting basal plane dislocations existing in the silicon carbide single crystal substrate 31 into edge dislocations. In addition, the buffer layer 32 may be formed by overlapping multiple layers. The higher the impurity concentration of the buffer layer 32, the higher the ability to suppress the expansion of stacking defects in the case of increasing the conduction current of the body diode. Therefore, the impurity concentration and thickness of the buffer layer 32 are set according to the current density of the current flowing through the body diode of the semiconductor element. For example, the impurity concentration of the buffer layer 32 is 1×10 18 cm -3 or more and 2×10 19 cm -3 or less.

[0061] The drift layer 33 is formed on the surface (i.e., the upper surface) on the first direction side in the thickness direction of the buffer layer 32. The impurity concentration of the drift layer 33 is lower than the impurity concentration of the silicon carbide single crystal substrate 31 and the impurity concentration of the buffer layer 32. The impurity concentration and thickness of the drift layer 33 are determined according to the breakdown voltage of the semiconductor element. For example, the impurity concentration of the drift layer 33 is 1×10 14 cm -3 or more and 1×10 17 cm -3 or less. In addition, for example, the thickness of the drift layer 33 is 5 μm or more and several hundred μm or less. In addition, as Figure 2 an example, in the SiC-MOSFET 100, an active region 5 where an element structure such as a field effect transistor is formed and a terminal region 6 surrounding the active region 5 are allocated.

[0062] On the surface layer on the upper surface side of the epitaxial growth layer 34 in the active region 5, that is, on the surface layer on the upper surface side of the drift layer 33, a p-well region 10 serving as a p-type (second conductivity type) well region is selectively formed. Further, on the surface layer of the p-well region 10, an n-type (first conductivity type) source region 11 and a p-type contact region 12 having an impurity concentration higher than that of the p-well region 10 are selectively formed, respectively. Further, when viewed from above, the p-type contact region 12 is formed so as to be surrounded by the p-well region 10.

[0063] On the upper surface of the silicon carbide epitaxial substrate 30 in the active region 5, a gate insulating film 13 is formed so as to cover the p-well region 10 between the n-type source region 11 and the drift layer 33. Further, on the upper surface of the gate insulating film 13, a gate electrode 14 is formed.

[0064] The surface layer portion of the p-well region 10 covered with the gate insulating film 13 and the gate electrode 14, that is, the portion of the p-well region 10 sandwiched between the n-type source region 11 and the drift layer 33, is a channel region where an inversion channel is formed when the SiC-MOSFET 100 is in an on state.

[0065] In the active region 5, the gate electrode 14 is covered with an interlayer insulating film 15. Further, on the upper surface of the interlayer insulating film 15, a source electrode 3 is formed. Therefore, the gate insulating film 13 and the gate electrode 14 are electrically insulated by the interlayer insulating film 15.

[0066] The source electrode 3 is connected to the n-type source region 11 and the p-type contact region 12 via contact holes formed in the interlayer insulating film 15. The source electrode 3 and the p-type contact region 12 form an ohmic contact.

[0067] The terminal region 6 surrounds the active region 5 when viewed from above. On the surface layer on the upper surface side of the epitaxial growth layer 34 in the terminal region 6, that is, on the surface layer of the drift layer 33, a p-type terminal well region 16 is selectively formed so as to surround the active region 5.

[0068] On the surface layer of the p-type terminal well region 16, a p-type high-concentration terminal well region 17 having an impurity concentration higher than that of the p-type terminal well region 16 is formed. Further, a p-type extended terminal well region 18 for maintaining the breakdown voltage of the SiC-MOSFET 100 is formed in the outer peripheral portion of the p-type terminal well region 16.

[0069] The p-type extended terminal well region 18 is a junction termination extension (JTE) region of the second conductivity type. As the structure of the p-type extended terminal well region 18, for example, it may also be a field limiting ring (i.e., FLR) structure formed annularly along the outer periphery of the SiC-MOSFET 100. When looking down at the SiC-MOSFET 100, the innermost part of the p-type extended terminal well region 18 is connected to the outermost peripheral part of at least one of the p-type terminal well region 16 and the high-concentration terminal well region 17.

[0070] As Figure 2 illustrated, a part of the gate insulating film 13, a part of the gate electrode 14, a part of the interlayer insulating film 15, and a part of the source electrode 3 straddle the boundary between the active region 5 and the terminal region 6 and extend from the active region 5 to the terminal region 6.

[0071] The source electrode 3 led out to the terminal region 6 is connected in an ohmic contact manner to the high-concentration terminal well region 17 formed in the p-type terminal well region 16 via a contact hole formed in the interlayer insulating film 15. In addition, the gate electrode 14 led out to the terminal region 6 is connected to one or both of the p-type terminal well region 16 and the p-type high-concentration terminal well region 17 via the gate insulating film 13.

[0072] Furthermore, on the upper surface of the silicon carbide epitaxial substrate 30 in the terminal region 6, a field insulating film 19, a gate wiring electrode 2, and a surface protective film 4 are provided.

[0073] The field insulating film 19 covers a part of the p-type terminal well region 16 and the whole of the p-type extended terminal well region 18, extends beyond the outer peripheral end of the p-type terminal well region 16 to the outside of the p-type terminal well region 16. In addition, the field insulating film 19 is not provided in the active region 5. In other words, the field insulating film 19 has an opening including the active region 5.

[0074] The gate wiring electrode 2 is formed on the upper surface of the interlayer insulating film 15 covering the gate electrode 14 led out to the terminal region 6 and is connected to the gate electrode 14 via a contact hole formed in the interlayer insulating film 15.

[0075] The surface protective film 4 is formed to cover the position on the terminal region 6 side in the active region 5 of the source electrode 3, the position of the source electrode 3 in the terminal region 6, the gate wiring electrode 2, and the field insulating film 19. In addition, the surface protective film 4 covers a part of the silicon carbide epitaxial substrate 30 in the terminal region 6.

[0076] Here, the position of the boundary A between the active region 5 and the terminal region 6 in the present embodiment is a position corresponding to the innermost end of the p-type terminal well region 16 and the innermost end of the p-type high-concentration terminal well region 17, which is the one closer to the central portion of the active region 5 (the one located more inward).

[0077] On the other hand, on the lower surface (back surface) of the silicon carbide single crystal substrate 31, a back electrode 20 is provided. The back electrode 20 includes a back electrode layer 20a, a back electrode layer 20b, and an ohmic contact region 21. The back electrode layer 20a is partially formed on the lower surface of the silicon carbide single crystal substrate 31. The ohmic contact region 21 is formed in a portion of the lower surface of the silicon carbide single crystal substrate 31 where the back electrode layer 20a is not formed. Further, the back electrode layer 20b is formed on the lower surface of the back electrode layer 20a and the lower surface of the ohmic contact region 21.

[0078] As Figure 2 illustrated, the ohmic contact region 21 is formed sandwiched between the lower surface of the silicon carbide single crystal substrate 31 and the upper surface of the back electrode layer 20b. In the present embodiment, the ohmic contact region 21 is a silicide region of the metal for the back electrode layer 20a.

[0079] By forming the ohmic contact region 21, the back electrode 20 and the silicon carbide single crystal substrate 31 are in ohmic contact in the region where the ohmic contact region 21 is formed, and a current flows between the two with a low resistance.

[0080] Conversely, in the region where the ohmic contact region 21 is not formed (i.e., the region where the back electrode layer 20a is formed), the contact resistance between the back electrode 20 and the silicon carbide single crystal substrate 31 is high, so the resistivity becomes high. Therefore, it is difficult for a current to flow between the two.

[0081] Therefore, in the present embodiment, the region where the ohmic contact region 21 is formed in a plan view is set as the low-resistance region 7 where the resistivity (contact resistivity) between the silicon carbide single crystal substrate 31 and the back electrode 20 is a low value, and the region where the ohmic contact region 21 is not formed in a plan view is set as the high-resistance region 8 where the resistivity (contact resistivity) between the silicon carbide single crystal substrate 31 and the back electrode 20 is a high value.

[0082] When a current is applied to the SiC-MOSFET 100, the current density is different between the low-resistance region 7 and the high-resistance region 8 in the back electrode 20. Specifically, almost no current flows in the high-resistance region 8, and a current with a high current density flows in the low-resistance region 7.

[0083] In the present embodiment, the high-resistance region 8 is provided in the active region 5 and the terminal region 6 so as to straddle the boundary A between the active region 5 and the terminal region 6.

[0084] To explain the above structure, first, an example of the structure of a silicon carbide semiconductor device known to the inventors is shown. Figure 14 It is a cross-sectional view schematically showing an example of the structure of the SiC-MOSFET 400 known to the inventors.

[0085] As Figure 14 illustrated, the SiC-MOSFET 400 is formed using a silicon carbide epitaxial substrate 30. The silicon carbide epitaxial substrate 30 includes a silicon carbide single crystal substrate 31 and an epitaxial growth layer 34. The epitaxial growth layer 34 includes a buffer layer 32 and a drift layer 33. In addition, as Figure 14 illustrated, in the SiC-MOSFET 400, an active region 5 where a device structure is formed and a terminal region 6 surrounding the active region 5 are provided.

[0086] On the upper surface side surface layer of the epitaxial growth layer 34 in the active region 5, a p-well region 10 is selectively formed. In addition, on the surface layer of the p-well region 10, an n-type source region 11 and a p-type contact region 12 are selectively formed, respectively.

[0087] On the upper surface of the silicon carbide epitaxial substrate 30 in the active region 5, a gate insulating film 13 is formed. In addition, on the upper surface of the gate insulating film 13, a gate electrode 14 is formed.

[0088] In the active region 5, the gate electrode 14 is covered with an interlayer insulating film 15. In addition, on the upper surface of the interlayer insulating film 15, a source electrode 3 is formed.

[0089] On the upper surface side surface layer of the epitaxial growth layer 34 in the terminal region 6, a p-type terminal well region 16 is selectively formed so as to surround the active region 5. On the surface layer of the p-type terminal well region 16, a p-type high-concentration terminal well region 17 is formed. In addition, on the outer peripheral portion of the p-type terminal well region 16, a p-type extended terminal well region 18 is formed.

[0090] Furthermore, on the upper surface of the silicon carbide epitaxial substrate 30 in the terminal region 6, a field insulating film 19, a gate wiring electrode 2, and a surface protective film 4 are provided.

[0091] Here, Figure 14 the position of the boundary A between the active region 5 and the terminal region 6 in is the position corresponding to the innermost end of the p-type terminal well region 16 and the innermost end of the p-type high-concentration terminal well region 17, which is the one closer to the central portion of the active region 5 (the one located more inward).

[0092] On the other hand, an ohmic contact region 221 is formed on the lower surface (back surface) of the silicon carbide epitaxial substrate 30. Further, a back electrode layer 220 is formed on the lower surface of the ohmic contact region 221.

[0093] Through the investigation by the inventor, it is known that when a current is applied to the body diode of the SiC-MOSFET 400 having the structure shown in Figure 14 , when a large current is applied to the center of the active region 5, in the epitaxial growth layer 34 near the boundary A between the terminal region 6 and the active region 5, there is a region where the hole current density increases. Specifically, there is a region where the hole current density becomes more than twice that of the center of the active region 5.

[0094] Furthermore, it is known that this phenomenon becomes more significant as the current density of the current applied to the center of the active region 5 increases, and a relatively large current compared to the center of the active region 5 concentrates near the boundary A between the terminal region 6 and the active region 5. Thus, for the first time, it has been clarified that stacking defects preferentially occur in the region near the boundary A between the terminal region 6 and the active region 5, causing a change in device characteristics (so-called device degradation).

[0095] For example, when a current of 500 A / cm 2 flows through the body diode at the center of the active region 5, in the epitaxial growth layer 34 near the boundary A between the active region 5 and the terminal region 6, a hole current of 1000 A / cm 2 or more flows.

[0096] Near the epitaxial growth layer 34, even if a large current flows in a part in a top view, a buffer layer 32 suitable for its maximum current needs to be designed. Therefore, even when an average current of 500 A / cm 2 flows through the body diode, in order to suppress the degradation of device characteristics, it is necessary to introduce a buffer layer 32 suitable for 1000 A / cm 2 .

[0097] Generally, as the current density of the current flowing through the body diode increases, the buffer layer 32 required to prevent characteristic degradation also needs to be thickened. This is not preferable from the viewpoint of productivity.

[0098] In order to determine the cause of the above current concentration, the inventor evaluated using current simulation analysis. As a result, it was found that due to the geometric relationship between the source electrode 3 and the back electrode layer 220, the current circulation from the terminal region 6 to the end of the active region 5 is one of the causes of the above current concentration.

[0099] In the SiC-MOSFET 400, in the terminal region 6 near the boundary A, the back electrode layer 220 and the source electrode 3 are connected via the p-type terminal well region 16 and the p-type high-concentration terminal well region 17. Such a structure is provided to improve the breakdown tolerance of the SiC-MOSFET 400 and is designed such that the contact resistivity per unit area in this region is lower than the contact resistivity per unit area in the active region 5.

[0100] Therefore, the resistivity of the path via the active region 5 is higher than the resistivity of the path via the p-type terminal well region 16 and the p-type high-concentration terminal well region 17, causing a phenomenon where current also flows from the back electrode layer 220 facing the active region 5 into the terminal region 6.

[0101] As a result, near the boundary A between the active region 5 and the terminal region 6, a large current flows locally. In addition, the inventors have also found that this becomes the main cause of further current concentration.

[0102] To suppress such a phenomenon, it is sufficient to increase the contact resistivity in the terminal region 6. As a result, the breakdown tolerance decreases. It is necessary to simultaneously achieve an increase in the breakdown tolerance and suppression of current concentration to suppress the degradation of device characteristics.

[0103] For example, a terminal structure for increasing the breakdown tolerance is not formed in the PN diode in Japanese Patent Laid-Open No. 9-36388, etc. Further, a p-type impurity layer is formed over the entire surface layer of the drift layer in the active region. Therefore, the resistivity per unit area in the terminal region does not become lower than that in the active region. That is, in the PN diode in Japanese Patent Laid-Open No. 9-36388, etc., current concentration caused by a decrease in the contact resistivity in the terminal region cannot occur.

[0104] From the above, the structure of the terminal region 6 in the present embodiment is a structure unique to MOSFETs, and current concentration during body diode conduction caused by the structure of the terminal region 6 as shown in the present embodiment is also a problem unique to MOSFETs.

[0105] To efficiently manufacture a highly reliable SiC-MOSFET with suppressed device degradation, it is important to avoid current concentration near the boundary between the active region and the terminal region during body diode conduction without reducing the breakdown tolerance of the SiC-MOSFET.

[0106] As described above, in the SiC-MOSFET 100 of this embodiment, the high-resistance region 8 is provided in the active region 5 and the terminal region 6 so as to straddle the boundary A between the active region 5 and the terminal region 6. With such a structure, it is possible to suppress current crowding from the terminal region 6 to the end of the active region 5, and suppress the concentration of the hole current density near the boundary A between the terminal region 6 and the active region 5.

[0107] Thus, it is possible to effectively suppress the expansion of stacking defects near the boundary A between the terminal region 6 and the active region 5 without making the buffer layer 32 thick. That is, it is possible to manufacture a highly reliable SiC-MOSFET without sacrificing productivity.

[0108] According to the thickness of the silicon carbide epitaxial substrate 30, the distance Di (the boundary in the active region 5 of the high-resistance region 8) between the inner boundary Bi of the high-resistance region 8 corresponding to the boundary between the ohmic contact region 21 and the back electrode layer 20a and the boundary A is set in a plan view. For example, when the thickness of the silicon carbide epitaxial substrate 30 (i.e., the total thickness of the silicon carbide single crystal substrate 31 and the epitaxial growth layer 34) is T [μm], the distance Di is set to be T × 1.0 [μm] or more and T × 10.0 [μm] or less.

[0109] The reason is that when the distance Di is less than T × 1.0 [μm], the effects in this embodiment cannot be obtained sufficiently. In addition, when the distance Di is more than T × 10.0 [μm], the area of the low-resistance region 7 becomes too small relative to the element area of the SiC-MOSFET 100. Therefore, the electrical resistance during energization becomes high. For example, when the thickness of the silicon carbide epitaxial substrate 30 is 100 μm, the distance Di is set to be 100 μm or more and 1000 μm or less.

[0110] On the other hand, the distance Do (the boundary in the terminal region 6 of the high-resistance region 8) between the outer boundary Bo of the high-resistance region 8 and the boundary A is also set according to the thickness of the silicon carbide epitaxial substrate 30. When the thickness of the silicon carbide epitaxial substrate 30 is set to T [μm], the distance Do is set to be T × 1.0 [μm] or more.

[0111] The reason is that when the distance Do is less than T × 1.0 [μm], the effects in this embodiment cannot be obtained sufficiently. The distance Do only needs to be T × 1.0 [μm] or more, and the boundary Bo may not reach near the outermost periphery of the SiC-MOSFET 100. In other words, the outside of the boundary A between the active region 5 and the terminal region 6 may all be the high-resistance region 8.

[0112] There is a case where the adhesion between the single-crystalline silicon carbide substrate 31 and the back electrode 20 is improved by forming an ohmic contact region, i.e., silicide. In this case, as Figure 2 illustrated, by forming a low-resistance region 7 at the outer peripheral end of the terminal region 6, peeling of the back electrode 20 from the end portion of the element can be suppressed.

[0113] Conversely, there is a case where the adhesion between the single-crystalline silicon carbide substrate 31 and the back electrode 20 is reduced by forming an ohmic contact region, i.e., silicide. In this case, by not forming a low-resistance region 7 at the outer peripheral end of the terminal region 6 (i.e., forming a high-resistance region 8 in the entire region of the terminal region 6), peeling of the back electrode 20 from the end portion of the element can be suppressed.

[0114] In addition, the reason why the lower limit values of the distance Di and the distance Do are T×1.0 is that current circulation occurs at an angle of approximately 45°.

[0115] With the structure of the present embodiment, an increase in the current density caused near the boundary A between the active region 5 and the terminal region 6 is suppressed, and current can flow uniformly within the active region 5. As a result, a highly reliable SiC-MOSFET 100 that suppresses deterioration in productivity due to the thickening of the buffer layer 32 and suppresses element degradation can be manufactured.

[0116] <Regarding the manufacturing method of a silicon carbide semiconductor device>

[0117] Next, with reference to Figures 1 to 3 , the manufacturing method of the SiC-MOSFET 100 as a silicon carbide semiconductor device of the present embodiment will be described.

[0118] First, a low-resistance single-crystalline silicon carbide substrate 31 containing a relatively high concentration (n+) of n-type impurities is prepared. In the present embodiment, it is assumed that the single-crystalline silicon carbide substrate 31 is a SiC substrate having a 4H polytype and a dissociation angle of 2° or more and 8° or less.

[0119] Next, on the upper surface of the single-crystalline silicon carbide substrate 31, an n-type buffer layer 32 having an impurity concentration of, for example, 1×10 18 cm -3 or more and 2×10 19 cm -3 or less is epitaxially grown. The thickness of the buffer layer 32 is, for example, 0.5 μm or more and 10 μm or less.

[0120] Next, on the upper surface of the buffer layer 32, an n-type impurity concentration of, for example, 1×10 14 cm -3above and 1×10 17 cm -3 or less, the drift layer 33 is epitaxially grown. The thickness of the drift layer 33 is, for example, 5 μm or more and several hundred μm or less. Thus, the silicon carbide epitaxial substrate 30 can be obtained.

[0121] Next, by repeatedly performing a photolithography process for forming a resist mask and an ion implantation process using the resist mask as an implantation mask, an impurity region is formed on the surface layer of the drift layer 33. Specifically, a p-type terminal well region 16, a p-well region 10, a p-type contact region 12, and an n-type source region 11 are formed on the surface layer of the drift layer 33.

[0122] In the above ion implantation process, N (nitrogen) or the like is used as the n-type impurity, and Al or B or the like is used as the p-type impurity.

[0123] In addition, in the above ion implantation process, the p-well region 10 and the p-type terminal well region 16 may be formed together in the same ion implantation process. In addition, the p-type contact region 12 and the p-type high-concentration terminal well region 17 may be formed together in the same ion implantation process.

[0124] The impurity concentration of the p-well region 10 and the impurity concentration of the p-type terminal well region 16 are, for example, 1.0×10 18 / cm 3 or more and 1.0×10 20 / cm 3 or less. In addition, the impurity concentration of the n-type source region 11 is in a range higher than the impurity concentration of the p-well region 10, for example, 1.0×10 19 / cm 3 or more and 1.0×10 21 / cm 3 or less. In addition, the dose of the p-type contact region 12 and the dose of the extended terminal well region 18 are preferably 0.5×10 13 / cm 2 or more and 5×10 13 / cm 2 or less, for example, 1.0×10 13 / cm 2 .

[0125] When the impurity is Al during ion implantation, the implantation energy, for example, becomes 100 keV or more and 700 keV or less. In this case, the impurity concentration of the p-type extended terminal well region 18 converted according to the dose [cm -2 becomes 1×10 17 / cm 3 or more and 1×10 19 / cm 3Next, in the case where the impurity is N, the implantation energy during ion implantation becomes, for example, 20 keV or more and 300 keV or less.

[0126] After that, using a heat treatment apparatus, annealing at 1500 °C or higher is performed. Thereby, the impurities added during ion implantation are activated.

[0127] Next, for example, by the CVD method, a SiO2 film having a thickness of, for example, 0.5 μm or more and 2 μm or less is formed on the upper surface of the silicon carbide epitaxial substrate 30. Then, by patterning the SiO2 film in a photolithography process and an etching process, a field insulating film 19 is formed.

[0128] At this time, the field insulating film 19 covers a part of the p-type terminal well region 16 and a part of the p-type high-concentration terminal well region 17, extends beyond the end of the p-type terminal well region 16 to the outer peripheral side of the p-type terminal well region 16, and is patterned.

[0129] Next, by thermally oxidizing the upper surface of the drift layer 33 not covered by the field insulating film 19, a SiO2 film serving as the gate insulating film 13 is formed. Then, on the upper surface of the gate insulating film 13, a conductive polysilicon film is formed by the reduced-pressure CVD method, and the polysilicon film is patterned in a photolithography process and an etching process to form a gate electrode 14. At this time, the gate electrode 14 may also be formed to extend onto the upper surface of the field insulating film 19.

[0130] After that, a SiO2 film serving as the interlayer insulating film 15 is formed by the CVD method so as to cover the gate electrode 14. Then, by a photolithography process and an etching process, contact holes that penetrate the gate insulating film 13 and the interlayer insulating film 15 and reach the p-type contact region 12, the n-type source region 11, and each region of the p-type high-concentration terminal well region 17 are formed. In this process, in the terminal region 6, contact holes that penetrate the interlayer insulating film 15 and reach the gate electrode 14 are formed, and the interlayer insulating film 15 in the end edge portions of the interlayer insulating film 15 and the drift layer 33 on the upper surface of the field insulating film 19 are respectively removed.

[0131] Next, by sputtering or evaporation, etc., a layer made of a material for the source electrode 3 or the gate wiring electrode 2 is formed on the upper surface of the silicon carbide epitaxial substrate 30. As the material for these surface electrodes (the source electrode 3 and the gate wiring electrode 2), for example, a metal containing any one or more of Ti, Ni, Al, Cu, Au, or an Al alloy such as Al-Si can be used. In addition, a silicide film may be formed in advance by heat treatment in a portion of the silicon carbide epitaxial substrate 30 that is in contact with the surface electrode.

[0132] Next, in the photolithography process and the etching process, the surface electrode is patterned to separate the surface electrode into the source electrode 3 and the gate wiring electrode 2. At this time, based on the position of the outer peripheral end of the p-type terminal well region 16, the outer peripheral end of the surface electrode in the corner of the terminal region 6 in a top view is positioned more inward than the outer peripheral end of the surface electrode in the straight portion of the terminal region 6 in a top view (such that the outer peripheral end in the corner of the surface electrode is not positioned more outward than the outer peripheral end in the straight portion), and the surface electrode is patterned.

[0133] Next, a surface protective film 4 is formed so as to cover at least a part of the outer peripheral end of the surface electrode and the upper surface of the silicon carbide epitaxial substrate 30 in the terminal region 6. The surface protective film 4 is processed into a desired shape, for example, by coating a photosensitive polyimide and exposure.

[0134] Next, a layer of a material for the back electrode layer 20a is formed on the lower surface of the silicon carbide epitaxial substrate 30 by a sputtering method or an evaporation method or the like. As the material for the back electrode layer 20a, for example, a metal containing any one or more of Ti, Ni, Al, Cu, and Au is used.

[0135] In addition, before forming the back electrode layer 20a, in order to reduce the resistivity during the operation of the SiC-MOSFET 100, the silicon carbide epitaxial substrate 30 can be thinned. Using grinding, polishing, or both techniques, until the silicon carbide epitaxial substrate 30 reaches a desired thickness, the lower surface of the silicon carbide single crystal substrate 31 is removed to achieve thinning. The thickness of the thinned silicon carbide epitaxial substrate 30 is, for example, about 100 μm, and can be 50 μm or more and 200 μm or less.

[0136] Next, the back electrode layer 20a and the silicon carbide single crystal substrate 31 are reacted to form a silicide layer. By forming the silicide layer, an ohmic contact is formed between the back electrode layer 20a and the silicon carbide single crystal substrate 31. That is, the region where the silicide layer is formed becomes Figure 2 the ohmic contact region 21 in

[0137] Hereinafter, a method for forming the ohmic contact region 21, that is, the silicide layer, will be described.

[0138] The formation of the silicide layer is performed by irradiating a laser from the lower surface of the back electrode layer 20a. In addition, during the irradiation of the laser, an annealing treatment can be performed while blowing an inert gas such as nitrogen onto the irradiation surface of the laser.

[0139] Moreover, while gradually shifting the irradiation position of the converged laser beam little by little and irradiating repeatedly, an ohmic contact region 21 is formed. By adjusting the irradiation range of the laser beam, the portions where the silicide layer is provided and the portions where the silicide layer is not provided are appropriately controlled. As exemplified in the present embodiment, a part of the back electrode layer 20a is used to form the ohmic contact region 21.

[0140] Figure 3 FIG. is a plan view showing an example of the region where the ohmic contact region 21 of the present embodiment is formed. The region where the ohmic contact region 21 is formed is the region indicated by oblique lines, and this region is the same as the region where the low-resistance region 7 is formed. On the other hand, the region without oblique lines is the region where the ohmic contact region 21 is not formed, corresponding to the high-resistance region 8. In addition, the boundary A between the active region 5 and the terminal region 6 is shown as a dotted line. In Figure 3 FIG., the region inside the dotted line indicating the boundary A is the active region 5, and the region outside the dotted line indicating the boundary A is the terminal region 6.

[0141] According to Figure 2 FIG., the high-resistance region 8 where the ohmic contact region 21 is not formed is formed in a range straddling the boundary A between the active region 5 and the terminal region 6. In Figure 3 FIG., an ohmic contact region 21 is also formed at the outer peripheral end of the terminal region 6, that is, at the end of the element. However, as described above, the ohmic contact region 21 in this part is not necessarily required, and it is also possible that the ohmic contact region 21 is not formed in the entire terminal region 6 (that is, the entire terminal region 6 is the high-resistance region 8).

[0142] After forming the ohmic contact region 21 by laser annealing, the surface oxide film is removed, and further, the back electrode layer 20b is formed. In this way, it is possible to manufacture Figure 2 the SiC-MOSFET 100 exemplified as the silicon carbide semiconductor device.

[0143] In addition, before forming the back electrode layer 20b, the non-silicided back electrode layer 20a may be removed by etching or the like. In this case, in the high-resistance region 8, the silicon carbide single crystal substrate 31 and the back electrode layer 20b are directly connected.

[0144] In the low-resistance region 7, in order to form the ohmic contact region 21, a silicide is formed by laser annealing. The region silicided by laser annealing tends to have surface irregularities or a large surface roughness. Therefore, even if it is the surface irregularities of the back electrode 20, the surface roughness in the low-resistance region 7 is larger than the surface roughness in the high-resistance region 8.

[0145] <Modification 1>

[0146] In Figure 2An example of a planar transistor is shown, but the transistor as a silicon carbide semiconductor device in the embodiment may also be a trench type.

[0147] In addition, regarding Figure 1 the illustrated SiC-MOSFET 100, the gate wiring electrode 2 as a pad is provided at the upper central portion in a plan view, but the position and shape of the gate wiring electrode 2 as a pad can also be arbitrarily changed. For example, as Figure 4 illustrated, the gate wiring electrode 2A as a pad can be provided at the corner of the SiC-MOSFET 110, or as Figure 5 illustrated, the gate wiring electrode 2B as a pad can be provided so as to pass through the central portion of the SiC-MOSFET 120. In addition, Figure 4 and Figure 5 are plan views schematically showing modified examples of the structure of the SiC-MOSFET of the present embodiment.

[0148] Figure 6 shows the setting Figure 4 An example of a region where the ohmic contact region 21A is formed in the case of the illustrated gate wiring electrode 2A as a pad for gate wiring is shown in a plan view. The region where the ohmic contact region 21A is formed is the region indicated by oblique lines, and this region is the same as the region where the low-resistance region 7 is formed. On the other hand, the region without oblique lines is the region where the ohmic contact region 21A is not formed, and corresponds to the high-resistance region 8. In addition, the boundary A between the active region 5 and the terminal region 6 is shown as a dotted line. In Figure 6 it, the region inside the dotted line indicating the boundary A is the active region 5, and the region outside the dotted line indicating the boundary A is the terminal region 6.

[0149] Figure 7 shows the setting Figure 5 An example of a region where the ohmic contact region 21B is formed in the case of the illustrated gate wiring electrode 2B as a pad for gate wiring is shown in a plan view. The region where the ohmic contact region 21B is formed is the region indicated by oblique lines, and this region is the same as the region where the low-resistance region 7 is formed. On the other hand, the region without oblique lines is the region where the ohmic contact region 21B is not formed, and corresponds to the high-resistance region 8. In addition, the boundary A between the active region 5 and the terminal region 6 is shown as a dotted line. In Figure 7 it, the region inside the dotted line indicating the boundary A is the active region 5, and the region outside the dotted line indicating the boundary A is the terminal region 6.

[0150] In addition, in Figure 6 and Figure 7In the above, an ohmic contact region 21A or an ohmic contact region 21B is also formed at the outer peripheral end of the terminal region 6, that is, at the end of the element. However, as described above, the ohmic contact region 21A or the ohmic contact region 21B in this part is not necessarily required, and it may also be the case where the ohmic contact region 21A or the ohmic contact region 21B is not formed in the entire terminal region 6 (that is, the entire terminal region 6 is a high-resistance region 8).

[0151] With these configurations, compared to Figure 3 the illustrated configuration, the shape of the region where the ohmic contact region is formed is simplified, so it becomes easier to manufacture a highly reliable element.

[0152] <Modified Example 2>

[0153] In Figures 1 to 7 the example shown, an ohmic contact region is provided in the entire region of the low-resistance region 7. On the other hand, it is important that the average resistivity from the silicon carbide single-crystalline substrate 31 to the back electrode 20 in the high-resistance region 8 is higher than the average resistivity in the low-resistance region 7. Therefore, it is not necessary to form an ohmic contact region in the entire region of the low-resistance region 7.

[0154] Figure 8 is a cross-sectional view schematically showing a modified example of the structure of the peripheral portion of the SiC-MOSFET of the present embodiment. As Figure 8 illustrated, the SiC-MOSFET 101 is formed using a silicon carbide epitaxial substrate 30. The silicon carbide epitaxial substrate 30 includes a silicon carbide single-crystalline substrate 31 and an epitaxial growth layer 34 formed on the upper surface of the silicon carbide single-crystalline substrate 31.

[0155] On the upper surface side of the surface layer of the drift layer 33 in the active region 5, a p-well region 10 is selectively formed. In addition, on the surface layer of the p-well region 10, an n-type source region 11 and a p-type contact region 12 having an impurity concentration higher than that of the p-well region 10 are selectively formed, respectively.

[0156] On the upper surface of the silicon carbide epitaxial substrate 30 in the active region 5, a gate insulating film 13 is formed so as to cover the p-well region 10 portion sandwiched between the n-type source region 11 and the drift layer 33. In addition, a gate electrode 14 is formed on the upper surface of the gate insulating film 13.

[0157] In the active region 5, the gate electrode 14 is covered with an interlayer insulating film 15. In addition, a source electrode 3 is formed on the upper surface of the interlayer insulating film 15.

[0158] The terminal region 6 surrounds the active region 5 when viewed from above. On the surface layer on the upper surface side of the epitaxial growth layer 34 in the terminal region 6, that is, the surface layer of the drift layer 33, a p-type terminal well region 16 is selectively formed so as to surround the active region 5.

[0159] On the surface layer of the p-type terminal well region 16, a p-type high-concentration terminal well region 17 having an impurity concentration higher than that of the p-type terminal well region 16 is formed. In addition, on the outer peripheral portion of the p-type terminal well region 16, a p-type extended terminal well region 18 for maintaining the breakdown voltage of the silicon carbide semiconductor device is formed.

[0160] Furthermore, a field insulating film 19, a gate wiring electrode 2, and a surface protective film 4 are provided on the upper surface of the silicon carbide epitaxial substrate 30 in the terminal region 6.

[0161] On the other hand, a back electrode 520 is provided on the lower surface of the silicon carbide epitaxial substrate 30. The back electrode 520 includes a back electrode layer 20a, a back electrode layer 20b, an ohmic contact region 21C, and a non-ohmic contact region 22. The back electrode layer 20a is partially formed on the lower surface of the silicon carbide single crystal substrate 31. The ohmic contact region 21C and the non-ohmic contact region 22 are formed in a portion of the lower surface of the silicon carbide single crystal substrate 31 where the back electrode layer 20a is not formed. Furthermore, the back electrode layer 20b is formed on the lower surfaces of the back electrode layer 20a, the ohmic contact region 21C, and the non-ohmic contact region 22.

[0162] In Figure 8 In the illustrated configuration, the ohmic contact region 21C and the non-ohmic contact region 22 are provided in the low-resistance region 7. According to such a configuration, the processing time of laser annealing can be shortened, so that effects such as an improvement in productivity can be obtained.

[0163] In addition, the resistivity from the silicon carbide single crystal substrate 31 to the back electrode 520 (or the back electrode 20) may be continuously changed at the boundary between the low-resistance region 7 and the high-resistance region 8. In this case, by continuously changing the irradiation interval of the laser, the resistivity per unit area can be changed. Thereby, the uniformity of the current density in the epitaxial growth layer 34 can be more precisely controlled.

[0164] As described above, according to the SiC-MOSFET of the present embodiment, even when a forward current having a large current density flows in the body diode of the field effect transistor, it is not necessary to significantly increase the thickness of the buffer layer 32, and fluctuations in element characteristics can be suppressed.

[0165] <Second Embodiment>

[0166] Describe the silicon carbide semiconductor device of this embodiment. In addition, in the following description, components that are the same as those described in the above-described embodiment are denoted by the same reference numerals and illustrated, and detailed descriptions thereof are appropriately omitted.

[0167] <Regarding the structure of the silicon carbide semiconductor device>

[0168] In the first embodiment, the resistivity is changed according to the formation of an ohmic contact region, and the low-resistance region 7 and the high-resistance region 8 are separately fabricated. In contrast, it is also possible to change the resistivity by changing the impurity concentration in the lower surface of the silicon carbide single crystal substrate 31, and separately fabricate the low-resistance region 7 and the high-resistance region 8.

[0169] Figure 9 It is a cross-sectional view schematically showing an example of the structure of the periphery of the SiC-MOSFET 200 of this embodiment. Figure 9 And Figure 1 corresponds to the a-a' cross-section in. In addition, the top view of the SiC-MOSFET 200 of this embodiment is the same as that in the first embodiment, Figure 1 so detailed description is omitted.

[0170] As Figure 9 illustrated, the SiC-MOSFET 200 is formed using a silicon carbide epitaxial substrate 30. The silicon carbide epitaxial substrate 30 includes a silicon carbide single crystal substrate 31 and an epitaxial growth layer 34 formed on the upper surface of the silicon carbide single crystal substrate 31.

[0171] On the upper surface side of the surface layer of the drift layer 33 in the active region 5, a p-well region 10 is selectively formed. In addition, on the surface layer of the p-well region 10, an n-type source region 11 and a p-type contact region 12 having an impurity concentration higher than that of the p-well region 10 are selectively formed, respectively.

[0172] On the upper surface of the silicon carbide epitaxial substrate 30 in the active region 5, a gate insulating film 13 is formed so as to cover the p-well region 10 that is sandwiched between the n-type source region 11 and the drift layer 33. In addition, a gate electrode 14 is formed on the upper surface of the gate insulating film 13.

[0173] In the active region 5, the gate electrode 14 is covered with an interlayer insulating film 15. In addition, a source electrode 3 is formed on the upper surface of the interlayer insulating film 15.

[0174] The terminal region 6 surrounds the active region 5 in a plan view. On the upper surface side of the surface layer of the epitaxial growth layer 34 in the terminal region 6, that is, on the surface layer of the drift layer 33, a p-type terminal well region 16 is selectively formed so as to surround the active region 5.

[0175] On the surface layer of the p-type terminal well region 16, a p-type high-concentration terminal well region 17 having an impurity concentration higher than that of the p-type terminal well region 16 is formed. Further, on the outer peripheral portion of the p-type terminal well region 16, a p-type extended terminal well region 18 for maintaining the breakdown voltage of the silicon carbide semiconductor device is formed.

[0176] Furthermore, on the upper surface of the silicon carbide epitaxial substrate 30 in the terminal region 6, a field insulating film 19, a gate wiring electrode 2, and a surface protective film 4 are provided.

[0177] On the other hand, an ion implantation region 40 is partially formed on the surface layer side of the lower surface of the silicon carbide epitaxial substrate 30. In addition, a back electrode 320 is provided on the lower surface of the silicon carbide epitaxial substrate 30. The back electrode 320 includes an ohmic contact region 21 as a silicide region formed over the entire lower surface of the silicon carbide single crystal substrate 31 and a back electrode layer 20b formed over the entire lower surface of the ohmic contact region 21.

[0178] Regarding the region where the ion implantation region 40 is provided, the resistivity from the silicon carbide single crystal substrate 31 to the back electrode 320 increases. Therefore, this region functions as a high-resistance region 8. As a result, the region where the ion implantation region 40 is not provided becomes a low-resistance region 7 having a relatively low resistivity, and a difference in current density is generated between the low-resistance region 7 and the high-resistance region 8 where the ion implantation region 40 is provided.

[0179] That is, in the present embodiment, in the surface layer on the lower surface side of the silicon carbide single crystal substrate 31, the ion implantation region 40 functioning as the high-resistance region 8 is provided in the active region 5 and the terminal region 6 so as to straddle the boundary A. The range in which the ion implantation region 40 is formed is, for example, the same as the range of the high-resistance region 8 in Figure 2 In addition, the impurity concentration of the ion implantation region 40 is different from the impurity concentration near the center in plan view of the active region 5.

[0180] <Regarding the manufacturing method of the silicon carbide semiconductor device>

[0181] Next, with reference to Figure 9 the manufacturing method of the SiC-MOSFET 200 as the silicon carbide semiconductor device in the present embodiment will be described.

[0182] First, in the same manner as in the case of the first embodiment, various structures up to the surface protective film 4 on the upper surface of the silicon carbide epitaxial substrate 30 are formed.

[0183] Next, the fabrication of the structure on the lower surface side of the silicon carbide epitaxial substrate 30 will be described. In addition, the fabrication of the structure on the lower surface side of the silicon carbide epitaxial substrate 30 can also be carried out after thinning the silicon carbide epitaxial substrate 30 to a desired thickness. Additionally, the timing of fabricating the structure on the lower surface side of the silicon carbide epitaxial substrate 30 can be appropriately selected in the manufacturing process. That is, it can be either after the fabrication of the structure on the upper surface side of the silicon carbide epitaxial substrate 30 is completed, or it can be carried out during the fabrication of the structure on the upper surface side of the silicon carbide epitaxial substrate 30.

[0184] In the fabrication of the structure on the lower surface side of the silicon carbide epitaxial substrate 30, through a photolithography process of forming a resist mask on the lower surface of the silicon carbide single crystal substrate 31 and an ion implantation process of performing ion implantation using this resist mask as an implantation mask, an ion implantation region 40 is formed partially in the surface layer portion on the lower surface side of the silicon carbide single crystal substrate 31. At this time, the element used in the ion implantation is not particularly limited. For example, it is a p-type impurity such as aluminum (Al), boron (B), gallium (Ga), or indium (In). Additionally, in the case where the impurity is Al, the implantation energy of the ion implantation is, for example, several hundred keV, and the maximum value of the impurity concentration converted according to the dose [cm -2 is, for example, 1×10 18 / cm 3 or more.

[0185] After that, using a heat treatment apparatus, annealing at 1500 °C or higher is performed. As a result, the impurities added by the ion implantation are activated. The annealing for activating this impurity can be carried out either simultaneously with the activation annealing of the structure on the upper surface side of the silicon carbide epitaxial substrate 30 or independently of the activation annealing of the structure on the upper surface side of the silicon carbide epitaxial substrate 30.

[0186] By performing the above activation annealing, the carrier concentration in the ion implanted region decreases, and the resistivity increases significantly. Therefore, this region functions as a high resistance region.

[0187] In addition, the activation annealing of the ion implantation region 40 in the surface layer on the lower surface side of the silicon carbide epitaxial substrate 30 is not an essential process. Therefore, it can also be omitted. Additionally, in the case of using an n-type impurity such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) as the impurity, conversely, activation annealing cannot be performed.

[0188] The reason for not requiring activation annealing is that through high-density ion implantation, a large number of implantation defects are formed in the single crystal, and it functions as a high resistance region 8 that takes this as a resistance component. This is the same regardless of whether a p-type impurity or an n-type impurity is implanted.

[0189] In addition, in the case of ion-implanting n-type impurities, the reason why activation annealing cannot be performed is that when activation annealing is performed on n-type impurities, the implanted defects are restored, the carrier concentration increases, and the resistance value decreases.

[0190] In addition, elements that form deep energy levels such as vanadium (V) or titanium (Ti) can also be used as impurity elements. By using these impurity elements, the resistivity of the region where these elements are introduced increases, and a high-resistance region 8 can be formed.

[0191] Next, a layer of the material for the back electrode layer 20a is formed on the lower surface of the silicon carbide epitaxial substrate 30 by a sputtering method or an evaporation method or the like. As the material for the back electrode layer 20a, for example, a metal containing any one or more of Ti, Ni, Al, Cu, and Au is used.

[0192] Next, the back electrode layer 20a and the silicon carbide single crystal substrate 31 are reacted to form a silicide layer. By forming this silicide layer, an ohmic contact region 21 where the back electrode layer 20a and the silicon carbide single crystal substrate 31 are in ohmic contact is formed.

[0193] The method for forming the silicide can be either the heat treatment using laser annealing described in the first embodiment or the thermal annealing treatment using a heat treatment apparatus. Since laser annealing has been described in detail in the first embodiment, the description thereof is omitted here. Regarding thermal annealing, for example, if it is Ni, heat treatment is performed at 1000°C.

[0194] After that, the surface oxide film is removed to form the back electrode layer 20b. In this way, it is possible to manufacture Figure 9 the SiC-MOSFET 200 exemplified as the silicon carbide semiconductor device.

[0195] Regarding the SiC-MOSFET 200 manufactured in this way, an increase in the current density caused near the boundary A between the active region 5 and the terminal region 6 is suppressed, and current can flow uniformly within the active region 5. As a result, there is no need to increase the thickness of the buffer layer 32, so deterioration in productivity can be suppressed. In addition, a highly reliable silicon carbide semiconductor device can be manufactured.

[0196] In addition, in Figure 9 a low-resistance region 7 is formed at the outer peripheral end of the terminal region 6, that is, at the end of the element. However, the low-resistance region 7 in this part is not necessarily required, and it is also possible that the low-resistance region 7 is not formed in the entire terminal region 6 (that is, the entire terminal region 6 is a high-resistance region 8).

[0197] <Modification 1>

[0198] Figure 9The impurity concentration of the ion implantation region 40 shown does not need to be constant, and may also vary continuously or stepwise. Figure 10 It is a cross-sectional view schematically showing a modified example of the structure of the peripheral portion of the SiC-MOSFET of the present embodiment.

[0199] As Figure 10 Illustrated, the SiC-MOSFET 201 is formed using a silicon carbide epitaxial substrate 30. The silicon carbide epitaxial substrate 30 includes a silicon carbide single crystal substrate 31 and an epitaxial growth layer 34 formed on the upper surface of the silicon carbide single crystal substrate 31.

[0200] On the surface layer on the upper surface side of the drift layer 33 in the active region 5, a p-well region 10 is selectively formed. In addition, on the surface layer of the p-well region 10, an n-type source region 11 and a p-type contact region 12 having an impurity concentration higher than that of the p-well region 10 are selectively formed, respectively.

[0201] On the upper surface of the silicon carbide epitaxial substrate 30 in the active region 5, a gate insulating film 13 is formed so as to cover the p-well region 10 portion sandwiched between the n-type source region 11 and the drift layer 33. In addition, a gate electrode 14 is formed on the upper surface of the gate insulating film 13.

[0202] In the active region 5, the gate electrode 14 is covered with an interlayer insulating film 15. In addition, a source electrode 3 is formed on the upper surface of the interlayer insulating film 15.

[0203] The terminal region 6 surrounds the active region 5 in a plan view. On the surface layer on the upper surface side of the epitaxial growth layer 34 in the terminal region 6, that is, on the surface layer of the drift layer 33, a p-type terminal well region 16 is selectively formed so as to surround the active region 5.

[0204] On the surface layer of the p-type terminal well region 16, a p-type high-concentration terminal well region 17 having an impurity concentration higher than that of the p-type terminal well region 16 is formed. In addition, on the outer peripheral portion of the p-type terminal well region 16, a p-type extended terminal well region 18 for maintaining the breakdown voltage of the silicon carbide semiconductor device is formed.

[0205] Furthermore, on the upper surface of the silicon carbide epitaxial substrate 30 in the terminal region 6, a field insulating film 19, a gate wiring electrode 2, and a surface protective film 4 are provided.

[0206] On the other hand, an ion implantation region 340 is partially formed on the surface layer on the lower surface side of the silicon carbide epitaxial substrate 30. In addition, a back electrode 320 is provided on the lower surface of the silicon carbide epitaxial substrate 30. The back electrode 320 includes an ohmic contact region 21 as a silicide region formed over the entire lower surface of the silicon carbide single crystal substrate 31 and a back electrode layer 20b formed over the entire lower surface of the ohmic contact region 21.

[0207] Regarding the region where the ion implantation region 340 is provided, the resistivity from the silicon carbide single crystal substrate 31 to the back electrode 320 increases. Therefore, this region functions as a high-resistance region 8. As a result, the region where the ion implantation region 40 is not provided becomes a low-resistance region 7 with a relatively low resistivity, and a difference in current density is generated between the low-resistance region 7 and the high-resistance region 8 where the ion implantation region 40 is provided.

[0208] The ion implantation region 340 includes ion implantation layers 40a, 40b, 40c, and 40d with different impurity concentrations. Figure 10 Among them, the ion implantation layers 40a, 40b, 40c, and 40d are sequentially provided from the side closer to the active region 5.

[0209] The impurity concentration of the ion implantation layers 40a, 40b, 40c, and 40d may continuously change from the side closer to the active region 5, or may change stepwise from the side closer to the active region 5. In addition, it may be such that the impurity concentration is the highest near the boundary A and decreases as the distance from the boundary A increases. In addition, the impurity concentration may be controlled in such a way that the resistivity continuously changes at the boundary Bi or the boundary Bo between the low-resistance region 7 and the high-resistance region 8.

[0210] In addition, Figure 10 in the example, the ion implantation region 340 is composed of four ion implantation layers, but the number of ion implantation layers constituting the ion implantation region 340 is not limited to four, and two or more are sufficient.

[0211] According to Figure 10 the illustrated structure, the current density in the epitaxial growth layer 34 can be controlled more precisely.

[0212] In addition, Figure 9 and Figure 10 in the illustrated structure, the ohmic contact region 21 is formed over the entire lower surface of the silicon carbide single crystal substrate 31, but the range where the ohmic contact region 21 is formed may also be a part of the lower surface of the silicon carbide single crystal substrate 31.

[0213] <The Third Embodiment>

[0214] A silicon carbide semiconductor device according to this embodiment will be described. In the following description, components that are the same as those described in the above-described embodiment are denoted by the same reference numerals and illustrated, and detailed descriptions thereof are appropriately omitted.

[0215] <Regarding the structure of the silicon carbide semiconductor device>

[0216] In the first and second embodiments, the low-resistance region 7 and the high-resistance region 8 are separately formed according to the presence or absence of an ohmic contact region and the presence or absence of an ion implantation region. In contrast, the low-resistance region 7 and the high-resistance region 8 can also be separately formed according to the presence or absence of a back electrode.

[0217] Figure 11 FIG. is a cross-sectional view schematically showing an example of the structure of the peripheral portion of the SiC-MOSFET 300 according to this embodiment. Figure 11 corresponds to the cross-section taken along the line a-a' in Figure 1 In addition, the top view of the SiC-MOSFET 300 according to this embodiment is the same as that in the first embodiment, so detailed description thereof is omitted. Figure 1 same, so detailed description is omitted.

[0218] As Figure 11 illustrated, the SiC-MOSFET 300 is formed using a silicon carbide epitaxial substrate 30. The silicon carbide epitaxial substrate 30 includes a silicon carbide single crystal substrate 31 and an epitaxial growth layer 34 formed on the upper surface of the silicon carbide single crystal substrate 31.

[0219] On the upper surface side of the drift layer 33 in the active region 5, a p-well region 10 is selectively formed. In addition, on the upper surface of the p-well region 10, an n-type source region 11 and a p-type contact region 12 having an impurity concentration higher than that of the p-well region 10 are selectively formed, respectively.

[0220] On the upper surface of the silicon carbide epitaxial substrate 30 in the active region 5, a gate insulating film 13 is formed so as to cover the p-well region 10 between the n-type source region 11 and the drift layer 33. In addition, a gate electrode 14 is formed on the upper surface of the gate insulating film 13.

[0221] In the active region 5, the gate electrode 14 is covered with an interlayer insulating film 15. In addition, a source electrode 3 is formed on the upper surface of the interlayer insulating film 15.

[0222] The terminal region 6 surrounds the active region 5 in a plan view. On the upper surface side of the epitaxial growth layer 34 in the terminal region 6, that is, on the upper surface of the drift layer 33, a p-type terminal well region 16 is selectively formed so as to surround the active region 5.

[0223] On the surface layer of the p-type terminal well region 16, a p-type high-concentration terminal well region 17 having an impurity concentration higher than that of the p-type terminal well region 16 is formed. In addition, on the outer peripheral portion of the p-type terminal well region 16, a p-type extended terminal well region 18 for maintaining the breakdown voltage of the silicon carbide semiconductor device is formed.

[0224] Furthermore, on the upper surface of the silicon carbide epitaxial substrate 30 in the terminal region 6, a field insulating film 19, a gate wiring electrode 2, and a surface protective film 4 are provided.

[0225] On the other hand, on the lower surface of the silicon carbide epitaxial substrate 30, a back electrode 620 is partially formed. The back electrode 620 includes an ohmic contact region 21 and a back electrode layer 420. The ohmic contact region 21 as a silicide region is partially formed on the lower surface of the silicon carbide epitaxial substrate 30. In addition, on the lower surface of the ohmic contact region 21, a back electrode layer 420 is provided.

[0226] In the present embodiment, as Figure 11 illustrated, on the lower surface of the silicon carbide epitaxial substrate 30, there are a region where both the ohmic contact region 21 and the back electrode layer 420 of the back electrode 620 are formed and a region where neither the ohmic contact region 21 nor the back electrode layer 420 is formed.

[0227] In this case, the region where neither the ohmic contact region 21 nor the back electrode layer 420 is formed functions as a high-resistance region 8. As a result, a resistivity difference occurs from the silicon carbide single crystal substrate 31 to the back electrode 620 between the low-resistance region 7 where both the ohmic contact region 21 and the back electrode layer 420 are formed and the high-resistance region 8 where neither the ohmic contact region 21 nor the back electrode layer 420 is formed. Specifically, since it is difficult for current to flow in the high-resistance region 8, the current density in the high-resistance region 8 is reduced.

[0228] That is, in the structure shown in the present embodiment, the high-resistance region 8 is provided in the active region 5 and the terminal region 6 so as to straddle the boundary A between the active region 5 and the terminal region 6. In addition, the range that becomes the high-resistance region 8 is, for example, the same as the range of the high-resistance region 8 in Figure 2 the [reference].

[0229] As described above, by making the region where neither the ohmic contact region 21 nor the back electrode layer 420 is formed function as the high-resistance region 8, the current path in the high-resistance region 8 can be completely cut off. Therefore, the effect of reducing the current density in the high-resistance region 8 becomes more significant.

[0230] In addition, in Figure 11In the structure shown, a low-resistance region 7 may not be formed at the outer peripheral end of the terminal region 6 (that is, a high-resistance region 8 may be formed in the entire region of the terminal region 6).

[0231] <Method of manufacturing a silicon carbide semiconductor device>

[0232] Next, with reference to Figure 11 , a method of manufacturing the SiC-MOSFET 300 as a silicon carbide semiconductor device according to the present embodiment will be described.

[0233] First, in the same manner as in the first embodiment, various structures up to the surface protective film 4 are formed on the upper surface of the silicon carbide epitaxial substrate 30.

[0234] Next, the manufacturing of the structure on the lower surface side of the silicon carbide epitaxial substrate 30 will be described. In addition, the manufacturing of the structure on the lower surface side of the silicon carbide epitaxial substrate 30 can also be performed after thinning the silicon carbide epitaxial substrate 30 to a desired thickness. Further, the manufacturing timing of the structure on the lower surface side of the silicon carbide epitaxial substrate 30 can be appropriately selected in the manufacturing process. That is, it can be either after the manufacturing of the structure on the upper surface side of the silicon carbide epitaxial substrate 30 is completed, or it can also be performed during the manufacturing of the structure on the upper surface side of the silicon carbide epitaxial substrate 30.

[0235] In the manufacturing of the structure on the lower surface side of the silicon carbide epitaxial substrate 30, first, a layer of a material for the back electrode layer 20a is formed on the lower surface of the silicon carbide epitaxial substrate 30 by a sputtering method or an evaporation method or the like. As the material for the back electrode layer 20a, for example, a metal containing any one or more of Ti, Ni, Al, Cu, and Au is used.

[0236] Next, the back electrode layer 20a and the silicon carbide single crystal substrate 31 are reacted to form a silicide layer. By forming this silicide layer, an ohmic contact region 21 in which the back electrode layer 20a and the silicon carbide single crystal substrate 31 are in ohmic contact is formed.

[0237] The method of forming the silicide can be either the heat treatment using laser annealing described in the first embodiment or the thermal annealing treatment using a heat treatment apparatus. Since laser annealing has been described in detail in the first embodiment, the description thereof is omitted here. Regarding thermal annealing, for example, if it is Ni, heat treatment is performed at 1000 °C.

[0238] After that, the surface oxide film is removed to form the back electrode layer 420. Further, a mask is formed on the lower surface of the silicon carbide single crystal substrate 31 by a photolithography process or the like, and then the back electrode layer 420 and the ohmic contact region 21 are selectively etched using this mask. Thereby, it is possible to manufacture Figure 11Exemplary SiC-MOSFET 300 as a silicon carbide semiconductor device.

[0239] In addition, in the present embodiment, the low-resistance region 7 and the high-resistance region 8 are separately formed according to the presence or absence of the back electrode layer 420 and the ohmic contact region 21. However, the low-resistance region 7 and the high-resistance region 8 can also be separately formed by forming electrode layers using different types of metals in the respective regions of the low-resistance region 7 and the high-resistance region 8.

[0240] Figure 12 It is a cross-sectional view schematically showing a modified example of the structure of the peripheral portion of the SiC-MOSFET of the present embodiment. As Figure 12 Exemplified, the SiC-MOSFET 301 is formed using a silicon carbide epitaxial substrate 30. The silicon carbide epitaxial substrate 30 includes a silicon carbide single crystal substrate 31 and an epitaxial growth layer 34 formed on the upper surface of the silicon carbide single crystal substrate 31.

[0241] On the upper surface side surface layer of the drift layer 33 in the active region 5, a p-well region 10 is selectively formed. In addition, on the surface layer of the p-well region 10, an n-type source region 11 and a p-type contact region 12 having an impurity concentration higher than that of the p-well region 10 are selectively formed, respectively.

[0242] On the upper surface of the silicon carbide epitaxial substrate 30 in the active region 5, a gate insulating film 13 is formed so as to cover the p-well region 10 of the portion sandwiched between the n-type source region 11 and the drift layer 33. In addition, a gate electrode 14 is formed on the upper surface of the gate insulating film 13.

[0243] In the active region 5, the gate electrode 14 is covered with an interlayer insulating film 15. In addition, a source electrode 3 is formed on the upper surface of the interlayer insulating film 15.

[0244] The terminal region 6 surrounds the active region 5 in plan view. On the upper surface side surface layer of the epitaxial growth layer 34 in the terminal region 6, that is, on the surface layer of the drift layer 33, a p-type terminal well region 16 is selectively formed so as to surround the active region 5.

[0245] On the surface layer of the p-type terminal well region 16, a p-type high-concentration terminal well region 17 having an impurity concentration higher than that of the p-type terminal well region 16 is formed. In addition, on the outer peripheral portion of the p-type terminal well region 16, a p-type extended terminal well region 18 for maintaining the breakdown voltage of the silicon carbide semiconductor device is formed.

[0246] Furthermore, a field insulating film 19, a gate wiring electrode 2, and a surface protective film 4 are provided on the upper surface of the silicon carbide epitaxial substrate 30 in the terminal region 6.

[0247] On the other hand, a back electrode 720 is provided on the lower surface of the silicon carbide epitaxial substrate 30. The back electrode 720 includes a back electrode layer 721 as a metal layer and a back electrode layer 722 as a metal layer containing a metal of a different type from the back electrode layer 721. The back electrode layer 721 is partially formed on the lower surface of the silicon carbide single crystal substrate 31. The back electrode layer 722 is formed on a portion of the lower surface of the silicon carbide single crystal substrate 31 where the back electrode layer 721 is not formed.

[0248] In Figure 12 In the illustrated configuration, the back electrode layer 721 is provided in the low-resistance region 7. On the other hand, the back electrode layer 722 having a contact resistivity with the silicon carbide single crystal substrate 31 higher than that of the back electrode layer 721 is provided in the high-resistance region 8.

[0249] As described above, according to the SiC-MOSFET of the present embodiment, even when a forward current having a large current density flows through the body diode of the field effect transistor, it is possible to suppress variations in element characteristics without significantly increasing the thickness of the buffer layer 32.

[0250] <Fourth Embodiment>

[0251] The power conversion device and the manufacturing method of the power conversion device according to the present embodiment will be described. In the following description, the same reference numerals are given to the same components as those described in the above-described embodiments, and the detailed description thereof will be appropriately omitted.

[0252] <Regarding the Structure of the Power Conversion Device>

[0253] The present embodiment is an example in which the silicon carbide semiconductor device of the above-described embodiment is applied to a power conversion device. The applied power conversion device is not limited to a specific use, but hereinafter, the case of applying it to a three-phase inverter will be described.

[0254] Figure 13 FIG. is an example showing the structure of a power conversion system including the power conversion device of the present embodiment conceptually.

[0255] As Figure 13 Illustrated, the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200. The power supply 2100 can be composed of various power supplies, for example, it can be composed of a DC system, a solar cell, or a storage battery, etc. In addition, the power supply 2100 can be composed of a rectifier circuit or an AC-DC converter connected to an AC system. In addition, the power supply 2100 can also be composed of a DC-DC converter that converts the DC power output from the DC system into predetermined power.

[0256] The power conversion device 2200 is a three-phase inverter connected between a power supply 2100 and a load 2300. The power conversion device 2200 converts the DC power supplied from the power supply 2100 into AC power and then supplies the AC power to the load 2300.

[0257] In addition, as Figure 13 illustrated, the power conversion device 2200 includes: a conversion circuit 2201 that converts DC power into AC power and outputs it; a drive circuit 2202 that outputs drive signals for driving the respective switching elements of the conversion circuit 2201; and a control circuit 2203 that outputs control signals for controlling the drive circuit 2202 to the drive circuit 2202.

[0258] The load 2300 is a three-phase motor driven by the AC power supplied from the power conversion device 2200. In addition, the load 2300 is not limited to a specific use and is a motor mounted on various electrical devices. For example, it is also used as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0259] Hereinafter, the power conversion device 2200 will be described in detail. The conversion circuit 2201 includes switching elements and freewheeling diodes (not shown here). Moreover, through the switching operation of the switching elements, the DC power supplied from the power supply 2100 is converted into AC power and then supplied to the load 2300.

[0260] There are various examples of the specific circuit structure of the conversion circuit 2201, but the conversion circuit 2201 of the present embodiment is a two-level three-phase full-bridge circuit and includes six switching elements and six freewheeling diodes connected in anti-parallel with the respective switching elements.

[0261] In at least one of the respective switching elements and the respective freewheeling diodes in the conversion circuit 2201, a silicon carbide semiconductor device according to any one of the embodiments described above is applied. Regarding the six switching elements, every two switching elements are connected in series to form upper and lower branches, and each of the upper and lower branches constitutes each phase (i.e., the U phase, the V phase, and the W phase) of the full-bridge circuit. Moreover, the output terminals of each of the upper and lower branches (i.e., the three output terminals of the conversion circuit 2201) are connected to the load 2300.

[0262] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201 and then supplies the drive signals to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, according to the control signals output from the control circuit 2203 described later, drive signals that make the switching elements in the on state and drive signals that make the switching elements in the off state are output to the control electrodes of the respective switching elements.

[0263] When the switching element is maintained in the on state, the drive signal is a voltage signal above the threshold voltage of the switching element (i.e., an on signal), and when the switching element is maintained in the off state, the drive signal becomes a voltage signal below the threshold voltage of the switching element (i.e., an off signal).

[0264] The control circuit 2203 controls the switching elements of the conversion circuit 2201 in such a way as to supply desired power to the load 2300. Specifically, based on the power to be supplied to the load 2300, the time during which each switching element of the conversion circuit 2201 should be in the on state (i.e., the on time) is calculated. For example, the conversion circuit 2201 can be controlled by PWM control in which the on time of the switching element is modulated according to the voltage to be output.

[0265] Moreover, the control circuit 2203 outputs a control command (i.e., a control signal) to the drive circuit 2202 in such a way as to output an on signal to the switching element that should be in the on state at each time point and an off signal to the switching element that should be in the off state. The drive circuit 2202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element based on this control signal.

[0266] In the power conversion device 2200 of the present embodiment, a silicon carbide semiconductor device of any of the above-described embodiments is applied as the switching element of the conversion circuit 2201, so that the on-resistance after the energization cycle can be stabilized.

[0267] In addition, in the present embodiment, an example in which a silicon carbide semiconductor device of any of the above-described embodiments is applied to a two-level three-phase inverter has been described, but the application example is not limited thereto, and a silicon carbide semiconductor device of any of the above-described embodiments can be applied to various power conversion devices.

[0268] In addition, in the present embodiment, a two-level power conversion device has been described, but a silicon carbide semiconductor device of any of the above-described embodiments can also be applied to a three-level or multi-level power conversion device. In addition, when supplying power to a single-phase load, a silicon carbide semiconductor device of any of the above-described embodiments can also be applied to a single-phase inverter.

[0269] In addition, when supplying power to a DC load or the like, a silicon carbide semiconductor device of any of the above-described embodiments can also be applied to a DC-DC converter or an AC-DC converter.

[0270] In addition, the power conversion device using the silicon carbide semiconductor device according to any of the above-described embodiments is not limited to the case where the load is a motor as described above. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system. In addition, the power conversion device using the silicon carbide semiconductor device according to any of the above-described embodiments can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

[0271] <Method for manufacturing a power conversion device>

[0272] Next, a method for manufacturing the power conversion device of the present embodiment will be described.

[0273] First, a silicon carbide semiconductor device is manufactured by the manufacturing method described in the above-described embodiments. Then, the conversion circuit 2201 having the silicon carbide semiconductor device is configured as the structure of the power conversion device. The conversion circuit 2201 is a circuit for converting the input power and outputting it.

[0274] Moreover, a drive circuit 2202 is provided as the structure of the power conversion device. The drive circuit 2202 is a circuit that outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device. Moreover, a control circuit 2203 is provided as the structure of the power conversion device. The control circuit 2203 is a circuit that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

[0275] The semiconductor switching element used in the above-described embodiments is not limited to a switching element made of silicon (Si) semiconductor. For example, the semiconductor switching element may be made of a non-Si semiconductor material having a wider bandgap than the Si semiconductor.

[0276] Examples of wide bandgap semiconductors as non-Si semiconductor materials include silicon carbide, gallium nitride-based materials, or diamond.

[0277] A switching element made of a wide bandgap semiconductor can also be used in a high voltage region where it is difficult for an Si semiconductor to operate in a unipolar manner, and the switching loss occurring during the switching operation can be significantly reduced. Therefore, the power loss can be significantly reduced.

[0278] In addition, a switching element made of a wide bandgap semiconductor has low power loss and high heat resistance. Therefore, when forming a power module having a cooling unit, the heat sink fins can be miniaturized, so that the semiconductor module can be further miniaturized.

[0279] In addition, a switching element made of a wide-bandgap semiconductor is suitable for high-frequency switching operations. Therefore, in the case of being applied to a converter circuit with a high demand for high-frequency operation, it is also possible to miniaturize a reactor, a capacitor, or the like connected to the converter circuit by increasing the switching frequency.

[0280] Therefore, in the case where the semiconductor switching element in the above-described embodiment is a switching element made of a wide-bandgap semiconductor such as silicon carbide, the same effects can still be obtained.

[0281] <Regarding the effects produced by the above-described embodiment>

[0282] Next, examples of the effects produced by the above-described embodiment are shown. In addition, in the following description, the effects are described based on the specific structures illustrated in the above-described embodiment example, but they may also be replaced with other specific structures illustrated in the present application specification within the range where the same effects are produced.

[0283] In addition, this replacement may be performed across multiple embodiments. That is, it may also be a case where the same effects are produced by combining the respective structures illustrated in different embodiments.

[0284] According to the above-described embodiment, a silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a semiconductor layer of the first conductivity type, and a back electrode. Here, the silicon carbide semiconductor substrate corresponds to, for example, a silicon carbide single-crystal substrate 31 or the like. In addition, the semiconductor layer corresponds to, for example, an epitaxial growth layer 34 or the like. In addition, the back electrode corresponds to any one of a back electrode 20, a back electrode 320, a back electrode 520, and a back electrode 720 or the like (hereinafter, for convenience, any one of them may be correspondingly described). The epitaxial growth layer 34 is formed on the upper surface of the silicon carbide single-crystal substrate 31. The back electrode 20 is formed on the lower surface of the silicon carbide single-crystal substrate 31. Here, a region where a field-effect transistor is formed on the surface layer and the upper surface of the epitaxial growth layer 34 is defined as an active region 5. In addition, a region that surrounds the active region 5 in a top view is defined as a terminal region 6. In addition, a region where the resistivity between the silicon carbide single-crystal substrate 31 and the back electrode 20 is a first value is defined as a first resistance region. Here, the first resistance region corresponds to, for example, a low-resistance region 7 or the like. In addition, a region where the resistivity between the silicon carbide single-crystal substrate 31 and the back electrode 20 is a second value larger than the first value is defined as a second resistance region. Here, the second resistance region corresponds to, for example, a high-resistance region 8 or the like. Moreover, the high-resistance region 8 is a region that straddles the boundary between the active region 5 and the terminal region 6, that is, the region boundary, in a top view. Here, the region boundary corresponds to, for example, a boundary A.

[0285] According to such a structure, the high-resistance region 8 is provided in a range that straddles the boundary A between the active region 5 and the terminal region 6 in a plan view, so that it is possible to suppress a large current from being locally generated near the boundary A when the body diode of the SiC-MOSFET is conducting. Therefore, the productivity of the SiC-MOSFET is not reduced, and variations in the device characteristics of the SiC-MOSFET can be suppressed.

[0286] In addition, when other structures exemplified in the present specification are appropriately added to the above structure, that is, when other structures in the present specification that are not mentioned as the above structure are appropriately added, the same effect can also be obtained.

[0287] Further, according to the embodiment described above, when the total thickness of the silicon carbide single crystal substrate 31 and the epitaxial growth layer 34 is set to T, the distance Di in a plan view between the boundary A and the end portion of the high-resistance region 8 included in the active region 5 in a plan view satisfies T ≤ Di ≤ T × 10, and the distance Do in a plan view between the boundary A and the end portion of the high-resistance region 8 included in the terminal region 6 in a plan view satisfies T ≤ Do. According to such a structure, it is possible to effectively suppress a large current from being locally generated near the boundary A when the body diode of the SiC-MOSFET is conducting.

[0288] Further, according to the embodiment described above, the high-resistance region 8 is a region that extends over the entire region of the terminal region 6. According to such a structure, it is possible to suppress a large current from being locally generated near the boundary A when the body diode of the SiC-MOSFET is conducting.

[0289] Further, according to the embodiment described above, the contact resistivity between the silicon carbide single crystal substrate 31 and the back electrode 20 in the high-resistance region 8 is greater than the contact resistivity between the silicon carbide single crystal substrate 31 and the back electrode 20 in the low-resistance region 7. According to such a structure, it is possible to suppress a large current from being locally generated near the boundary A when the body diode of the SiC-MOSFET is conducting.

[0290] Further, according to the embodiment described above, in the high-resistance region 8, no ohmic contact is formed between the silicon carbide single crystal substrate 31 and the back electrode 20 (or the back electrode 520, the back electrode 720). According to such a structure, by relatively increasing the contact resistivity of the high-resistance region 8, it is possible to suppress a large current from being locally generated near the boundary A when the body diode of the SiC-MOSFET is conducting.

[0291] In addition, according to the embodiments described above, in the low-resistance region 7, an ohmic contact is formed by a silicide formed between the silicon carbide single-crystal substrate 31 and the back electrode 20 (or the back electrode 320, the back electrode 520). According to such a structure, by relatively reducing the contact resistivity of the low-resistance region 7, it is possible to suppress the locally generated large current near the boundary A when the body diode of the SiC-MOSFET is energized.

[0292] In addition, according to the embodiments described above, the silicon carbide semiconductor device includes an impurity region of a second conductivity type, which is formed on the surface layer on the lower surface side of the silicon carbide single-crystal substrate 31 and is disposed to overlap with the high-resistance region 8 in a plan view. Here, the impurity region corresponds to, for example, any one of the ion implantation region 40 and the ion implantation region 340. According to such a structure, by relatively increasing the contact resistivity of the high-resistance region 8, it is possible to suppress the locally generated large current near the boundary A when the body diode of the SiC-MOSFET is energized.

[0293] In addition, according to the embodiments described above, the ion implantation region 340 includes a first impurity layer and a second impurity layer having an impurity concentration different from that of the first impurity layer. Here, the first impurity layer and the second impurity layer correspond to, for example, any two of the ion implantation layers 40a, 40b, 40c, and 40d. According to such a structure, by relatively increasing the contact resistivity of the high-resistance region 8, it is possible to suppress the locally generated large current near the boundary A when the body diode of the SiC-MOSFET is energized. In addition, by dividing the impurity layer in the ion implantation region 340 into multiple stages, the current density in the epitaxial growth layer 34 can be precisely controlled.

[0294] In addition, according to the embodiments described above, the back electrode 720 includes a first metal layer disposed to overlap with the low-resistance region 7 and a second metal layer disposed to overlap with the high-resistance region 8 and containing a metal of a different type from the first metal layer. Here, the first metal layer corresponds to, for example, the back electrode layer 721. In addition, the second metal layer corresponds to, for example, the back electrode layer 722. According to such a structure, it is possible to effectively suppress the locally generated large current near the boundary A when the body diode of the SiC-MOSFET is energized.

[0295] In addition, according to the embodiments described above, the resistivity between the silicon carbide single-crystal substrate 31 and the back electrode 20 continuously changes from the low-resistance region 7 toward the high-resistance region 8. According to such a structure, it is possible to effectively suppress the locally generated large current near the boundary A when the body diode of the SiC-MOSFET is energized. In addition, the uniformity of the current density in the epitaxial growth layer 34 can be precisely controlled.

[0296] In addition, according to the embodiments described above, the silicon carbide semiconductor device includes a silicon carbide single crystal substrate 31, an epitaxial growth layer 34 formed on the upper surface of the silicon carbide single crystal substrate 31, and a back electrode 620 formed on a part of the lower surface of the silicon carbide single crystal substrate 31. Here, the region where the field effect transistor is formed on the surface layer and the upper surface of the epitaxial growth layer 34 is defined as the active region 5. In addition, the region surrounding the active region 5 in a top view is defined as the terminal region 6. In addition, the region where the back electrode 620 is formed in a top view is defined as the first region. Here, the first region corresponds to, for example, the low resistance region 7 or the like. In addition, the region where the back electrode is not formed in a top view is defined as the second region. Here, the second region corresponds to, for example, the high resistance region 8 or the like. Moreover, the high resistance region 8 is a region that straddles the boundary A, which is the boundary between the active region 5 and the terminal region 6, in a top view.

[0297] According to such a structure, the high resistance region 8 where the back electrode 620 is not formed is provided in a range that straddles the boundary A between the active region 5 and the terminal region 6 in a top view, so that it is possible to suppress the local generation of a large current near the boundary A when the body diode of the SiC-MOSFET is energized. Therefore, the productivity of the SiC-MOSFET is not reduced, and the variation in the element characteristics of the SiC-MOSFET can be suppressed.

[0298] In addition, according to the embodiments described above, when the total thickness of the silicon carbide single crystal substrate 31 and the epitaxial growth layer 34 is set to T, the distance Di in a top view between the boundary A and the end portion of the high resistance region 8 included in the active region 5 in a top view satisfies T ≤ Di ≤ T × 10, and the distance Do in a top view between the boundary A and the end portion of the high resistance region 8 included in the terminal region 6 in a top view satisfies T ≤ Do. According to such a structure, it is possible to effectively suppress the local generation of a large current near the boundary A when the body diode of the SiC-MOSFET is energized.

[0299] In addition, according to the embodiments described above, the high resistance region 8 is a region that extends throughout the entire terminal region 6. According to such a structure, it is possible to suppress the local generation of a large current near the boundary A when the body diode of the SiC-MOSFET is energized.

[0300] In addition, according to the embodiments described above, the power conversion device includes: a conversion circuit 2201, which has the above-mentioned silicon carbide semiconductor device and converts the input power for output; a drive circuit 2202, which outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; and a control circuit 2203, which outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202. According to such a structure, the high-resistance region 8 is provided in a range that straddles the boundary A between the active region 5 and the terminal region 6 in a top view, so it is possible to suppress the local generation of a large current near the boundary A when the body diode of the SiC-MOSFET is energized. Therefore, the productivity of the SiC-MOSFET is not reduced, and the variation in the device characteristics of the SiC-MOSFET can be suppressed.

[0301] <Regarding the modification examples of the embodiments described above>

[0302] In the embodiments described above, the materials, materials, dimensions, shapes, relative arrangement relationships, or implementation conditions of each component may sometimes be described, but these are examples in all embodiments and are not limiting.

[0303] Therefore, within the scope of the technology disclosed in this application specification, countless modification examples and equivalents that are not illustrated are envisioned. For example, it includes cases where at least one component is deformed, added, or omitted, and further cases where at least one component in at least one embodiment is extracted and combined with the components in other embodiments.

[0304] In addition, in the embodiments described above, when the material name or the like is described without special designation, as long as there is no contradiction, it includes, for example, alloys and the like that contain other additives in the material.

[0305] In addition, as long as there is no contradiction, a component described as having "one" in the embodiments described above may also have "more than one".

[0306] Furthermore, each component in the embodiments described above is a conceptual unit, and within the scope of the technology disclosed in this application specification, it includes cases where one component is composed of multiple structures, cases where one component corresponds to a part of a certain structure, and further cases where multiple components are provided in one structure.

[0307] In addition, among the components in the embodiments described above, as long as they perform the same function, it includes structures having other structures or shapes.

[0308] In addition, the descriptions in this application specification are for all purposes related to this technology and should not be regarded as prior art.

[0309] In addition, in the above described embodiments, a planar MOSFET is described, but it is also conceivable that the present invention is applied to a trench MOSFET in which a groove is formed on the upper surface of the drift layer. In the case of the trench MOSFET, a groove portion, i.e., a trench, is formed on the upper surface of the drift layer, and a gate electrode is buried in the groove portion. The gate electrode is buried between the bottom surface and the side surface of the trench via a gate insulating film.

Claims

1. A silicon carbide semiconductor device comprising: A silicon carbide semiconductor substrate of a first conductivity type; A semiconductor layer of the first conductivity type formed on the upper surface of the silicon carbide semiconductor substrate; and A back electrode formed on the lower surface of the silicon carbide semiconductor substrate, The region where a field effect transistor is formed on the surface layer and the upper surface of the semiconductor layer is set as an active region, The region that surrounds the active region in a top view is set as a terminal region, The region where the resistivity between the silicon carbide semiconductor substrate and the back electrode is a first value is set as a first resistance region, The region where the resistivity between the silicon carbide semiconductor substrate and the back electrode is a second value greater than the first value is set as a second resistance region, The second resistance region is a region that straddles the boundary between the active region and the terminal region, i.e., the region boundary, in a top view.

2. The silicon carbide semiconductor device according to claim 1, wherein, When the total thickness of the silicon carbide semiconductor substrate and the semiconductor layer is set as T, The distance Di in a top view between the region boundary and the end portion of the second resistance region included in the active region in a top view satisfies T ≤ Di ≤ T × 10, and The distance Do in a top view between the region boundary and the end portion of the second resistance region included in the terminal region in a top view satisfies T ≤ Do.

3. The silicon carbide semiconductor device according to claim 1, wherein, The second resistance region is a region that extends throughout the entire region of the terminal region.

4. The silicon carbide semiconductor device according to claim 2, wherein, The second resistance region is a region that extends throughout the entire region of the terminal region.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, The contact resistivity between the silicon carbide semiconductor substrate and the back electrode in the second resistance region is greater than the contact resistivity between the silicon carbide semiconductor substrate and the back electrode in the first resistance region.

6. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, In the second resistance region, no ohmic contact is formed between the silicon carbide semiconductor substrate and the back electrode.

7. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, In the first resistance region, an ohmic contact is formed by a silicide formed between the silicon carbide semiconductor substrate and the back electrode.

8. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, It further includes an impurity region of a second conductivity type, and this impurity region of the second conductivity type is formed on the surface layer on the lower surface side of the silicon carbide semiconductor substrate and is disposed to overlap with the second resistance region in a top view.

9. The silicon carbide semiconductor device according to claim 8, wherein, The impurity region includes: A first impurity layer; and A second impurity layer with an impurity concentration different from that of the first impurity layer.

10. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, The back electrode includes: a first metal layer provided to overlap with the first resistance region; and a second metal layer provided to overlap with the second resistance region and including a metal of a type different from that of the first metal layer.

11. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein from the first resistance region toward the second resistance region, the resistivity between the silicon carbide semiconductor substrate and the back electrode changes continuously.

12. A silicon carbide semiconductor device includes: a silicon carbide semiconductor substrate; a semiconductor layer formed on the upper surface of the silicon carbide semiconductor substrate; and a back electrode formed on a part of the lower surface of the silicon carbide semiconductor substrate, wherein a region where a field effect transistor is formed on the surface layer and the upper surface of the semiconductor layer is set as an active region, a region that surrounds the active region in a plan view is set as a terminal region, a region where the back electrode is formed in a plan view is set as a first region, a region where the back electrode is not formed in a plan view is set as a second region, and the second region is a region that straddles a boundary between the active region and the terminal region, i.e., a region boundary, in a plan view.

13. The silicon carbide semiconductor device according to claim 12, wherein when the total thickness of the silicon carbide semiconductor substrate and the semiconductor layer is set as T, a distance Di in a plan view between the region boundary and an end portion of the second region included in the active region in a plan view satisfies T ≤ Di ≤ T × 10, and a distance Do in a plan view between the region boundary and an end portion of the second region included in the terminal region in a plan view satisfies T ≤ Do.

14. The silicon carbide semiconductor device according to claim 12 or 13, wherein the second region is a region that extends over the entire region of the terminal region.

15. A power conversion device includes: a conversion circuit having the silicon carbide semiconductor device according to any one of claims 1 to 14, and the conversion circuit converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

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