Wireless BMS host time synchronization mechanism

Abstract

This article describes a wireless battery management system (BMS) and host controller associated with low-cost time synchronization. The time synchronization technique described herein is low-cost because it uses existing communication lines rather than additional dedicated lines or wires for synchronization. Furthermore, the time synchronization technique described herein can be implemented without complex circuitry.

Description

[0001] Claim priority

[0002] This patent application claims priority to U.S. patent application serial number 17 / 222,681, filed on April 5, 2021, entitled “Wireless BMS Host Time Synchronization Mechanism,” which claims priority to U.S. provisional patent application serial number 63 / 033,396, filed on June 2, 2020, entitled “Wireless BMS Host Time Synchronization Mechanism,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to wireless battery management systems (BMS), and more particularly to time synchronization with a host system. Background Art

[0004] Electric vehicles are becoming increasingly popular. One factor driving their adoption is improvements in battery management. Electric vehicles can monitor battery charge and quickly and accurately communicate this information to their control units. With timely and accurate battery charge information, electric vehicles can operate more reliably and efficiently.

[0005] Some BMSs include a wired network (sometimes called a "daisy chain"), where battery monitors are connected to the manager via wired connections. However, wiring in electric vehicles comes at a cost, and each wire presents its own reliability issues. Consequently, wireless BMSs have recently been introduced. However, using wireless communication in a BMS can present its own challenges. For example, a wireless BMS typically operates using its own network clock, while the vehicle's control system uses its own clock. Therefore, if these two clocks are out of sync, data can be lost or corrupted. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various figures in the drawings depict only exemplary embodiments of the present disclosure and should not be considered as limiting its scope.

[0007] Figure 1A A block diagram of a wireless BMS according to an example of the present invention is shown.

[0008] Figure 1B Timing synchronization of a wireless BMS according to an example of the present invention is shown.

[0009] Figure 2 Timing messages according to an example of the present invention are shown.

[0010] Figure 3 A flow chart of a method for sending a timing message according to an example of the present invention is shown.

[0011] Figure 4A flow chart of a method for synchronizing timing of WBMS managers according to an example of the present invention is shown.

[0012] Figure 5 An example of an isolated SPI system according to an example of the present invention is shown. DETAILED DESCRIPTION

[0013] The inventors have recognized, among other things, a need for low-cost time synchronization of wireless battery management systems (BMS) and host controllers, as described herein. The time synchronization techniques described herein are low-cost because existing communication lines are used for synchronization without requiring additional dedicated lines or wires. Furthermore, the time synchronization techniques described herein can be implemented without complex circuitry.

[0014] The present invention describes a method for synchronizing timing between a host controller and a wireless manager. The method may include: detecting a timing mismatch between the host controller and the wireless manager at a host controller; sending a unique word to the wireless manager in response to detecting the timing mismatch; obtaining a master timestamp from a clock at the host controller; and sending the master timestamp to the wireless manager.

[0015] The present invention also describes a method for synchronizing the timing of a wireless manager. The method may include: detecting, at the wireless manager, a unique word received from a host controller; receiving a master timestamp from the host controller; and adjusting the timing of a clock at the wireless manager based on the master timestamp.

[0016] The present invention also describes a system comprising: a host controller including a host clock, a wireless manager including a local clock, and a communication interface between the host controller and the wireless manager. The host controller may include circuitry configured to: in response to detecting a timing mismatch between the host and local clocks, send a unique word to the wireless manager; obtain a master timestamp from the host clock; and send the master timestamp to the wireless manager; the wireless manager may include circuitry configured to: receive the unique word from the host controller; receive a master timestamp from the host controller based on the master timestamp; and adjust the timing of the local clock.

[0017] Figure 1A 1 is a block diagram of a wireless BMS 100 according to an example of the present invention. The wireless BMS 100 may include a plurality of BMS monitors 102.1-102.n coupled to respective WBMS nodes 104.1-104n. The wireless BMS 100 may also include a WBMS manager 106, a host controller 108, and an electronic control unit (ECU) 110.

[0018] Each of the multiple BMS monitors 102.1-102.n can monitor a corresponding battery module. The BMS monitors 102.1-102.n can be provided as integrated circuits. Such integrated circuits can include monolithic BMS circuitry or integrated modules comprising multiple integrated circuit dies or other circuit components within a shared integrated circuit device package, as described in the example. The BMS monitors 102.1-102.n can sample the corresponding battery cell voltage to monitor the battery level. The monitors 102.1-102.n can also monitor the current and temperature of each battery module.

[0019] Each BMS monitor 102.1-102.n can be coupled to a corresponding WBMS node 104.1-104.n via a communication interface (e.g., via a serial peripheral interface (SPI) or the like). Each pair of BMS monitors 102.1-102.n and WBMS nodes 104.1-104.n can be provided on a single printed circuit board (PCB). The WBMS nodes can include corresponding radio transceivers to transmit battery measurements to the WBMS manager via a wireless network.

[0020] As shown, multiple BMS monitors 102.1-102.n can be provided. Each BMS monitor 102.1 can monitor a separate battery module. For example, multiple BMS monitors 102.1-102.n can be installed in an electric vehicle, each monitoring a unique battery module in the electric vehicle. Each BMS monitor 102.1-102.n can be equipped with its own WBMS node 104.1-104.n. Each WBMS node 104.1-104.n can communicate with the WBMS manager 106 via a wireless network. For example, the wireless network can be provided as a mesh network, etc.

[0021] Figure 1B The figure illustrates timing synchronization of a wireless BMS 100 according to an example of the present invention. A WBMS manager 106 and multiple WBMS nodes 104.1-104.n can synchronize their clocks based on the WBMS network time. For example, the WBMS manager 106 can include a local clock, such as a local crystal oscillator, which can serve as the master clock for the wireless network. The local clocks of the WBMS nodes 104.1-104.n can be synchronized with the clock of the WBMS manager 106 according to a network protocol.

[0022] The WBMS manager 106 may be coupled to the host controller 108 via a communication interface (e.g., via SPI). The host controller 106 may be provided as a microcontroller, a microprocessor, or the like. The WBMS manager 106 and the host controller 108 may be provided together on a single PCB. The host controller may be coupled to the ECU 110 via a wired connection such as a controller area network (CAN) bus.

[0023] Each BMS monitor 102.1-102.n and coupled WBMS node 104.1-104.n can measure the battery charge (e.g., voltage, current, temperature, etc.) of its corresponding battery module and send the measured values ​​to the WBMS manager 106 on a regular basis (e.g., every 100 milliseconds). The WBMS manager 106 can receive the battery measurements from the different WBMS nodes 104.1-104.n and can communicate the measurements to the host controller 108. The host controller 108 can, in turn, transmit information about the measured battery charge to the ECU 108. The host controller 108 can include a data buffer to collect the battery measurement information and send the information to the ECU 110.

[0024] Based on the battery measurement information, the ECU 110 can control the operation of the electric vehicle accordingly. For example, based on the battery measurement information, the ECU 110 can calculate the range of the battery, detect problems with the battery module, and so on.

[0025] The host controller 106 may include its own clock, such as a reference local oscillator, such as a local crystal oscillator. The clocks of the host controller 106 and the ECU 108 may be synchronized. For example, the host controller 106 may synchronize its clock with the clock of the ECU 108. However, the clocks of the WBMS manager 106 and the host controller 108 may be independent of each other. Therefore, if the clocks of the WBMS manager 106 and the host controller 108 drift and become misaligned, data may be lost or corrupted.

[0026] To this end, the host controller 108 can synchronize the WBMS manager 106's clock with its clock using a timing message (e.g., "HOST2MGR TIME INPUT"). For time synchronization purposes, the host controller 108 can operate as a master controller, and the WBMS manager 106 can operate as a slave controller. The host controller 108 can generate and send a timing message when it detects a timing mismatch between its clock and the WBMS manager 106's clock (e.g., a time desynchronization event). For example, the timing mismatch can be detected based on the state of a data buffer used by the host controller 108 to send battery measurement information to the ECU 110.

[0027] Furthermore, over time, the WBMS manager 106 clock may drift relative to the host controller 108 clock. If the magnitude of the error associated with this drift becomes greater than the buffer size or some other threshold, the buffer may overflow and release old data before it is transmitted to the ECU 110, resulting in data loss or corruption. In another illustrative example, if the drifting error reduces the frequency of the clock, the rate or margins of the data in the buffer may also be affected, causing one or more buffers to underflow or possible data corruption. Therefore, either a buffer overflow or a buffer underflow may indicate a timing mismatch.

[0028] Figure 2 2 shows an example timing message 200 according to the present invention. As discussed herein, when a time desynchronization event is detected, the timing message 200 may be sent by the host controller 108 to the WBMS manager 106, as described above with reference to FIG. Figures 1A-1B As stated.

[0029] Furthermore, as discussed herein, the host controller 106 and the WBMS manager 108 can communicate using a communication interface such as SPI. In an SPI bus, there are four logic lines: SCLK – Serial Clock; MOSI – Master Output Slave Input; MISO – Master Input Slave Output; and CS – Chip / Slave Select.

[0030] Timing message 200 can be sent on the MOSI logic line of the SPI bus. Host controller 108 can operate as a master controller, and WBMS manager 106 can operate as a slave controller. As described herein, using the MOSI logic line to transmit timing messages provides the benefit of not using additional wires for time synchronization.

[0031] The timing message 200 may include two parts: 1) a unique sync word 202 and 2) a master timestamp 204. The unique sync word 202 of the timing message 200 may immediately follow the master timestamp 204. Thus, receipt of the unique sync word 202 may alert or notify the WBMS manager 106 of the upcoming master timestamp 204. The unique sync word 202 may have a fixed bit setting. The unique sync word 202 may have a fixed pattern. Thus, the WBMS manager 106 may be programmed to detect the unique sync word 202.

[0032] The master timestamp 204 may be a timestamp indicating the timing of the clock signal of the host controller 108. The master timestamp may be acquired at the instant when the last bit of the unique synchronization word 202 is transmitted.

[0033] Figure 31 is a flow chart showing a method 300 for sending a timing message according to an example of the present invention. The method 300 may be performed by the host controller 108, as described above with reference to Figures 1A-1B In addition, as mentioned above Figure 2 As described herein, the time message may be provided as a timing message 200. Initially, the host controller 108 may detect the occurrence of a time desynchronization event. At 302, as described herein, the host controller 108 may detect whether the buffer is in an overflow state or an underflow state. If the host controller 108 detects either state, the host controller 108 may send a timing message 200 to synchronize the clock of the WBMS manager 106 with its own clock. At 304, the host controller 108 may send a unique synchronization word 200 to the WBMS manager 106 via a communication interface (e.g., the MOSI line in an SPI bus). At 306, the host controller 108 may also obtain a timestamp of its clock, referred to as the master timestamp 204, at the instant the last bit of the unique synchronization word 202 was sent. At 308, the host controller 108 may send the master timestamp information to the WBMS manager via the communication interface (e.g., the MOSI line in an SPI bus). Method 300 may then return to monitoring the status of the buffer (e.g., step 302).

[0034] Figure 4 4. A flowchart 400 is shown of a method for synchronizing timing of WBMS managers according to an example of the present invention. The method 400 may be performed by the WBMS manager 106, as described above with reference to FIG. Figures 1A-1B In addition, the time message can be provided as a timing message 200, as described above with reference to Figure 2 As stated.

[0035] At 402 , the WBMS manager may detect a unique synchronization word 202 in a received data stream from the host controller 108 , such as on the MOSI line in an SPI bus. The WBMS manager 106 may detect a fixed pattern or set of bits that represent the unique synchronization word 202 .

[0036] If a unique sync word 202 is detected, then at 404, the WBMS manager can obtain the timestamp of its own clock at the moment the last bit of the unique sync word 202 is received, called the slave timestamp. At 406, the WBMS manager 1065 can then read the master timestamp information 204 received after the unique sync word 202 from the host controller through the communication interface. At 408, the WBMS manager 108 can compare its slave timestamp with the received master timestamp. Both timestamps are relative to the last bit of the unique sync word being sent / received. Based on the comparison of the two timestamps, if drift is detected, the WBMS manager 106 can adjust its timing (e.g., WBMS network time) to synchronize its time with the time of the host controller 108. The WBMS manager 106 can then synchronize the WBMS nodes (e.g., as described above with reference to Figures 1A-1B The timing of the described WBMS nodes 104.1-104.n) (referred to as network time) is synchronized with the timing of the WBMS nodes so that the WBMS nodes can also be synchronized with the timing of the host controller.

[0037] For illustration purposes, the above synchronization technique is described using SPI between the WBMS manager and the host controller; other interfaces may also be employed. For example, the WBMS manager and the host controller may be provided on separate PCBs and they may be coupled using isolated SPI.

[0038] Figure 5 An example of an isolated SPI system 500 according to an example of the present invention is shown. System 500 can include a master node 502 having a master converter chip 504 and multiple slave nodes 506-1, 506.2 having corresponding converter chips 508.1, 508.2. Each node (master or slave) can include a converter chip, and the converter chip can include an SPI interface with its four logic lines (MOSI, MISO, SCLK, CS), and convert the signals from the SPI interface to an ISO SPI interface via differential pair conductors 510 (IP, IM). In another example, a universal asynchronous receiver-transmitter (UART) interface can also be used with the synchronous techniques described herein.

[0039] Furthermore, in one example, the WBMS manager can be integrated with a host controller. In this example, the synchronization techniques described herein can be used between the timing of the integrated WBMS manager / host controller and the ECU, where the timing of the integrated WBMS manager / host controller can be synchronized with the timing of the ECU.

[0040] Various annotations

[0041] Each of the above-described non-limiting aspects may stand alone or may be combined in various permutations or combinations with one or more of the other aspects or other subject matter described in this document.

[0042] The above detailed description includes references to the accompanying drawings that form part of the detailed description. The accompanying drawings illustrate specific embodiments in which the present invention can be put into practice. These implementations are also generally referred to as "examples". Such examples may include elements other than those shown or described. However, the inventors have also considered examples that only provide those elements shown or described. In addition, the inventors have also considered examples using any combination or arrangement of those elements shown or described (or one or more aspects thereof), which may be with respect to a specific example (or one or more aspects thereof) or with respect to other examples shown or described herein (or one or more aspects thereof).

[0043] In the event of a conflicting usage between this document and any document incorporated by reference, the usage in this document controls.

[0044] In this document, the terms "a" or "an," as are common in patent documents, include one or more, independent of any other instance or usage of "at least one" or "one or more," and unless otherwise stated, "A or B" includes "A but not B," "B but not A," and "A and B." In this document, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "in...". Furthermore, in the following claims, the terms "including" and "comprising" are open-ended, i.e., systems, devices, articles, compositions, formulations, or processes that include elements other than the elements listed after such terms in a claim are still considered to fall within the scope of the claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0045] The method examples described herein may be at least partially implemented by a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions that are operable to configure an electronic device to perform the methods described in the above examples. The implementation of such methods may include code, such as microcode, assembly language code, higher-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, in one example, the code may be tangibly stored on one or more volatile, non-transitory or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical disks and digital video disks), cassette tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0046] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other implementations may be used, such as by those of ordinary skill in the art when reviewing the above description. An abstract is provided to allow the reader to quickly determine the nature of the technical disclosure. It is submitted with the understanding that this application will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be interpreted as intending that unclaimed disclosed features are essential to any claim. On the contrary, the subject matter of the present invention may not lie in all features of a particular disclosed implementation. Therefore, the following claims are incorporated into the detailed description as examples or embodiments, wherein each claim exists independently as a separate embodiment, and it is expected that these embodiments may be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the appended claims and all equivalent scopes to which these claims have.

Claims

1. A method for synchronizing timing between a host controller and a wireless manager, the method comprising: detecting, at a host controller, a timing mismatch between the host controller and the wireless manager; as well as In response to detecting the timing mismatch: sending a unique word comprising a fixed bit pattern to the wireless manager using a common data line in the communication interface; obtaining a master timestamp from a clock at the host controller at the instant a specific bit in the fixed bit pattern of the unique word is transmitted; and The master timestamp is sent to the wireless manager using a common data line in the communication interface.

2. The method of claim 1, wherein the specific bit is the last bit of the unique word.

3. The method of claim 1 , wherein the communication interface comprises a serial peripheral interface (SPI), and wherein the unique word is sent via a master output slave input MOSI line of the SPI. The method of claim 3 , wherein the communication interface comprises an isolated SPI.

5. The method according to claim 1, further comprising: A buffer overflow condition is detected, the buffer overflow condition indicating the timing mismatch.

6. The method according to claim 1, further comprising: A buffer underflow condition is detected, the buffer underflow condition being indicative of the timing mismatch.

7. A non-transitory machine-readable medium embodying instructions that, when executed by a machine, cause the machine to perform operations comprising: detecting, at a host controller, a timing mismatch between the host controller and a wireless manager; and In response to detecting the timing mismatch: sending a unique word comprising a fixed bit pattern to the wireless manager using a common data line in the communication interface; deriving a master timestamp from a clock at the host controller at the instant a specific bit in the fixed bit pattern of the unique word is transmitted; and The master timestamp is sent to the wireless manager using a common data line in the communication interface.

8. The non-volatile machine-readable medium of claim 7, wherein the specific bit is a last bit of the unique word.

9. The non-volatile machine-readable medium of claim 7, wherein the communication interface comprises a serial peripheral interface (SPI), and wherein the unique word is sent via a master output slave input (MOSI) of the SPI.

10. The non-transitory machine-readable medium of claim 9, wherein the communication interface comprises an isolated SPI.

11. The non-transitory machine-readable medium of claim 7, wherein the operations further comprise: A buffer overflow condition is detected, the buffer overflow condition indicating the timing mismatch.

12. The non-transitory machine-readable medium of claim 7, wherein the operations further comprise: A buffer underflow condition is detected, the buffer underflow condition being indicative of the timing mismatch.

13. A system for synchronizing timing between a host controller and a wireless manager, comprising: The host controller includes a host clock; The wireless manager includes a local clock; a communication interface between the host controller and the wireless manager, wherein the host controller includes circuitry configured to, in response to detecting a timing mismatch between the host clock and the local clock: sending a unique word comprising a fixed bit pattern to the wireless manager using a common data line in the communication interface; obtaining a master timestamp from the host clock at the instant a specific bit in the fixed bit pattern of the unique word is transmitted; and sending the master timestamp to the wireless manager using a common data line in the communication interface; The wireless manager includes circuitry configured to: receiving the unique word from the host controller; obtaining a slave timestamp from a local clock at the wireless manager at the instant of receiving the specific bit of the unique word; receiving the master timestamp from the host controller; and The timing of the local clock is adjusted based on the master timestamp and the slave timestamp. The system of claim 13 , wherein the specific bit is a last bit of the unique word.

15. The system of claim 13 or 14, wherein the communication interface comprises a serial peripheral interface (SPI), and wherein the unique word is sent from an input MOSI line via a master output of the SPI.

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