Improved Vertical 3D Memory Device and Access Method

Abstract

This application relates to an improved vertical 3D memory device and access method. The present disclosure provides a memory device and its access / deselect method. The memory device includes: a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein the memory cells are accessed via word lines and digit lines orthogonal to each other, and the digit lines are in the form of vertically extending conductive pillars; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing the memory cells; and a peripheral circuit layer formed under the pillar selection layer and having sense amplifiers and decoding circuitry for the word lines and bit lines, wherein a TFT is configured for each pillar.

Description

[0001] Cross-reference

[0002] This patent application is a national stage application of International Patent Application No. PCT / IB2020 / 020028, titled "Improved Vertical 3D Memory Device and Accessing Method", filed by VILLA et al. on May 25, 2020, which is assigned to the assignee hereof and the entire text thereof is hereby incorporated by reference in its entirety.

[0003] The technical field relates to an improved vertical 3D memory device and accessing method. Background Art

[0004] The following disclosure generally relates to the field of electronic devices and, more particularly, to an improved vertical 3D (three-dimensional) memory device structure and an associated accessing method.

[0005] Electronic memory devices (hereinafter simply referred to as "memory devices") are widely used to store data in various electronic devices such as tablet computers, computers, wireless communication devices (e.g., smart phones), cameras, digital displays, and the like.

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most commonly store one of two states often represented by logic 1 or logic 0. In other devices, more than two states may be stored. To access the stored information, components of the device may read or sense at least one of the stored states in the memory device. To store information, components of the device may write or program a state in the memory device.

[0007] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), other chalcogenide-based memories, and other memory devices. Memory devices can be volatile or non-volatile.

[0008] Generally, improving a memory device may include increasing memory cell density, improving read / write speed, enhancing reliability, extending data retention, reducing power consumption, or reducing manufacturing cost, among other metrics. Solutions may be needed to save space in a memory array, increase memory cell density, or reduce the overall power usage of a memory array having a three-dimensional vertical architecture.

[0009] The object of the present disclosure is to provide an improved memory device having additional select elements, and an efficient method for accessing memory cells of the memory device. SUMMARY OF THE INVENTION

[0010] A memory device is described. In some instances, the memory device may include: a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein the memory cells are configured to be accessed via a word line and a digit line that are orthogonal to each other, and the digit line is in the form of a vertically extending conductive pillar; a pillar selection layer formed under the memory layer, and having at least one thin film transistor (TFT) formed therein for accessing the memory cells; and a peripheral circuit layer formed under the pillar selection layer, and having sense amplifiers and decoding circuitry for the word line and the bit line, wherein a TFT is configured for each pillar.

[0011] A memory device is described. In some instances, the memory device may include: a memory array of memory cells structured as a vertical 3D memory, including a plurality of word lines configured to be orthogonal to a plurality of digit lines, each digit line intersecting at least one pair of word lines; and at least one select transistor located at one end of a corresponding digit line, the select transistor being a thin film transistor (TFT) for selecting the corresponding digit line and accessing at least the memory cells associated with the corresponding digit line.

[0012] A method for accessing memory cells of a memory device is described. In some instances, the method may include: applying a first voltage to a selected word line while other word lines are at a predetermined voltage; applying a second voltage to the gate region of a TFT associated with other memory cells sharing the selected word line with the memory cell; applying the second voltage to the source region of the TFT associated with the memory cell sharing the selected word line while the source regions of other TFTs are at the predetermined voltage; and applying a third voltage to the gate region of the TFT associated with the memory cell.

[0013] Disclosed is a method for deselecting unaddressed memory cells in a 3D memory array, where multiple word lines extend horizontally over multiple stacks and multiple array digit lines extend vertically, and each memory cell is located at the intersection of a word line and an array digit line. In some instances, the method may include floating the array digit lines among the multiple array digit lines that are coupled to the unaddressed memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Illustrates an example memory array supporting a vertical 3D memory device with NMOS TFT selectors, according to an example as disclosed herein.

[0015] Figures 2A to 2F Illustrates various views of an example memory array supporting a vertical 3D memory device with NMOS TFT selectors, according to an example as disclosed herein.

[0016] Figures 3A to 3I Illustrates various views of an example memory array supporting a vertical 3D memory device with NMOS TFT selectors, according to an example as disclosed herein.

[0017] Figure 4A AND 4B Illustrates various views of another example memory array supporting a vertical 3D memory device with NMOS TFT selectors, according to an example as disclosed herein.

[0018] Figure 5 Illustrates another example memory array supporting a vertical 3D memory device with NMOS TFT selectors, according to an example as disclosed herein.

[0019] Figure 6 Illustrates an example NMOS TFT, according to an example as disclosed herein.

[0020] Figures 7A to 7C Illustrates various views of an example NMOS TFT selector, according to an example as disclosed herein.

[0021] Figures 8A to 8D Illustrates various diagrams for accessing memory cells of a vertical 3D memory device with NMOS TFT selectors, according to an example as disclosed herein.

[0022] Figure 9 Shows a flow diagram illustrating a method for accessing a vertical 3D memory device with NMOS TFT selectors, according to an example as disclosed herein. DETAILED DESCRIPTION

[0023] The present disclosure relates to a vertical 3D memory device having NMOS TFT selectors, and a method of accessing the same. The memory device may include: a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, where the memory cells are accessed via word lines and digit lines orthogonal to each other, and the digit lines are in the form of vertically extending conductive pillars; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing the memory cells; and a peripheral circuit layer formed under the pillar selection layer and having sense amplifiers and decoding circuitry for the word lines and bit lines, where a TFT is configured for each pillar. In some cases, the TFT is an n-type metal oxide semiconductor (NMOS) transistor, where the drain region is coupled to the pillar. In some cases, the channel region of the TFT extends to a first predetermined value. In some cases, the TFT has two gate regions parallel to a gate oxide on one side of the channel region and another gate oxide on the other side of the channel region. In some cases, the channel region is formed under the drain region, and the source region is formed under the channel region. In some cases, the length of the channel region is extended to a second predetermined value. In some cases, the first predetermined value is 120 nm. In some cases, the second predetermined value is 220 nm. In some cases, the conductive pillar further includes a first sub-pillar and a second sub-pillar separated from each other, and two TFTs are configured for the conductive pillar, where one is for the first sub-pillar and the other is for the second sub-pillar. In some cases, the pitch of the TFTs matches the pitch of the pillars.

[0024] In some instances, a matrix of thin film transistors (TFTs) is provided under and / or above the digit lines, where one transistor per digit line, and a peripheral circuit system having sense amplifiers and decoding circuitry for the word lines and bit lines is formed under the matrix.

[0025] Thus, the matrix of thin film transistors is formed in a polysilicon layer, and the peripheral circuit layer is implemented in a silicon substrate layer; in some instances, the peripheral circuit layer may be located under the polysilicon layer, and the polysilicon layer may be located under the 3D memory array.

[0026] In some instances, the memory device may include an arrangement of conductive contacts and openings through alternating layers of conductive and insulating materials, which may reduce the pitch between the memory cells while maintaining a dielectric thickness to hold the voltage to be applied to the memory array of the memory device, and the memory device may further include a select transistor coupled to each conductive contact, which is the NMOS TFT for implementing decoding of the vertical 3D memory device.

[0027] In some instances, the memory device may include a substrate having a set of contacts arranged in a pattern (e.g., a geometric pattern) and a first insulating material (e.g., a dielectric material) formed on the substrate. A set of planes of conductive material may be separated from one another by a second insulating material (e.g., a dielectric material) and formed on the substrate material. That is, alternating planes of conductive material and insulating material may be formed on the substrate. The planes of conductive material may be examples of word lines.

[0028] During the fabrication of the memory device, one or more trenches may be formed by etching the alternating planes of conductive material and insulating material. The trenches may extend parallel to one another and expose the substrate. In some instances, the planes of conductive material and dielectric material may form the sidewalls of the trenches. The planes of conductive material may be etched in such a way that the dielectric material and the planes of conductive material form a set of recesses, where each recess may be configured to receive a memory element material (e.g., a chalcogenide material). A sacrificial layer (e.g., a conformal material) may be deposited in the trenches, and in some cases, the sacrificial layer fills the recesses. An insulating material may be deposited in the trenches on top of the sacrificial layer.

[0029] The sacrificial layer and portions of the insulator may be removed to form a first opening. The first opening may expose portions of the substrate, at least some of the set of conductive contacts, and portions of the planes of conductive material and dielectric material. A memory element material (e.g., a chalcogenide material) may be deposited in the first opening. The memory element material may fill the recesses formed by the planes of dielectric material and conductive material. The memory element material may be partially removed from the first opening such that the memory element material in the recesses is retained. The memory element material positioned in the recesses may be a memory element assembly (e.g., a chalcogenide assembly).

[0030] Conductive pillars may be formed in the first opening that includes the memory assemblies in the recesses. The conductive pillars may be arranged to extend through the planes of conductive material (e.g., generally perpendicular to the planes of conductive material) and contact the substrate. Each conductive pillar may contact two memory element assemblies, and the two memory element assemblies each contact the same plane of conductive material. Each conductive pillar may further be coupled to one or two conductive contacts, and thus an NMOS TFT may be associated with each conductive pillar. In some cases, the pillars may be formed of a barrier material and a conductive material. In some cases, a single NMOS TFT may be provided for each pillar.

[0031] A portion of the removable conductive pillar is formed to create a second opening. The second opening may divide each pillar into a first pillar and a second pillar. The first and second pillars may be examples of digit lines. The first pillar may contact-couple to a first memory element assembly of a plane of conductive material, and the second pillar may contact-couple to a second memory element assembly of a plane of conductive material. In some cases, each of the first pillar and the second pillar may couple to different conductive contacts on the substrate. In some other cases, each of the first pillars may couple to different conductive contacts on the substrate, and each of the second pillars may couple to different conductive contacts on a second substrate formed above the first substrate. In some cases, each of the first pillar and the second pillar may be associated with a respective NMOS TFT. In other words, one pillar may be coupled with a single NMOS TFT.

[0032] In some cases, the NMOS TFTs may be formed below the array of memory cells, specifically, below each pillar. In some cases, the drain region of the NMOS TFT may be coupled to the pillar. In some cases, the active region (i.e., polysilicon channel) of the NMOS TFT may extend to a predetermined value (e.g., 120 nm). In some cases, the NMOS TFT may have two gate regions, having a gate oxide on one side of the channel region and another gate oxide on the other side of the channel region, thereby doubling the width of the NMOS TFT. In some cases, a first bottom silicon layer of the memory device may be dedicated to sense amplifiers and decoding circuitry for word lines and bit lines. In some cases, above the first silicon layer, an epitaxial growth of polysilicon may be provided, and in this polysilicon layer, NMOS TFTs may be provided as a matrix below the pillars.

[0033] The present disclosure further relates to a method for accessing memory cells of a vertical 3D memory device having NMOS TFT selectors. Generally speaking, the cells of a 3D memory array may be addressed by word lines and bit lines. To address a target cell, a positive bias voltage may be applied to a digit line (which may be a vertical portion of a bit line), and a negative bias voltage may be applied to a word line plate. However, the word lines receiving the negative bias voltage may be shared with all other cells associated with the same word line plate and linked to other pillars (i.e., vertical portions of bit lines). Therefore, it is necessary to determine the desired bit line.

[0034] It is possible to select a single cell having a single NMOS TFT while deselecting all others according to an access method to be described in detail below. Therefore, it is also possible to bias set voltages or programming and reset voltages as well as read voltages. The disclosed solution is also suitable for selecting a single cell when a negative bias voltage is applied to a digit line (which may be a vertical portion of a bit line) and a positive bias voltage is applied to a word line plate.

[0035] Figure 1 FIG. 100 (e.g., a three-dimensional (3D) memory array) of a memory array that supports a vertical 3D memory device with an NMOS TFT selector according to an example as disclosed herein is shown. The memory array 100 may include a first array or stack 105 of memory cells positioned above a substrate 104 and a second array or stack 108 of memory cells on top of the first array or stack 105.

[0036] The memory array 100 may include word lines 110 and digit lines 115. The memory cells of the first stack 105 and the second stack 108 may each have one or more self-selecting memory cells. Although Figure 1 some of the elements included in FIG. are labeled with numerical indicators, other corresponding elements are not labeled, but they are the same or will be understood to be similar.

[0037] The stack of memory cells may include a first dielectric material 120, a memory element material 125 (e.g., a chalcogenide material), a second dielectric material 130, a memory element material 135 (e.g., a chalcogenide material), and a third dielectric material 140. In some examples, the self-selecting memory cells of the first stack 105 and the second stack 108 may have a common conductive line such that the corresponding self-selecting memory cells of each stack 105 and 108 may share a digit line 115 or a word line 110.

[0038] In some examples, the memory cells may be programmed by providing an electrical pulse to the cell, which may include a memory storage element. The pulse may be provided via a first access line (e.g., word line 110) or a second access line (e.g., digit line 115) or a combination thereof. In some cases, after the pulse is provided, depending on the polarity of the memory cell, ions may migrate within the memory storage element. Thus, the concentration of ions relative to the first side or the second side of the memory storage element may be at least partially based on the polarity of the voltage between the first access line and the second access line. In some cases, an asymmetrically shaped memory storage element may cause ions to be more crowded at the portion of the element with a larger area. Certain portions of the memory storage element may have a higher resistivity and may thus cause a higher threshold voltage than other portions of the memory storage element. This description of ion migration represents an example of a mechanism of a self-selecting memory cell for achieving the results described herein. This example of the mechanism should not be considered limiting. The present disclosure also includes other examples of mechanisms of self-selecting memory cells for achieving the results described herein.

[0039] The architecture of memory array 100 can be referred to as a cross-point architecture. In some cases, in this cross-point architecture, memory cells are formed at topological cross-points such as between word line 110 and digit line 115. This cross-point architecture can provide relatively high-density data storage with a lower production cost compared to other memory architectures. For example, the cross-point architecture can have memory cells with a reduced area compared to other architectures and thus an increased memory cell density.

[0040] Although Figure 1 the example shows two memory stacks 105 and 108, other configurations are possible. In some instances, a single memory stack of self-selecting memory cells can be constructed above substrate 104, which can be referred to as two-dimensional memory. In some instances, three or four memory stacks of memory cells can be configured in a three-dimensional cross-point architecture in a similar manner.

[0041] Memory array 100 can include substrate 104 having a set of contacts arranged in a grid or staggered pattern. In some cases, the set of contacts can extend through the substrate and be coupled to the access lines of memory array 100. Memory array 100 can include an additional substrate 104 (e.g., positioned above two stacks 105 and 108). The additional substrate 104 can have a set of contacts (e.g., extending through the substrate) and be coupled to the access lines of memory array 100.

[0042] Memory array 100 can include a set of planes of conductive material separated from each other by a second insulating material formed on a first insulating material on a substrate material. Each of the set of planes of conductive material can include a set of recesses formed therein. The set of planes can be obtained through a reset process by using a sacrificial layer (e.g., a conformal layer) for etching during a stacked deposition processing step, removing the conformal layer after cell definition, and replacing the conformal layer with a more conductive material, for example, a word line plate corresponding to one or more word lines 110 on the same stack (e.g., memory stack 105, memory stack 108).

[0043] A set of conductive pillars can be formed in the openings to extend generally perpendicular to the set of planes of conductive material and the substrate. The set of conductive pillars can be divided into a set of pillar pairs. Each pillar in the pair of pillars can be coupled to a different one of the conductive contacts. In some cases, each pillar in the pair of pillars can be coupled to a conductive contact on substrate 104. Additionally or alternatively, one pillar of each pair of pillars can be coupled to a conductive contact on substrate 104, and the other pillar of each pair of pillars can be coupled to a conductive contact on a different substrate 104 (e.g., positioned above memory stacks 105 and 108).

[0044] In some instances, memory stacks 105 and 108 may include chalcogenide materials configured to store logical states. For example, the memory cells of memory stacks 105 and 108 may be examples of self-selecting memory cells. The chalcogenide materials may be formed in a set of recesses such that the chalcogenide material in each corresponding one of the set of recesses is in contact with at least one of a set of pillars of a pillar pair.

[0045] Figures 2A to 2F Illustrates various views of example memory arrays 200-a, 200-b, 200-c, and 200-d during a series of steps or processes that may be performed to form a stacked memory device as disclosed herein. Specifically, in Figures 2A to 2F a process of forming a word line plane, depositing a sacrificial layer, and an insulating material is shown.

[0046] Figure 2A A side view of an example memory array 200-a is shown. Figure 2B Illustrates during Figure 2A a process step after the process steps shown in Figure 2A a top view of an example memory array 200-b along section line A-A' of Figure 2C Illustrates along Figure 2B section line B-B' of a memory array 200-b (e.g., as shown in Figure 2B a cross-sectional view of Figure 2D Illustrates during Figure 2B and 2C a process step after the process steps shown in Figure 2B a cross-sectional view of a memory array 200-c along section line B-B' of Figure 2E Illustrates during Figure 2D a process step after the process steps shown in Figure 2B a cross-sectional view of a memory array 200-d along section line B-B' of

[0047] Figure 2F Illustrates along Figure 2E section line A-A' of an example memory array 200-d (e.g., as shown in Figure 2D a top view of

[0048] Figure 2AShows a side view of an example memory array 200-a according to an example as disclosed herein; for example, the memory array 200-a may support a vertical 3D memory device having NMOS TFT selectors. The memory array 200-a may include a set of conductive contacts 235 extending through the substrate 104-a or 104-b. The memory array 200-a may further include alternating layers of a material 240 and an insulating material 245 (e.g., an insulating material layer, a dielectric layer). In some cases, the material 240 may be a conductive material (e.g., to form a conductive layer). In other situations, the material 240 may be a sacrificial insulating material (e.g., different from the insulating material 245).

[0049] The substrate 104 may be a dielectric material, such as a dielectric film. A single conductive contact of the set of conductive contacts 235 may be configured to couple any single vertical pillar (e.g., a digit line) to a transistor (e.g., a select transistor or a digit line selector).

[0050] In some examples, the conductive contacts 235 may be formed in both substrates 104-a and 104-b. For example, the conductive contact 235-a may couple a first pillar of a pair of pillars (e.g., corresponding to a digit line) to a transistor. The conductive contact 235-c may couple the second pillar of the pair of pillars to the transistor. The conductive contacts 235-b and 235-d may each couple one pillar of a second pair of pillars to the transistor. Additionally or alternatively, each of the conductive contacts 235 may extend through the substrate 104-b (e.g., the conductive contacts 235-c and 235-d may be formed through the substrate 104-b). For example, the conductive contact 235-a may couple a first pillar of a pair of pillars to a transistor, and the contact 235-b may couple the second pillar of the pair of pillars to the transistor.

[0051] The set of conductive contacts 235 may be arranged in a grid pattern. In some examples, a corresponding one of the set of conductive contacts 235 may be surrounded by up to eight other conductive contacts 235. Additionally or alternatively, the set of conductive contacts 235 may be arranged in a staggered pattern or a hexagonal pattern. For example, a corresponding one of the set of conductive contacts 235 may be surrounded by up to six other conductive contacts 235.

[0052] The memory array 200-a may also include a set of stacked planes of the insulating material 245 and a set of stacked planes of the material 240 (e.g., word line planes or word line plates), where the material 240 may be a conductive material or an insulating material (e.g., as will be in Figure 2ADuring the process steps following the process steps shown, it is replaced with a conductive material). The stacked planes of material 240 can be separated from each other in the z direction (e.g., vertically separated) by a set of planes of insulating material 245. For example, the first plane (e.g., the bottom plane) of the second insulating material 245 can be formed (e.g., deposited) on the plane of substrate 104-b, and then the plane of material 240 can be formed on the first plane of the second insulating material 245. In some instances, a layer of the first insulating material 245 can be deposited on substrate 104-b. In some instances, material 240 can be a layer of conductive carbon or other conductive layer compatible with the active material. In some instances, material 240 can include conductive layers separated by active material passing through a protective barrier. The layers of material 240 can be configured to act as at least one word line plate. In some instances, material 240 and insulating material 245 form a set of layers, such as alternating layers.

[0053] Alternatively, material 240 can be a sacrificial insulating material. Here, the memory array 200-a can include a set of stacked planes of sacrificial insulating material 240 and a set of stacked planes of insulating material 245. The sacrificial insulating material 240 can be a material different from insulating material 245 (e.g., correspondingly, an oxide material and a nitride material). During Figure 2A the process steps following the process steps shown, the sacrificial insulating material 240 can be removed and replaced with a conductive material (e.g., a conductive carbon layer, or other conductive layer compatible with the active material).

[0054] Additional planes of the second insulating material 245 can be formed on material 240 in an alternating manner as Figure 2A shown. The second insulating material 245 can be a dielectric material, such as a dielectric film or layer. In some instances, the second insulating material 245 and substrate 104-a can be the same type of insulating material. Examples of insulating materials disclosed herein include (but are not limited to) dielectric materials such as silicon oxide.

[0055] Each corresponding one of the set of planes of material 240 can be located (e.g., formed) at a different level of the memory array 200-a. The individual planes of the material forming the memory cells can be referred to as a stack of the 3D memory array 200-a. Material 240 (e.g., the conductive material) can include (e.g., be formed of) a metallic (or semi-metallic) material or a semiconductor material such as doped polysilicon material, among others. In some instances, material 240 can be a plane of conductive carbon.

[0056] Figure 2ASix planes of the material 240 and seven planes of the second insulating material 245 are shown. The seventh plane of the second insulating material 245 can be the uppermost layer of the memory array 200-a. The number of planes of the material 240 and the second insulating material 245 is not limited to Figure 2A the number shown. The material 240 and the second insulating material 245 can be arranged in more than six stacks or less than six stacks.

[0057] Figure 2B Shows a top view of the memory array 200-b along the Figure 2A section line A-A'. Figure 2B Shows the formation trenches 250 that penetrate alternating planes of the material 240 (e.g., conductive material, insulating material) and the second insulating material 245 of the memory array 200-b. The trenches 250 can expose the substrate 104 and the conductive contacts 235 (previously shown in Figure 2A ) to the bottom of the trenches 250. The trenches 250 can be etched from top to bottom and are etched in a linear shape. In some cases, the trenches 250 can be formed by a combination of vertical and horizontal etching processes to form recesses within the trenches 250. Refer to Figure 2C for additional details regarding the etching process and the recesses. The trenches 250 can form a set of openings that extend in a generally parallel direction on each plane of the material 240 (e.g., word line plane, conductive layer).

[0058] Figure 2C Shows a side view of the memory array 200-b taken along the Figure 2B line B-B'. The memory array 200-b shows a set of recesses 215 formed in the material 240 (e.g., conductive material, insulating material) in each of the planes of the memory array 200-b. For example, a selective etching operation can be performed to form a set of recesses 215 in an isotropic manner in the sidewalls 290 and 291 of the trenches 250. In some instances, the trenches 250 include a first sidewall 290 spaced apart from a second sidewall 291, where a first portion 292 of the first sidewall 290 formed by the first insulating material 245 is spaced apart from a first portion 293 of the second sidewall 291 formed by the first insulating material 245 by a first distance. A second portion 294 of the first sidewall 290 formed by the first material 240 can be spaced apart from a second portion 294 of the second sidewall 291 formed by the first material 240 by a second distance greater than the first distance. In some instances, portions of the sidewalls 290 and 291 of the trenches 250 formed by the first material 240 are recessed relative to portions of the sidewalls 290 and 291 of the trenches 250 formed by the first insulating material 245.

[0059] The etching operation may include one or more vertical etching processes (e.g., anisotropic etching process or dry etching process or a combination thereof) or horizontal etching processes (e.g., isotropic etching process) or a combination thereof. For example, a vertical etching process may be performed to vertically etch the trench 250 to expose the substrate 104-b and one or more conductive contacts 235, and a horizontal etching process may be used to form at least one recess 215 in at least one material 240. The etching parameters may be selected such that the material 240 is etched faster than the second insulating material 245.

[0060] Figure 2D Shows a side view of the memory array 200-b taken along Figure 2B the line B-B'. The memory array 200-c shows the formation of a conformal material 220 (e.g., a sacrificial material or sacrificial layer). The conformal material 220 may be deposited into the trench 250 of the memory array 200-c. The conformal material 220 may be formed by conformally depositing the conformal material 220 in the recess 215 as Figure 2C shown. The conformal material 220 contacts the first sidewall 290, the second sidewall 291, and the bottom wall 295 of each trench 250 (e.g., contacts the substrate 104-b and the contact 235). Although Figure 2D shown the conformal material 220 formed on the sidewalls of the trench 250 (e.g., on the surfaces of the second insulating material 245 and the material 240 in different layers facing the trench 250), the example is not limited thereto. For example, in some cases, the conformal material 220 may be limited to a set of recesses 215 in the material 240 (e.g., conductive material, insulating material) in different layers. In some cases, the conformal material 220 may be referred to as a conformal layer or a sacrificial layer.

[0061] In some cases, an etching operation may be performed after the conformal material 220 is formed. In the etching operation, the conformal material 220 may be etched to form an opening or trench 250. The etching operation may cause the surface of the conformal material 220 (e.g., the surface facing the trench 250) to be spaced apart from the surface of the second insulating material 245 (e.g., the surface facing the trench 250). In some cases, the etching operation may cause the surface of the conformal material 220 (e.g., the surface facing the trench 250) to be substantially coplanar with the surface of the second insulating material 245 (e.g., the surface facing the trench 250), and thus form connected sidewalls of the trench. The etching operation may further cause the substrate 104-b and the contacts 235 to be exposed (e.g., the conformal material 220 is removed from the bottom wall 295 of the trench 250). The etching operations described herein may be a vertical etching process (e.g., an anisotropic etching process or a dry etching process or a combination thereof) or a horizontal etching process (e.g., an isotropic etching process). For example, a vertical etching process may be performed to vertically etch the trench 250, and a horizontal etching process may be used to form at least one recess in the first material 240 (e.g., the first conductive material 240, the sacrificial insulating material 240).

[0062] Figure 2E Shows a side view of the memory array 200-b taken along line B-B' of Figure 2B . The memory array 200-d shows the deposition of the dielectric material 218 in the trench 250 on top of the conformal material 220 of the memory array 200-d. The dielectric material 218 may contact the conformal material 220. The dielectric material 218 may further contact one or more contacts 235. The dielectric material 218 and the conformal material 220 may cooperate to fill the trench 250. In some cases, the dielectric material 218 may be an example of an insulating material. In some examples, the conformal material 220 may be selectively etched back to form a coplanar surface using the dielectric material 218. The depth of the notch may be defined depending on the desired thickness.

[0063] Figure 2F Shows a top view of an example memory array 200-d taken along the section line A-A' of Figure 2E . Figure 2F Shows the memory array 200-d after the dielectric material 218 is deposited into the set of trenches 250. Each of the trenches 250 in the memory array 200-d is lined with the conformal material 220 and filled with the dielectric material 218. The trenches 250 may extend through each of the layers of the material 240 (e.g., the conductive material 240, the sacrificial insulating material 240), as shown in Figure 2E .

[0064] Figures 3A to 3IShows various views of example memory arrays 200-e, 200-f, 200-g, 200-h, and 200-i during a series of steps or processes executable to form a stacked memory device as disclosed herein.

[0065] Figure 3A Shows during Figure 2F the process steps following those shown in Figure 2F a top view of example memory array 200-e along section line C-C'. Figure 3B Shows a cross-sectional view of example memory array 200-e along section line B-B' of Figure 3A . Figure 3C And 3D shows example memory array 200-f during the process steps following those shown in Figure 3A and 3B . Figure 3C Shows section C-C' of a top view of example memory array 200-f (as shown in Figure 2F ), and Figure 3D shows a cross-sectional view of example memory array 200-f along section line B-B' of Figure 3C . Figure 3E , 3F and 3G show example memory array 200-g during the process steps following those shown in Figure 3C and 3D . Figure 3E Shows section C-C' of a top view of example memory array 200-g (e.g., along section line A-A' of Figure 3D ) as shown in Figure 2F . Figure 3F Shows a top view of example memory array 200-g, and Figure 3G shows a cross-sectional view of example memory array 200-g along section line B-B' of Figure 3E . Figure 3H Shows section C-C' of a top view of example memory array 200-h during the process steps following those shown in Figure 3E , 3F and 3G. Figure 3F Figure 3I Shows an example memory array supporting a vertical 3D memory device with NMOS TFT selectors according to an example as disclosed herein.

[0066] Figure 3A Shows section C-C' of a top view of example memory array 200-e of Figure 2F . Example memory array 200-e may exhibit during Figure 2E and2F during the process steps after the process steps shown in Figure 2F a cross-section C-C' of the exemplary memory array 200-d as shown in. The opening 360 may be formed in the trench 250 by etching away a portion of the dielectric material 218 and / or the conformal material 220. The opening 360 may be positioned above one or more of the contacts 235 such that at least a portion of one of the contacts 235 is exposed by the opening 360. Refer to Figure 3B for additional details showing and describing the relationship between the opening 360 and the contacts 235. In some cases, the exemplary memory array 200-e may include a set of openings 360. For example, a set of openings may be formed at intervals along each of the trenches 250. Each of the openings 360 within the trench 250 may be separated from the other openings in the trench 250 by the dielectric material 218. The etching process used to form the opening 360 may be a vertical etching process. In some instances, the etching operation may not etch away all portions of the conformal material 320, e.g., portions where the opening 360 is not formed.

[0067] Figure 3B shows a side view of the memory array 200-e taken along the Figure 3A line B-B'. As shown in Figure 3B , a set of recesses 215 may be formed in the material 240 in each of the planes. The set of recesses 215 may be formed during the formation of the opening 360 (e.g., as discussed in reference to Figure 3A ). For example, a selective etching operation may be performed to form the set of recesses 215 in a fully or partially isotropic manner. The etching chemical reaction may be selected to selectively reach the material 240. The contacts 235 may be exposed by forming the opening 360 in the trench 250.

[0068] Figure 3C shows a top view of a cross-section C-C' of an exemplary memory array 200-f according to an example as disclosed herein. The top view may be a view taken along the Figure 2F section line A-A'. The exemplary memory array 200-f may be formed from the exemplary memory array 200-e after the process steps shown in Figure 3B and Figure 3A and 3B . As shown in Figure 3C , the storage element material 365 may be formed in the opening 360. In some cases, the storage element material 365 may extend to contact each sidewall of the material 240. The storage element material 365 may further contact the conformal material 220 and the dielectric material 218. (e.g., by depositing the storage element material 365 in the opening 360) Forming the storage element material 365 in the opening 360 may reduce the size of the opening 360.

[0069] The memory element material 365 can be an example of a chalcogenide material that can act as a self-selective memory element material (e.g., a material that can act as both a select device and a memory element), such as a chalcogenide alloy and / or glass. For example, the memory element material 365 can respond to an applied voltage, such as a programming pulse. For an applied voltage less than the threshold voltage, the memory element material 365 can remain in a non-conductive state (e.g., an "off" state). Alternatively, in response to an applied voltage greater than the threshold voltage, the memory element material 365 can enter a conductive state (e.g., an "on" state).

[0070] Figure 3D Shows a side view of the memory array 200-f taken along line B-B' of Figure 3C The memory element material 365 can be formed in the set of recesses 215 by conformally depositing the memory element material 365 into the trenches 250. The memory element material 365 can be deposited to contact the sidewalls 290 and 291 and the bottom wall 295 of the trench 250 exposed by the etching of the conformal material 320. When the memory element material 365 contacts the bottom wall 295 of the trench 250, the memory element material 365 covers the exposed contact 235. The memory element material 365 can include a top layer 366.

[0071] Figure 3E Shows a top view (e.g., along the section line A-A') of an example memory array 200-g of Figure 2F Shown in Figure 3C And 3D An etching operation can be performed on the example memory array 200-f shown in

[0072] The data storage element can be programmed to a target state by applying a pulse (e.g., a programming pulse) that meets a programming threshold. The amplitude, shape, or other characteristics of the programming pulse can be configured such that the storage element material 365 assumes the target state. For example, after applying the programming pulse, ions of the storage element assembly can redistribute throughout the storage element, thereby changing the resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of the storage element assembly can change based on the applied programming pulse.

[0073] The state stored by the storage element assembly can be sensed, detected, or read by applying a read pulse to the storage element assembly. The amplitude, shape, or other characteristics of the read pulse can be configured to allow the sensing component to determine what state is stored on the storage element assembly. For example, in some cases, the amplitude of the read pulse is configured to be at a level where the storage element assembly will be in an "on" state (e.g., current is directed through the material) for a first state but will be in an "off" state (e.g., little or no current is directed through the material) for a second state.

[0074] In some cases, the polarity of the pulse (whether programming or reading) applied to the storage element assembly can affect the effectiveness of the operation being performed. For example, if the storage element assembly stores a first state, a read pulse with a first polarity may cause the storage element assembly to assume an "on" state, while a read pulse with a second polarity may cause the storage element assembly to assume an "off" state. This can occur due to the asymmetric distribution of ions or other materials in the storage element assembly when storing the state. A similar principle applies to programming pulses and other pulses or voltages.

[0075] Examples of chalcogenide materials that can serve as storage element assemblies include indium (In)-antimony (Sb)-tellurium (Te) (IST) materials such as In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc., and germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) materials such as Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, etc., or other chalcogenide materials, including for example alloys that do not change phase during operation (e.g., selenium-based chalcogenide alloys). In addition, the chalcogenide materials can include very low concentrations of other dopant materials. Other examples of chalcogenide materials can include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), sulfur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc) materials, and combinations thereof. As used herein, hyphenated chemical composition designations indicate the elements included in a particular mixture or compound and are intended to represent all stoichiometries involving the indicated elements. In some instances, the chalcogenide materials can be chalcogenide glasses or amorphous chalcogenide materials. In some instances, chalcogenide materials primarily having selenium (Se), arsenic (As), and germanium (Ge) can be referred to as SAG alloys. In some instances, the SAG alloys can include silicon (Si), and such chalcogenide materials can be referred to as SiSAG alloys. In some instances, the chalcogenide glasses can include additional elements in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F). In some instances, the conductivity can be controlled via doping with various chemical species. For example, doping can include incorporating Group 3 (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or Group 4 (tin (Sn), carbon (C), silicon (Si), etc.) elements into the composition.

[0076] Figure 3F Shows a top view of an example memory array 200-g along Figure 3D section line A-A'. Figure 3F Includes Figure 3E section C-C' shown in. The example memory array 200-g shows a collection of trenches 250. Each of the trenches 250 includes a collection of storage element assemblies of storage element material 365. The collection of storage element assemblies can be separated from other storage element assemblies by openings 360 and dielectric material 218. The storage element assemblies can be in contact with conformal material 220.

[0077] Figure 3G Shows a cross-section along Figure 3FSide view of memory array 200-g taken along line B-B'. The etching operation (e.g., as discussed with reference to Figure 3C and 3D ) can be performed after forming the memory element material 365 such that the surface of the memory element material 365 (e.g., the surface facing the trench 250) is substantially coplanar with the surface of the layer of insulating material 245 (e.g., the surface facing the trench 250). Etching of the memory element material 365 can form connected sidewalls and remove the top layer 366 of the memory element material 365, as shown in Figure 3D . Etching of the memory element material 365 can also expose the contact 235 in the substrate 104-b.

[0078] The portion of the memory element material 365 located in the recess can correspond to a memory element assembly. In each recess, each memory element assembly of the memory element material 365 can contact a single conductive material 240 (e.g., a single conductive material 240 positioned adjacent to the cell of the memory element material 365) and at least two dielectric layers (e.g., a top insulating material 245 positioned on top of the memory element assembly of the memory element material 365 and a bottom insulating material 245 positioned on the bottom of the memory element assembly of the memory element material 365). In some cases, each memory element assembly of the memory element material 365 can contact a single material 240. Here, the material 240 can be subsequently removed (e.g., during a process step after the process steps shown in Figure 3G ) and replaced with a conductive material. Etching of the memory element material 365 can expose the memory element assemblies of the memory element material 365. Etching of the memory element material 365 can also expose the contact 235 in the substrate 104-b.

[0079] Figure 3H Shows a top view of an example memory array 200-h during a process step after the process steps shown in Figure 3E , 3F and 3G (section C-C' as shown in Figure 3F ). As shown in Figure 3H , a conductive material 370 is deposited into the opening 360. The conductive material 370 can form a conductive pillar extending from a first substrate (e.g., the substrate 104-a as shown with reference to Figure 2C ) to a second substrate (e.g., substrate 104-b). In some implementations, the conductive material 370 contacts the insulating material 245 and at least a portion of the layer of the memory element material 365 as shown in Figure 3G . In some instances, the conductive material 370 is compatible with the active material. The conductive material 370 can be a uniform conductive material (e.g., a conformal conductive material), or have a barrier layer of an internal material (e.g., where the barrier layer surrounds the conductive material).

[0080] In the case where the conductive material 370 includes a barrier layer and an internal material, the barrier material may be deposited into the opening 360. In some implementations, the barrier material may contact the insulating material 245 and at least a portion of the memory element material 365 as shown in Figure 3G . In some instances, the barrier material may be compatible with the active material. The barrier material may be a conductive material (e.g., a conformal conductive material) or a barrier layer having a conductive material. For example, the barrier material may include aluminum oxide. The internal material may be deposited into the opening 360 (e.g., to contact the barrier material) to form a conductive pillar. The internal material may be a metallic (or semi-metallic) material, or a semiconductor material such as doped polysilicon material, among others. However, other metallic, semi-metallic, or semiconductor materials, metallic materials, or dielectric materials may be used.

[0081] The conductive material 370 may contact the first and second memory element assemblies formed by the memory element material 365. The pillars (e.g., having the conductive material 370) formed in each respective one of the set of openings 360 may be arranged to extend generally orthogonally to the alternating planes of the material 240 and the insulating material 245. The memory element material 365 and the conductive pillars formed in each respective one of the set of openings 360 may be formed in a generally square shape. The examples of the present disclosure are not limited to an exact or approximately exact square shape. For example, the memory element material 365 and the conductive pillars may be formed in any shape, including circular or elliptical.

[0082] Figure 3I An example memory array 200-i is shown that supports a vertical 3D memory device having an NMOS TFT selector according to examples as disclosed herein. In Figure 3I the configuration of the memory device shown, the pillars of the conductive material 370 contact the contacts 235 on the same substrate 104-b. The substrate 104-b is shown positioned below the pillars of the conductive material 370, but in some other cases, the contacts 235 may be formed to pass through a substrate 104-a positioned above the pillars of the conductive material 370.

[0083] The contact 235 can couple a pillar formed of the conductive material 370 to an additional select element such as a select transistor. For example, the contact 235 can couple the pillar (e.g., a digit line) to the NMOS TFT 305, which is formed in a pillar select layer below the substrate 104-b. In some instances (not shown), the pillar select layer can be located above the memory layer, e.g., the TFT can contact from above the digit line. A combination of the two configurations is also possible; for example, some TFTs can be located below the memory layer and some can be located above the memory layer such that digit line selection can be partially from above and partially from below. Details of the NMOS TFT 305 will be described below. The portion located above the pillar select layer can form a memory layer in which a vertical 3D memory array of memory cells is disposed. The transistor 305 can be a digit line selector formed as a regular matrix. The transistor 305 can be positioned to selectively couple or isolate the pillar (e.g., digit line) at various times during an access operation (e.g., a read operation, a write operation, a refresh operation). Activating the transistor 305 can initiate an access operation of one of the memory element assemblies formed of the memory element material 365. For example, activating the transistor 305 and applying a voltage to the material 240 (e.g., applying a voltage to the conductive material through a word line driver) can access the memory element assembly formed of the memory element material 365.

[0084] A peripheral circuit layer can be formed below the pillar select layer, and in the peripheral circuit layer, e.g., sense amplifiers and decoding circuitry can be arranged for word lines and bit lines.

[0085] Figure 4A and 4B Illustrate example memory arrays 200-j and 200-k during a series of steps or processes executable to form a stacked memory device as disclosed herein.

[0086] Figure 4A Illustrate a top view of an example memory array 200-j according to an example as disclosed herein. It can illustrate the example memory array 200-j during a series of steps or processes that can be performed Figure 3G subsequently.

[0087] The conductive material 370 can be deposited into the opening 360 to form a conductive pillar. In some cases, the pillar can be partially filled with the conductive material 370 and then filled with a dielectric material 705. In some cases, the dielectric material 705 can be the same as the dielectric material 218. The pillar can extend from a first substrate (e.g., substrate 104-a) to a second substrate (e.g., substrate 104-b).

[0088] The conductive material 370 can contact the first and second memory element assemblies formed of the memory element material 365. The pillars (e.g., having the conductive material 370 and the dielectric material 705) in each corresponding one of the set of openings 360 can be arranged to extend generally orthogonally to the alternating planes of the material 240 and the insulating material 245.

[0089] Figure 4B FIG. 4 shows a top view of an example memory array 200-k according to an example as disclosed herein. The memory array 200-k can be formed after forming a second opening and then filling the second opening with the insulating material 710. In some cases, the dielectric material 705 and the insulating material 710 are examples of the same material. The second opening can be formed in the trench 250 by etching away a portion of the conductive material 370. The etching process can further include etching away a portion of other materials. For example, the etching process can etch some (or all) of the dielectric material 218. The etching process can include a vertical etching process that occurs generally orthogonally to the alternating planes of the material 240 and the insulating material 245. For example, the etching process can include a single-gate vertical channel (SGVC) 3D NAND (not AND) technology to produce the second opening of the example memory array 200-k. The second opening can extend to the bottom substrate (e.g., 104-b) to expose one or more contacts 235. The second opening can divide the pillars (e.g., including the conductive material 370 and the dielectric material 705) into a pair of pillars including a first pillar (e.g., a sub-pillar) and a second pillar (e.g., a sub-pillar). Each sub-pillar of the pair of pillars can correspond to a digit line. The size (e.g., cross-sectional area) of each sub-pillar of the pair of pillars may not affect the operation of the memory array 200-k. That is, the height of each sub-pillar of the pair of pillars (e.g., extending from a first substrate such as the substrate 104-a to a second substrate such as the substrate 104-b) can be relatively low (e.g., less than two micrometers).

[0090] In some cases, the trench 250 can extend and include a set of second openings (e.g., separated by the dielectric material 218), where each opening divides the pillar into a pair of pillars. The insulating material 710 can be a dielectric material. In some cases, the insulating material 710 can be the same material as the dielectric material 218. The insulating material 710 can contact the pillars formed of the conductive material 370. The insulating material 710 can extend from the top substrate (e.g., Figure 2A the substrate 104-a shown in FIG. 4) to the bottom substrate (e.g., Figure 2A the substrate 104-b shown in FIG. 4), thus isolating each sub-pillar of the pair of pillars. The insulating material 710 can further extend to contact the dielectric material 218. Here, the insulating material (e.g., the insulating material 410 combined with the dielectric material 218) can extend the length of the trench 250.

[0091] The insulating material 710 can isolate the pillars within the pillar from each other. This can reduce the effect of accessing the first memory element assembly located on the second memory element assembly when the first and second memory element assemblies are positioned in the same recess. The insulating material 710 can separate the memory element materials 365 on either side of the trench 250. That is, the insulating material 710 can isolate (e.g., electrically isolate) the memory cells (e.g., formed of the memory element material 365) in contact with the first sidewall of the contact trench 250 from the memory cells of the second sidewall of the contact trench 250.

[0092] Figure 5 Another example memory array 200-l is shown that supports a vertical 3D memory device with an NMOS TFT selector as disclosed herein. Specifically, Figure 5 A configuration for coupling a digital line to a digital line selector is shown.

[0093] Figure 5 A cross-sectional view of the memory array 200-l is shown. The cross-sectional view can be along the section line B-B' as shown in any of Figure 4B the above. Figure 5 A configuration of the memory device is shown in which each pillar having a conductive material 370 (e.g., a pair of pillars) contacts a contact 235 on the same substrate 104. The substrate 104-b is shown positioned below the pillars of the conductive material 370, but in some other cases, the contact 235 can be formed to pass through the substrate 104-a positioned above the pillars of the conductive material 370.

[0094] The memory array 200-l can include a first pillar (or first sub-pillar) formed of a conductive material 370-a that contacts a contact 235-a of the substrate 104-b. The contact 235-a can couple the pillar formed of the conductive material 370-a to an additional selection element such as a selection transistor. For example, the contact 235-a can couple the first pillar (e.g., a digital line) to an NMOS TFT 505-a, which is formed in a pillar selection layer ( Figure 5 not shown in the above and similar to as shown in Figure 3I the above). Details of the NMOS TFT 505-a will be described below. The portion located above the pillar selection layer can form a memory layer ( Figure 5 not shown in the above and similar to as shown in Figure 3Ias shown, a vertical 3D memory array in which memory cells are disposed. The transistor 505-a can be a digital line selector formed as a regular matrix. The transistor 505-a can be positioned to selectively couple or isolate a pillar (e.g., a digital line) at various times during an access operation (e.g., a read operation, a write operation, a refresh operation). Activating the transistor 505-a can initiate an access operation of one of the memory element assemblies formed by the memory element material 365. For example, activating the transistor 505-a and applying a voltage to the material 240-a (e.g., applying a voltage to the conductive material through a word line driver) can access the memory element assembly formed by the memory element material 365-a. The material 240-a can be an example of the conductive material 240. In some cases, the material 240-a can be deposited onto the stack (e.g., during the process steps shown previously) as a conductive material. In some other cases, the material 240-a can be deposited onto the stack as a sacrificial insulating material. In a subsequent process step, the material 240-a can be removed and replaced with the conductive material 240-a. Figure 2A before the process steps shown).

[0095] The memory array 200-l can further include a second pillar (or second sub-pillar) formed of a conductive material 370-b that contacts the contact 235-b of the contact substrate 104-b. The pillar formed of the conductive material 370-a and the pillar formed of the conductive material 370-b can be a pair of pillars. That is, the pillar formed of the conductive material 370-a and the pillar formed of the conductive material 370-b can be formed when the conductive pillar is divided by an etching process. The contact 235-b can couple the second pillar formed of the conductive material 370-b to a transistor (e.g., an NMOS TFT), 505-b, which can be a digital line selector formed as a regular matrix. In some cases, the transistor 505-b can be in the same layer (e.g., part of the same matrix) as the transistor 505-a. Details of the NMOS TFTs 505-a and 505-b will be described below.

[0096] In some embodiments, the selector TFTs 505-a and 505-b can be located on opposite sides of the memory layer and contact the respective sub-pillars from below (as Figure 5 depicted) and from above (not shown); in some cases, both TFTs can be in a pillar selection layer (e.g., a polysilicon layer) above the memory layer. A Figure 5 peripheral circuit layer not shown and similar to that shown in Figure 3I can be formed below the pillar selection layer, and in the peripheral circuit layer, for example, sense amplifiers and decoding circuitry can be arranged for word lines and bit lines.

[0097] Figure 6Shows an example of a transistor semiconductor device according to an example disclosed herein, e.g., a field effect NMOS thin film transistor (TFT). Figure 6 FIG. depicts an embodiment of two TFT selection devices 504a and 504b, which can be used to select a vertically oriented bit line portion or an array digital line (not shown). Each TFT selection device 504a, 504b has two source / drain (S / D) regions. The source / drain regions are located on either side of the channel region. In one embodiment, the source / drain regions and the channel region are polysilicon. The TFT selection devices 504a, 504b have an upper junction between the channel region and the upper D and a lower junction between the channel region and the lower S.

[0098] Each of the TFT selection devices 504a, 504b has two gates 507 and a dielectric material 505 that separates each gate from the channel region and the S / D regions. This dielectric can be referred to as a gate dielectric because it separates the gate 507 from the channel region and the S / D regions. In one embodiment, the gate dielectric 505 extends along the sides of the source / drain regions and the channel region or each selection device. The gate dielectric can extend in the x direction along the vertical sidewalls of the pillar structure that includes the channel region and the S / D regions.

[0099] Depending on the situation, the gate dielectric separates the gate from either the channel region or the source / drain region. In this example, each gate 507 extends vertically from below the lower junction to above the upper junction. That is, the gate 507 is formed to be adjacent to the vertical length of the channel region and a portion of the vertical length of both the S / D regions. The upper drain can be connected to a vertically oriented bit line portion or an array digital line. In some embodiments, for example, a gate material can be deposited and selectively (e.g., anisotropically) removed to form the gate 507, e.g., along and / or around the channel region, forming a spacer-like structure of the gate material adjacent to the gate dielectric.

[0100] An inter-gap filling dielectric 520, such as an oxide, is formed as an insulating material between adjacent selection devices. In some cases, the TFT selection devices 504a and 504b can share the same gate 507 located therebetween. In other words, there may be no gap between adjacent selection devices 504a and 504b.

[0101] In some cases, the TFT selection devices can be formed in a regular matrix below the memory array, specifically, below the pillars of the memory cells. In this example, the pitch of adjacent TFT selection devices in the x direction can be consistent with the corresponding pitch of the memory cells, which will be further explained with reference to Figures 7A to 7C Further explanation.

[0102] Figures 7A to 7CShows various views of an example NMOS TFT selector according to an example as disclosed herein.

[0103] Typically, a polysilicon-based TFT having, for example, a 48 nm pitch and a 100 nm channel length may be capable of supporting 1.5 V as the maximum drain bias and 3.5 V as the maximum gate bias, and may have a 20 uA I ON . Other voltage and / or current values are possible. This is a depletion-mode MOSFET with N+ S / D implants and N-channel implants. However, in the present disclosure, in accordance with a significantly relaxed pitch with respect to the V-3D MTX cell, a selector transistor configured with at least a pair of parallel elongated TFTs enabling a factor of 10× more than I ON is proposed. This 10× factor will become a 5× factor or greater due to a doubling of the channel length (from 110 to ~220 nm).

[0104] As shown in Figures 7A to 7C , the strip 710 may represent the gate terminal. There may be two gates having a gate oxide on one side of the channel region 720 and another gate oxide on the other side, and the gates may be represented by rectangular boxes, and thus the width of the TFT may be doubled. Below the channel region 720, there may be a source region of the TFT, and the rectangular box may physically correspond to a polysilicon pillar of the transistor channel, and the drain region is connected to the pillar.

[0105] In other words, a matrix of thin-film transistors (TFTs) is provided below the digital lines, with one TFT transistor per digital line. The thin-film transistors (TFTs) are formed in a polysilicon layer below the 3D memory array, while the peripheral circuitry having sense amplifiers and decoding circuitry for the word lines and bit lines is formed below the matrix.

[0106] As can be seen from these Figure 7A views, the transistor channel has been extended up to 120 nm, where the integration distance is limited to 50 nm. Thus, the width of the transistor has been relaxed or extended, and two transistors are arranged in parallel, so that the driving ability can be approximately five times (due to the larger width), and thus capable of feeding the correct current to the memory cell.

[0107] Figure 7B An alternative configuration is schematically shown, where a strip 730 forming the gate terminal is configured in a square around the channel region 740.

[0108] As another alternative, in Figure 7C , an example is shown where the strip 750 is doubled between two adjacent channel regions 720 while keeping the integration distance still reduced to 55 nm.

[0109] Figures 8A to 8DVarious diagrams are shown for accessing memory cells of a vertical 3D memory device with NMOS TFT selectors as disclosed herein. Specifically, Figures 8A to 8D shows how to select a single memory cell with a single NMOS TFT while deselecting all others.

[0110] As an example, the diagrams may show only a 3×3 matrix of pillars (P1, …, P9, i.e., the pillars extend vertically towards the reader), and more specifically, a small matrix of nine TFT select transistors provided at the bottom of these pillars, one TFT per pillar.

[0111] As Figure 8A shown, for deselection, a floating - bias strategy is safely employed for unselected pillars that cannot be shorted to GND. The potential of the unselected pillars that remain floating will be determined by the capacitance ratio between the pillars and the WL (biased at GND - all unselected, and at - 3.5V, one selected), and thus will be approximately GND.

[0112] On Figure 8A the left side of Figure 1 is shown an example 3×3 matrix of pillars (P1, …, P9). In some examples, each pillar may correspond to Figure 6 and 7A the digit line 115 in

[0113] As Figure 8AAs depicted, the pillars (P1, …, P9) and the select transistors (T1, …, T9) can be organized into rows and columns. For example, transistors T1, T2, and T3 can have respective terminals (e.g., source terminals) coupled to a common line L0; transistors T4, T5, and T6 can have respective terminals (e.g., source terminals) coupled to a common line L1, and transistors T7, T8, and T9 can have respective terminals (e.g., source terminals) coupled to a common line L3. Lines L0, L1, and L2 can be coupled (not shown) to a digital line driver formed in a peripheral circuit layer formed below the pillar selection layer (e.g., a silicon substrate layer), such as a CMOS below the array. Lines L0, L1, and L2 are configured to be biased to respective line voltages V_L0, V_L1, and V_L2, which line voltages can be selected digital line programming (e.g., set / reset) or read voltages or unselected digital line voltages.

[0114] In the depicted row / column organization, transistors T1, T4, and T7 can have gate terminals coupled to a common row line R2; transistors T2, T5, and T8 can have respective gate terminals coupled to a common row line R1, and transistors T3, T6, and T9 can have respective gate terminals coupled to a common row line R0. Lines R0, R1, and R2 can be coupled (not shown) to a digital line driver control circuitry formed in the peripheral circuit layer. Row lines R0, R1, and R2 are configured to be biased to respective row line voltages V_R0, V_R1, and V_R2, which can be conduction voltages or biased to a prohibit voltage, based on the operation to be performed and the addressed cell or pillar.

[0115] On the Figure 8A right side, a schematic cross-section of a portion of a 3D memory array is shown. Each memory cell includes a storage element, the intersection of a digital line (e.g., pillar Pi) with a word line that can be a selected word line SWL or an unselected word line UWL. The memory cell can be programmed in one of at least two states by applying a programming pulse of an appropriate amplitude and polarity. For example, a first polarity pulse having a magnitude higher than the threshold voltage of the memory cell can be applied to program the memory cell in a first state (set state); the first polarity can be a positive polarity, e.g., the word line voltage is higher than the digital line voltage - see reference Figure 8B discussed. A second polarity pulse having a magnitude higher than the threshold voltage of the memory cell can be applied to program the memory cell in a second state (reset state); the second polarity can be different from the first polarity (e.g., opposite thereto), and thus the second polarity can be a negative polarity, e.g., the word line voltage is less than the digital line voltage - see reference Figure 8C discussed. In some embodiments, the programming polarities can be interchanged; for example, in some cases, the set state can use negative polarity programming and the reset state can use positive polarity programming. The set and reset states can respectively correspond to logic 1 and logic 0 states; however, different rules can be employed.

[0116] Memory cells in different states (e.g., set and reset, or logic 1 and 0) have different threshold voltages. Thus, it is possible to apply a sense or read voltage across the memory cell to read the cell state. The read voltage can be a positive voltage or a negative voltage; depending on the polarity of the read voltage, different situations can occur, as explained below.

[0117] Generally, after a programming pulse in a given polarity, when reading is performed in the same polarity, the memory cell has a low threshold voltage, while when reading in the opposite polarity, the memory cell has a high threshold voltage. Thus, if the set state is programmed with a positive polarity pulse, as described above, then the memory cell has a low threshold voltage when read in the same (positive) polarity. Conversely, a cell programmed with a positive polarity pulse in the set state has a high threshold voltage when read in the opposite (negative) polarity. At the same time, if the reset state is programmed with a negative polarity pulse, as described above, then the memory cell has a high threshold voltage when read in the opposite (positive) polarity. Conversely, a cell programmed with a negative polarity pulse in the reset state has a low threshold voltage when read in the same (negative) polarity.

[0118] Independent of the read polarity, it is possible to distinguish between the set and reset states and thus read the cell logic state associated therewith. In fact, it is sufficient to bias the selected digit line terminal and the selected word line SWL terminal to a read voltage (which is an intermediate voltage between the low and high threshold voltages of the memory cell) and detect which memory cells draw a large current or have been thresholded. In the example above, with a negative polarity read scheme, cells programmed with a positive polarity pulse in the set state are not thresholded, while cells programmed with a negative polarity in the reset state are thresholded. As already mentioned, different read schemes can be employed, e.g., a positive polarity read scheme.

[0119] Referring again to Figure 8A the cross-section shown on the right, during an access operation, in the case where the pillar is the selected pillar (e.g., Figure 8A pillar P5 in the left part of ), the pillar is biased to an addressed digit line access voltage that can be a programming voltage (e.g., a set or reset voltage) based on the operation being performed, or to a read voltage. All cells coupled to the selected pillar have a digit line terminal biased to the digit line access voltage, but only the addressed cell (in the depicted example, a cell on the fourth plane from the bottom) has a word line terminal SWL biased to the word line access voltage VWL - all other cells in the selected pillar (e.g., unselected cells) have an unselected word line UWL terminal biased to an unselected voltage (e.g., a ground (GND) voltage).

[0120] During an access operation, when the pillar is an unselected pillar (e.g., pillars P1, …, P4, P6, …, P9), the pillar is floating (or grounded) because, as will be explained in detail below, the corresponding selector transistors (T1, …, T4, T6, …, T9) are in a prohibited situation and thus effectively insulate the pillar from the bias circuit system (or it is passing the prohibited voltage provided by the bias circuit system, e.g., the ground voltage GND). When the unselected pillar is floating, it is capacitively coupled to the word line, and thus the actual pillar voltage depends on the word line voltage weighted by the corresponding capacitance ratio (pillar capacitance to each WL node divided by the total capacitance, e.g., pillar capacitance to all WL nodes). Since all unaddressed or unselected word lines UWL are at the ground voltage during an access operation and only the addressed or selected word line SWL is at the access voltage, the pillar voltage remains close to the ground. The deviation from the ground voltage decreases as the number of word lines increases (e.g., as the number of planes or stacks in a 3D memory array increases).

[0121] Although Figure 8A FIG. shows a small matrix of pillars (P1, …, P9) and selector transistors (T1, …, T9) organized into 3 rows and 3 columns, but any number of rows and columns can be used. In the following description, pillar P5 will be considered the addressed or target pillar, e.g., the addressed cell is coupled to the selected pillar P5 and to the selected plane or word line SWL. Based on the operation to be performed, the selected word line SWL is biased to an access word line voltage V_WL that typically has an opposite polarity with respect to the digital line access voltage; in an exact voltage division method, the digital line voltage and the word line voltage are the same or approximately the same; however, for example, different methods can be employed, such as the amplitude ratio is not 1. Even if not explicitly specified, the unaddressed word lines UWL are typically biased to the ground voltage through the corresponding word line circuit system (not shown).

[0122] To simplify the following description, a negative voltage read scheme will be employed; for example, during a read access operation, the overall voltage drop across the selected word line SWL terminal and the selected digit line terminal (post P5) of a memory cell is negative, i.e., V_WL - V_L1 < 0 volts. Additionally, it will be assumed that the threshold voltage of a memory cell in the set state (e.g., logic 1 state) is in a negative voltage within the range of approximately -6.5V to approximately -5.5V (corresponding to a positive voltage read within the range of approximately +3.5V to approximately +4.5V), while the threshold voltage of a memory cell in the reset state (e.g., logic 0 state) is in a negative voltage within the range of approximately -4.5V to approximately -3.5V (corresponding to a positive voltage read within the range of approximately +5.5V to approximately +6.5V). This is merely an example, and different threshold voltage values and ranges may be used. Thus, in the above example, during a read access operation of a memory cell, a -5.0V read voltage (e.g., selected word line SWL voltage versus selected digit line P5 voltage) may be applied across the addressed memory cell, as Figure 8D described.

[0123] As Figure 8B shown, a memory cell connected to post P5 can be programmed in the set state. For this purpose, a positive bias pulse of approximately +7V may need to be applied, since the cell may be in a reset state with a threshold voltage Vt up to 7V (considering a 0.5V tolerance with respect to the target reset programming state threshold voltage range of 5.5 to 6.5V). This can be achieved by applying at least +3.5V to the selected word line (while others are at GND - not shown here, see Figure 8A ), and applying at least -3.5V to bit line L1. The sector transistor T5 is enabled with a gate turn - on voltage of +1.0V (e.g., applied to row line R1) to transfer the voltage to the digit line of the addressed cell in the array (post P5). It is necessary to deselect the other posts (P1,…,P9, except P5), whose cells may potentially share the same word line and / or bit line.

[0124] As the voltages of row lines R0 and R2 and the gates coupled thereto increase to a bias voltage higher than -3.5V, transistors T4 and T6 will turn on, thus undesirably biasing the array digit lines (e.g., posts P4 and P6) coupled to the addressed bit line L1. Therefore, a -3.5V blocking or inhibit bias can be applied to row lines R0 and R2 to prevent T4 and T6 from turning on; this effectively results in floating array digit lines P4 and P6. Subsequently, a ground voltage GND can be applied to bit lines L0 and L2.

[0125] In this configuration, all TFTs T1, …, T9 (except T5) can be in an off state. For example, the voltages at the corresponding terminals coupled to bit lines L0, L1, and L2 are not transferred to the corresponding posts P1, …, P9 (except P5), which can thus float. Transistors T2 and T8 may or may not transfer the GND voltage to the corresponding posts P2 and P8, depending on their actual threshold voltages and the actual bias voltage of row line R1 (which can thus be adjusted).

[0126] The floating post potential will be determined by the capacitance ratio between the post and the WLs (all unselected word lines biased at GND and the selected WL biased at +3.5V). Thus, the floating post can reach a small positive bias (e.g., +1V) that is safe for deselection.

[0127] As Figure 8C shown, the memory cell connected to post P5 can be programmed in the reset state. For this purpose, a negative bias pulse of about -7V may need to be applied, since the cell in the reset state also needs to be reprogrammed and / or the cell may be in a set state with a threshold voltage Vt up to -7V (relative to the target set programming state threshold voltage range of -5.5 to -6.5V, considering a 0.5V tolerance). This can be obtained by applying -3.5V to the selected word line (while the others are at GND -- not shown here, see Figure 8A ), and applying +3.5V to bit line L1. The sector transistor T5 is enabled with a gate conduction voltage of +4.5V (e.g., applied to row line R1) to transfer the voltage to the digital line of the addressed cell in the array (post P5). The other posts (P1, …, P9, except P5) need to be deselected, whose cells may potentially share the same word line and / or bit line.

[0128] To turn off transistors T4 and T6, and thus effectively isolate posts P4 and P6 from bit line L1, row lines R0 and R2 and the gates coupled thereto can be biased at +3.5V, such that posts P4 and P6 will float. Subsequently, the ground voltage GND can be applied to bit lines L0 and L2, such that the array digital line posts P1, P2, P3, P7, P8, and P9 will be shorted to GND via the corresponding transistors T1, T2, T3, T7, T8, and T9.

[0129] In this configuration, only posts P4 and P6 can float. The potential of the digital line P4 and P6 posts will be determined by the capacitance ratio between the posts and the WLs (all unselected word lines biased at GND and one selected word line biased at -3.5V). Thus, the floating posts can reach a small negative bias (e.g., -1V) that is safe for deselection. The other unaddressed posts are grounded, i.e., also a safe condition for deselection.

[0130] As Figure 8D shown, the state of the memory cells connected to the P5 pillar can be read out. For this purpose, a negative bias pulse of about -5V may need to be applied. This can be achieved by applying at least -2.5V to the selected word line (while the others are at GND--not shown here, see Figure 8A ), and applying at least +2.5V to the bit line L1. The sector transistor T5 is enabled by applying a gate conduction voltage of +3.5V (e.g., applied to the row line R1) to transfer the voltage to the digit line of the addressed cell in the array (pillar P5). It is necessary to deselect the other pillars (P1,…,P9, except P5), whose cells may potentially share the same word line and / or bit line.

[0131] To turn off the transistors T4 and T6, and thus effectively isolate the pillars P4 and P6 from the bit line L1, the row lines R0 and R2 and the gate biases coupled thereto can be set to +2.5V, such that the P4 and P6 pillars will float. Subsequently, the ground voltage GND can be applied to the bit lines L0 and L2, such that the array digit line pillars P1, P2, P3, P7, P8, and P9 will be shorted to GND via the corresponding transistors T1, T2, T3, T7, T8, and T9.

[0132] In this configuration, only the pillars P4 and P6 can become floating. The potential of the digit line P4 and P6 pillars will be determined by the capacitance ratio between the pillars and the WL (all unselected word lines biased at GND and one selected word line biased at -2.5V). Thus, the floating pillars can reach a small negative bias (e.g., -0.5V) that is safe for deselection. The other unaddressed pillars are grounded, i.e., also a safe condition for deselection.

[0133] If a positive polarity read mechanism (not shown in any of the figures) is employed, then similar bias conditions can be applied as described for programming the memory cells to the Figure 8B set state depicted in, but using smaller magnitudes of the word line and bit line pulses to avoid limiting all cells and instead only inducing snap-back on the set cells. For example, a positive word line read voltage V_WL of +2.5V can be applied to the selected word line SWL, a negative bit line read voltage of -2.5V can be applied to the selected bit line L1, a conduction voltage of +1.0V can be applied to the gate terminal of the selection transistor T5 coupled to the addressed digit line P5 via the row line R1; the bias conditions described above are suitable for applying a read voltage of +5.0V to the addressed cell. Different magnitudes can be used. Additionally, the unaddressed or unselected bit lines L0 and L2 can be biased at the ground voltage, and the unaddressed or unselected word lines R0 and R2 can be biased at a blocking or inhibiting voltage of, for example, -2.5V, resulting in all unaddressed or unselected digit lines floating.

[0134] The voltage values used in the above description are only example values and can vary while maintaining the scope of the present invention. In some cases, the ground voltage (GND) can be different from 0V; for example, the ground voltage can be a positive voltage or a negative voltage, and other positive or negative voltages are evaluated relative to the ground voltage. The same concepts and solutions described above can also be applied to array configurations different from the 3D memory device configuration depicted in the reference Figures 8A to 8D For example, it may be necessary to make minor adaptations to address 3D sub-pillars in a memory array similar to the reference Figures 4A to 7C described. In some cases, for a split-pillar architecture, a shared bit line can drive the gates of selector transistors (e.g., TFT transistors) as depicted in Figure 7A and 7B wherein at each stack or plane, even / odd cells are selected by even / odd digit lines; alternatively, even / odd sub-bit lines can independently drive the gates of selector transistors as depicted in Figure 7C Other pillar or sub-pillar decoding arrangements of selector transistors can also be implemented (e.g., different from the bit lines L0 to L2 / row lines R0 to R2 depicted in Figures 8A - 8D ).

[0135] It should be further noted (not shown in any of the figures) that selector transistors (e.g., pillar selection layers) can be formed at least partially on top of the memory layer - see Figure 3I to better identify the layers mentioned. For example, a TFT can be partially formed below the memory array (e.g., below the word line conductive material layer) (e.g., coupled to even bit lines / sub-pillars) and partially formed above the memory array (e.g., coupled to odd bit lines / sub-pillars). Additionally or alternatively, multiple building blocks each including a memory layer and a corresponding pillar selection layer can be arranged on top of each other in a building block stack. These arrangements will allow the same basic building block (e.g., containing a given number of memory stacks or layers and corresponding pillar selection) to be repeated several times during manufacturing to obtain a 3D memory array with an increased height (e.g., higher, with more stacks and layers) and thus an increased surface density. Bit lines for decoding different blocks and / or row lines of corresponding TFT selector transistors can be shared by all vertically stacked blocks (in which case word lines are decoded separately) or they can be separated for each stacked block (in which case word lines can be decoded jointly or individually). Connections to bit lines, row lines, and / or word lines can extend from a peripheral circuit layer in a substrate (e.g., a silicon substrate accommodating CMOS (CUA) circuitry below the array, e.g., decoding and sensing circuitry) to corresponding building blocks extending vertically adjacent to the memory array.

[0136] Figure 9A flowchart showing a method for accessing memory cells in a vertical 3D memory device having an NMOS TFT selector, as disclosed herein, is presented. The operations of method 900 may be implemented by one or more controllers associated with the memory device. In some instances, the one or more controllers may execute an instruction set to control one or more functional elements of the memory device to perform the described functions. Additionally or alternatively, the one or more controllers may use dedicated hardware to perform portions of the described functions.

[0137] At 910, method 900 may include applying a first voltage to a selected word line while other word lines are at a predetermined voltage. The operation of 910 may be performed according to the methods described herein.

[0138] At 930, method 900 may include applying a second voltage to the gate region of a TFT associated with other memory cells that share the selected word line with the memory cell. The operation of 930 may be performed according to the methods described herein.

[0139] At 950, method 900 may include applying a second voltage to the source region of a TFT associated with the memory cell that shares the selected word line while the source regions of other TFTs are at a predetermined voltage. The operation of 950 may be performed according to the methods described herein.

[0140] At 970, method 900 may include applying a third voltage to the gate region of a TFT associated with the memory cell. The operation of 970 may be performed according to the methods described herein.

[0141] In some cases, depending on the technology used, the first voltage may be +3.5V, the second voltage may be -3.5V, the third voltage may be +1V, and the predetermined voltage may be ground voltage.

[0142] In some cases, depending on the technology used, the first voltage may be +2.5V, the second voltage may be -2.5V, the third voltage may be +1V, and the predetermined voltage may be ground voltage.

[0143] In some cases, the first voltage may be -3.5V, the second voltage may be +3.5V, the third voltage may be +4.5V, and the predetermined voltage may be ground voltage.

[0144] In some cases, the first voltage may be -2.5V, the second voltage may be +2.5V, the third voltage may be +3.5V, and the predetermined voltage may be ground voltage.

[0145] Note that during the access process using a single NMOS TFT, for the unselected pillar receiving the 3.5V, the transistor channel may be blocked and no current can pass through, and thus it may not even be necessary to place the source region at GND. The corresponding NMOS TFT can remain floating. The floating pillars of the NMOS select transistors may pose a danger to the correct reading of the memory device. However, when the target cell is programmed, only the plate or plane of the selected word line is biased to 3.5V (as Figure 8A shown). Therefore, due to the capacitive coupling of all other plates or planes biased to ground, even the floating pillars are at a voltage close to ground and do not affect the function of the memory device.

[0146] The access scheme provided in this disclosure may further show that at least some of the pillars close to the selected pillar remain at a bias voltage close to ground and are not affected by the activities performed on the selected pillar.

[0147] Disclosed is a method for deselecting unaddressed memory cells in a 3D memory array, where multiple word lines extend horizontally on multiple stacks and multiple array digit lines extend vertically, and each memory cell is located at the intersection of a word line and an array digit line. The method includes: floating the array digit line among the multiple array digit lines coupled to the unaddressed memory cell.

[0148] In some embodiments, floating the array digit line includes applying a prohibit voltage to the gate of a thin film transistor (TFT) coupled between the array digit line and a bit line.

[0149] In some embodiments, the method further includes grounding the unselected word lines among the multiple word lines capacitively coupled to the array digit line.

[0150] In some embodiments, the method further includes deselecting a second unaddressed memory cell in the 3D memory array coupled to a second array digit line at least partially based on: applying a conduction voltage to a second thin film transistor (TFT) coupled between the second array digit line and a second bit line; grounding the second bit line; and grounding the second array digit line.

[0151] In some embodiments, the method further includes deselecting a second unaddressed memory cell by grounding the unselected word lines among the multiple word lines.

[0152] In some embodiments, the method further includes, during deselecting the unaddressed memory cells, selecting the addressed memory cells coupled to the selected digit lines, at least in part based on: applying a word line access voltage to a selected word line of the plurality of word lines; applying a bit line access voltage to a selected bit line coupled to the selected array digit line; and applying a turn-on voltage to a gate of a selected TFT coupled between the selected array digit line and the selected bit line to transfer the bit line access voltage to the selected array digit line.

[0153] For example, referring to the Figure 8B bias conditions described, a memory cell can be programmed to a set state (or it can be read according to a positive voltage read scheme) by applying voltages GND, -3.5V (read -2.5V), and GND to L0, L1, and L2, respectively, and applying voltages -3.5V, +1.0V, and -3.5V to R0, R1, and R2, respectively. An addressed word line in the 3D array can be biased to the desired word line access voltage (e.g., set +3.5V; or read +2.5V), while the unaddressed WLs can be grounded. This configuration will cause the array digit line P5 coupled to the addressed memory cell to be biased to the desired digit line access voltage (set -3.5V, or read -2.5V), and thus the overall desired voltage drop is obtained across the addressed memory cell. Memory cells coupled to different array digit lines (e.g., pillars P1, P2, P3, P4, P6, P7, P8, and P9) are not disturbed because the corresponding digit lines are floating, and their potential can be determined by the word line voltage weighted according to the capacitance ratio, and can differ very little from the ground voltage due to all WLs other than the addressed WL biased to the access voltage being grounded.

[0154] In a similar manner, referring to the Figure 8C (programmed to a reset state) and 8D (read according to a negative read scheme) bias conditions, a memory cell can be accessed by applying voltages GND, +3.5V (read +2.5V), and GND to L0, L1, and L2, respectively, and applying voltages +3.5V, +4.5V, and +3.5V to R0, R1, and R2, respectively. An addressed word line in the 3D array can be biased to the desired word line access voltage (e.g., set -3.5V; or read -2.5V), while the unaddressed WLs can be grounded. This configuration will cause the array digit line P5 coupled to the addressed memory cell to be biased to the desired digit line access voltage (set +3.5V, or read +2.5V), and thus the overall desired voltage drop is obtained across the addressed memory cell. Memory cells coupled to different array digit lines are not disturbed because the corresponding digit lines are grounded (e.g., pillars P1, P2, P3, P7, P8, and P9) or floating (e.g., pillars P6, P7).

[0155] In some embodiments, unaddressed memory cells may be coupled to an array digit line different from the array digit line to which addressed memory cells are coupled (e.g., a vertical pillar in a 3D memory array). The unaddressed memory cells may share the same word line with the addressed memory cells. By floating the digit line coupled to the unaddressed memory cell, a safety condition is established during access (e.g., read or program, e.g., set or reset) of the addressed memory cell to avoid or at least minimize interference to or from the unaddressed memory cell. The actual voltage of the floating digit line may depend on the voltage of the word line capacitively coupled to the floating digit line. Each word line may affect the voltage of the floating digit line through capacitive coupling, and since all unaddressed word lines may be grounded while only the addressed word line may be biased to a read / program access voltage, the actual voltage of the floating digit line remains close to ground. In some configurations, a portion of the digit line coupled to the unaddressed cell may be grounded, thus also providing a safe and interference-free situation. Additionally, memory cells coupled to unaddressed word lines (e.g., word lines in different stacks or planes) that include memory cells sharing the same digit line with the addressed memory cell may be kept in a safe and interference-free situation by grounding the unaddressed word line to which they are coupled. The steps of the methods described above may be performed in an order different from the order described. Additional steps not yet described may be performed.

[0156] The description provided herein enables a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: A memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, where the memory cells are configured to be accessed via a word line and a digit line that are orthogonal to each other, and the digit line is a vertically extending conductive pillar; A pillar selection layer in which a plurality of thin film transistors TFTs for accessing the memory cells are formed; A peripheral circuit layer formed below the pillar selection layer and having sense amplifiers and decoding circuitry for a plurality of word lines and a plurality of digit lines of the memory device, where each of the plurality of digit lines is a different vertically extending conductive pillar; and A matrix of the plurality of TFTs located below and above the plurality of digit lines, where each of the plurality of conductive pillars is associated with a corresponding TFT of the plurality of TFTs.

2. The memory device according to claim 1, wherein: The corresponding TFT is an n-type metal oxide semiconductor (NMOS) transistor, where the drain region is coupled to the conductive pillar.

3. The memory device according to claim 2, wherein: The corresponding TFT has two gate regions that are parallel to a first gate oxide on a first side of the channel region and a second gate oxide on a second side of the channel region.

4. The memory device according to claim 2, wherein: The channel region is formed below the drain region, and the source region is formed below the channel region.

5. The memory device according to claim 1, wherein: The conductive pillar further includes a first sub-pillar and a second sub-pillar different from the first sub-pillar, and the corresponding TFT is a first TFT configured for the first sub-pillar; and The memory device further includes a second TFT of a matrix of the TFTs configured for the second sub-pillar.

6. The memory device according to claim 1, wherein: The pitch of the plurality of TFTs matches the pitch of the conductive pillars.

7. The memory device according to claim 1, wherein the TFT is formed in a polysilicon layer.

8. The memory device according to claim 1, wherein the peripheral circuit layer is implemented in a silicon substrate layer.

9. A memory device, comprising: A memory array of memory cells structured as a vertical three-dimensional (3D) memory, including a plurality of word lines configured to be orthogonal to a plurality of digit lines, each digit line intersecting two or more word lines; A matrix of thin film transistors TFTs located below and above the plurality of digit lines, where each of the plurality of digit lines is associated with a corresponding TFT of the matrix of TFTs; and A selection transistor located at one end of a corresponding digit line, the selection transistor being a TFT for selecting the corresponding digit line and accessing at least the memory cells associated with the corresponding digit line.

10. The memory device according to claim 9, further comprising: A peripheral circuitry formed below the matrix of TFTs, the peripheral circuitry having sense amplifiers and decoding circuitry for the plurality of word lines and the plurality of digit lines.

11. The memory device according to claim 9, wherein the TFT is formed in a polysilicon layer.

12. The memory device according to claim 9, further comprising a peripheral circuit layer having a sense amplifier and a decoding circuit system implemented in a silicon substrate.

13. The memory device according to claim 9, wherein: The TFT is an n-type metal oxide semiconductor (NMOS) transistor, where the drain region is coupled to the corresponding digit line.

14. The memory device according to claim 9, wherein the TFT includes two gate regions parallel to a first gate oxide adjacent to a first side of the channel region and a second gate oxide adjacent to a second side of the channel region.

15. The memory device according to claim 9, further comprising: A stack of a plurality of building blocks, each building block including: A corresponding memory layer in which corresponding pluralities of word lines are configured to be orthogonal to corresponding pluralities of digit lines, each of the corresponding pluralities of digit lines intersecting two or more of the corresponding pluralities of word lines; and A corresponding pillar selection layer having a corresponding plurality of TFTs, each TFT for selecting the corresponding digit line of the corresponding pluralities of digit lines.

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