Method for testing the connectivity of a semiconductor structure and testing system thereof

Abstract

Embodiments of the present application relate to the field of semiconductor, and provide a method for testing the connectivity of a semiconductor structure and a testing system thereof. The method comprises: providing a semiconductor structure and a detection transistor, the semiconductor structure comprising a through-silicon via structure having a first end and a second end opposite to each other, and the detection transistor having a detection gate, a first port and a second port, the detection gate being configured to receive a test signal, the first port being configured to receive an operating voltage, and the second port being electrically connected to the first end; obtaining an intrinsic conductance factor of the detection transistor; turning on the detection transistor by receiving the test signal and providing a test voltage to the second port, so that the detection transistor operates in a deep triode region, and obtaining a current flowing through the second port during the operation of the detection transistor in the deep triode region; and obtaining a resistance of the through-silicon via structure based on the intrinsic conductance factor, the operating voltage, the test voltage and the current flowing through the second port. The embodiments of the present application detect the resistance of the through-silicon via structure to test the connectivity of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a method and system for testing the connectivity of semiconductor structures. Background Technology

[0002] As the integration density of semiconductor structures increases, through-silicon vias (TSVs) are typically used to penetrate multiple stacked chips, allowing these chips to be electrically connected to each other to form a 3D semiconductor structure comprising multiple stacked chips. Because the semiconductor structure includes multiple TSVs, the chips can receive various signals via these TSVs.

[0003] However, on the one hand, TSVs themselves may have various defects, resulting in a decrease in their conductivity and thus reducing the connectivity between chips that rely on TSV electrical connections. On the other hand, incorrect TSV connections, such as when the chip actually connected to the TSV differs from the chip required for TSV connections in the design, will also reduce the yield of the semiconductor structure. Both of these factors will affect the operating speed of the semiconductor structure.

[0004] Therefore, a testing method is needed to detect the interconnectivity between chips in a semiconductor structure, thereby determining whether the semiconductor structure is of acceptable quality. Summary of the Invention

[0005] This application provides a method and system for testing the connectivity of semiconductor structures, which is at least advantageous for detecting the connectivity of semiconductor structures by obtaining the resistance value of the silicon through-hole structure.

[0006] According to some embodiments of this application, one aspect of this application provides a method for testing the connectivity of a semiconductor structure, comprising: providing a semiconductor structure and a detection transistor, the semiconductor structure including a silicon through-hole structure having opposing first and second ends, the detection transistor having a detection gate, a first port, and a second port, the detection gate being used to receive a test signal, the first port being used to receive an operating voltage, and the second port being electrically connected to the first end; obtaining the intrinsic conductivity factor of the detection transistor, the intrinsic conductivity factor being the product of the carrier mobility and the capacitance per unit area of ​​the gate oxide layer under the condition that the detection transistor operates in the saturation region and the current in the detection transistor has a first current direction; the detection transistor receiving the test signal and turning on, and providing a test voltage to the second end, such that the current in the detection transistor has a second current direction, the first current direction being opposite to the second current direction, so that the detection transistor operates in the deep transistor region, and obtaining the current flowing through the second end during the detection transistor operating in the deep transistor region; and obtaining the resistance of the silicon through-hole structure based on the intrinsic conductivity factor, the operating voltage, the test voltage, and the current flowing through the second end.

[0007] According to some embodiments of this application, another aspect of this application provides a test system for detecting the connectivity of a semiconductor structure, comprising: a semiconductor structure including a silicon through-hole structure having opposing first and second ends, the first end being electrically connected to a first chip and the second end being electrically connected to a second chip; a detection transistor located in the first chip, the detection transistor including: a detection gate, a first port, and a second port, the detection gate being used to receive a test signal, the first port being used to receive an operating voltage, and the second port being electrically connected to the first end; a test voltage application module, which provides a test voltage to the second end when the detection transistor is turned on by receiving the test signal, causing the detection transistor to operate in a deep transistor region; a current acquisition module, which acquires the current flowing through the second end during the operation of the detection transistor in the deep transistor region; and a resistance acquisition module, which acquires the resistance of the silicon through-hole structure based on the intrinsic conductivity factor, the operating voltage, the test voltage, and the current flowing through the second end.

[0008] The technical solution provided in this application has at least the following advantages:

[0009] In the above technical solution, a detection transistor is provided, and its second port is electrically connected to the first port of the through-silicon via (TSV) structure. The detection gate of the detection transistor receives a test signal, which is used to turn on the detection transistor. Then, a test voltage is provided at the second port of the TSV structure to change the operating state of the detection transistor, causing it to operate in the deep transistor region. By acquiring the current flowing through the second port during the deep transistor region and the intrinsic conductivity of the detection transistor, the resistance of the TSV structure is obtained. By comparing the actual resistance value of the TSV structure with the ideal resistance value, the connectivity of the semiconductor structure can be determined. Furthermore, by judging the difference between the actual and ideal resistance values, the cause of connectivity problems in the semiconductor structure can be preliminarily inferred, allowing for targeted repair of the semiconductor structure. Additionally, when the semiconductor structure is in normal operating mode, the detection transistor can be turned off by the test signal, thus not affecting the normal operation of the semiconductor structure. Attached Figure Description

[0010] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0011] Figure 1 A flowchart for testing the connectivity of a semiconductor structure provided in one embodiment of this application;

[0012] Figure 2 This is a schematic block diagram illustrating the configuration of a circuit for testing the connectivity of a semiconductor structure according to an embodiment of this application;

[0013] Figure 3 A schematic diagram of the functional modules of a test system for detecting the connectivity of semiconductor structures provided in another embodiment of this application. Detailed Implementation

[0014] As can be seen from the background technology, there is currently a need for a method to test the connectivity of semiconductor structures.

[0015] Analysis revealed that when using through-silicon vias (TSVs) to connect chips in semiconductor structures, defects in the TSVs and improper connections between the TSVs and the chip can negatively impact the operating speed of the semiconductor structure. Defects in the TSVs include voids created by incomplete filling of the conductive material within the TSV, cracks in the TSV itself, and contact failures between the TSV and the chip due to chip warping or bump material migration. Improper connections between the TSV and the chip can lead to short circuits in the TSV.

[0016] Therefore, a method for testing the connectivity of semiconductor structures is needed to determine whether the connectivity of the semiconductor structure is good by measuring the resistance of the silicon through-hole structure.

[0017] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0018] This application provides a method for testing the connectivity of semiconductor structures according to an embodiment. The method for testing the connectivity of semiconductor structures according to an embodiment of this application will be described in detail below with reference to the accompanying drawings. Figure 1 A flowchart for testing the connectivity of a semiconductor structure provided in one embodiment of this application; Figure 2 This is a schematic block diagram illustrating the configuration of a circuit for testing the connectivity of a semiconductor structure according to an embodiment of this application.

[0019] Reference Figure 1 and Figure 2 The testing method for semiconductor structure connectivity includes the following steps:

[0020] S101: Provide a semiconductor structure 100 and a detection transistor 101. The semiconductor structure 100 includes a silicon through-hole structure 102 having a first end 112 and a second end 122. The detection transistor 101 has a detection gate 111, a first port 121 and a second port 131. The detection gate 111 is used to receive a test signal, the first port 121 is used to receive an operating voltage, and the second port 131 is electrically connected to the first end 112.

[0021] In some embodiments, the semiconductor structure may further include a first electrical connection layer 113, with the second port 131 and the first end 112 both electrically connected to the first electrical connection layer 113, so that the second port 131 is electrically connected to the first end 112.

[0022] S102: Obtain the intrinsic conductivity factor of the detection transistor 101. The intrinsic conductivity factor is the product of the carrier mobility and the capacitance of the gate oxide layer per unit area, under the condition that the detection transistor 101 is operating in the saturation region and the current in the detection transistor 101 has a first current direction X.

[0023] The detection transistor 101 is a PMOS transistor (P-channel metal-oxide-semiconductor field-effect transistor). The testing method also includes providing a standard PMOS transistor with standard aspect ratio, standard saturation current, standard gate-source voltage, and standard threshold voltage. The intrinsic conductivity of the detection transistor 101 is the same as that of the standard PMOS transistor. It should be noted that the standard PMOS transistor is provided by a foundry; therefore, the standard aspect ratio, standard saturation current, standard gate-source voltage, and standard threshold voltage are basic performance parameters provided by the foundry and do not require manual measurement.

[0024] The specific steps for obtaining the intrinsic conductivity factor of the detection transistor 101 are as follows:

[0025] The intrinsic conductivity factor is obtained based on the standard gate-source voltage, standard width-to-length ratio, standard saturation current, and standard threshold voltage. The intrinsic conductivity factor, standard gate-source voltage, standard width-to-length ratio, standard saturation current, and standard threshold voltage satisfy the following relationship:

[0026]

[0027] Among them, I Dsat The standard saturation current is given by A, the intrinsic conductivity factor is given by W / L, and the standard width-to-length ratio is given by V. GS For standard gate-source voltage, V TH This is the standard threshold voltage. Due to the standard width-to-length ratio (W / L) and standard saturation current (I)... Dsat Standard gate-source voltage V GS and standard threshold voltage V TH Since all values ​​are known, the intrinsic conductivity factor A of the standard PMOS transistor, i.e. the intrinsic conductivity factor of the detection transistor 101, can be calculated using the above relationship.

[0028] S103: The detection transistor 101 receives the test signal and turns on, and provides a test voltage to the second terminal 122, so that the current in the detection transistor 101 has a second current direction, and the first current direction X is opposite to the second current direction, so that the detection transistor 101 operates in the deep transistor region, and acquires the current flowing through the second terminal 122 during the period when the detection transistor 101 operates in the deep transistor region.

[0029] In some embodiments, the testing method may further include providing a test signal application structure 114 for applying a test signal to the detection gate 111 of the detection transistor 101. The semiconductor structure may also include a second electrical connection layer 123, and the apparatus provides a first probe and makes the first probe electrically connected to the second electrical connection layer 123 for applying a test voltage to the second electrical connection layer 123, thereby providing a test voltage to the second terminal 122; the semiconductor structure may also include a probe contact point 105, and the apparatus provides a second probe and makes the second probe electrically connected to the probe contact point 105 for acquiring the current flowing through the probe contact point 105 during the operation of the detection transistor 101 in the deep transistor region, thereby acquiring the current flowing through the second terminal 122 during the operation of the detection transistor 101 in the deep transistor region. In other embodiments, the apparatus provides a first probe that can directly contact the second terminal to apply a test voltage to the second terminal; the apparatus also provides a second probe that directly contacts the second terminal for acquiring the current flowing through the second terminal during the operation of the detection transistor in the deep transistor region.

[0030] When the detection transistor 101 is a PMOS transistor, a low-level test signal turns on the detection transistor 101, and the test voltage is greater than the operating voltage. When the detection transistor 101 operates in the deep transistor region, the direction of the second current is from the second port 131 to the first port 121. Furthermore, when the semiconductor structure 100 is in normal operating mode, a high-level test signal can be used to turn off the detection transistor 101, thus not affecting the normal operation of the semiconductor structure 100.

[0031] A PMOS transistor operating in the deep triode region can be regarded as an equivalent controllable resistor controlled by the overdrive voltage. When the gate-source voltage is constant, the channel DC on-resistance is approximately a constant resistance.

[0032] Therefore, before obtaining the resistance of the silicon through-hole structure 102, the test method further includes: when the detection transistor 101 is operating in the deep transistor region, obtaining the equivalent resistance of the detection transistor 101 based on the intrinsic conductivity factor, the operating voltage and the threshold voltage of the detection transistor 101.

[0033] Specifically, the equivalent resistance of the detection transistor 101 can be calculated using the following formula:

[0034]

[0035] Among them, R on To detect the equivalent resistance of transistor 101, A is the intrinsic conductivity factor, and W... p / L P To detect the aspect ratio of transistor 101, V G1To detect the voltage at the gate 111 when transistor 101 is turned on, V TH For the standard threshold voltage, V DD This is the operating voltage. It should be noted that the standard threshold voltage V... TH It is the same as the threshold voltage of the detection transistor 101.

[0036] It should be noted that the aspect ratio W of the detection transistor 101 is... p / L P To obtain the ideal resistance of the silicon through-hole structure 102 as needed, a detection transistor 101 of suitable size is designed. In practical applications, the aspect ratio W of the detection transistor 101 varies depending on the ideal resistance of different silicon through-hole structures 102. p / L P They can be different.

[0037] Among them, the voltage V of the gate 111 is detected when the detection transistor 101 is turned on. G1 It is 0V.

[0038] therefore,

[0039] S104: Obtain the resistance of the silicon through-hole structure 102 based on the intrinsic conductivity factor, operating voltage, test voltage, and current flowing through the second terminal 122.

[0040] Specifically, the resistance of the through-silicon via structure can be calculated using the following formula:

[0041]

[0042] Among them, R on To detect the equivalent resistance of transistor 101, i D V is the current flowing through the second terminal 122. TSV For testing voltage, V DD R is the operating voltage. TSV The resistor is for the silicon through-hole structure 102.

[0043] Obtain the resistance R of the silicon through-hole structure 102 TSV After that, R TSV By comparing the resistance value with that of an ideal through-silicon via structure 102, it is possible to determine whether the interconnectivity of the semiconductor structure 100 is good. Furthermore, the resistance value can be determined by judging R... TSV The magnitude of the difference between the resistance value of the obtained through-silicon via (TSV) structure 102 and the ideal resistance value of the TSV structure 102 can be used to preliminarily deduce the cause of the connectivity problem in the semiconductor structure 100, thereby enabling targeted repairs to the semiconductor structure 100. For example, in some embodiments, when the obtained resistance R of the TSV structure 102 is significantly different from the ideal resistance value of the TSV structure 102, the cause of the connectivity problem in the semiconductor structure 100 can be determined. TSV The resistance is far lower than that of an ideal through-silicon via structure 102, R TSVIf the resistance R of the obtained through-silicon via (TSV) structure 102 is zero, it can be preliminarily determined that the TSV structure 102 is not properly connected to other conductive structures in the semiconductor structure 100, causing the TSV structure 102 to short-circuit due to the influence of other conductive structures in the semiconductor structure 100. Based on this preliminary judgment, the circuit connected to the TSV structure 102 in the semiconductor structure 100 is then investigated. In other embodiments, when the resistance R of the obtained TSV structure 102 is zero... TSV If the resistance value is greater than that of the ideal silicon through-hole structure 102, it can be preliminarily determined that the voids are caused by incomplete filling of the conductive material in the silicon through-hole structure 102, or by a partial breakage of the silicon through-hole structure 102 itself, or by poor contact between the silicon through-hole structure 102 and the first electrical connection layer 113 or the second electrical connection layer 123 due to warping or migration. Based on this preliminary judgment, the defective silicon through-hole structure 102 is replaced, or the connection strength between the silicon through-hole structure 102 and the first electrical connection layer 113 or the second electrical connection layer 123 is enhanced. In other embodiments, when the resistance R of the obtained silicon through-hole structure 102 is greater than that of the ideal silicon through-hole structure 102, it can be determined that the voids are caused by incomplete filling of the conductive material in the silicon through-hole structure 102, or by a partial breakage of the silicon through-hole structure 102 itself, or by poor contact between the silicon through-hole structure 102 and the first electrical connection layer 113 or the second electrical connection layer 123. TSV When the value approaches infinity, it can be preliminarily determined that the silicon through-hole structure 102 is not electrically connected to the first electrical connection layer 113 or the second electrical connection layer 123, or that the silicon through-hole structure 102 itself is broken, causing the circuit formed by the detection transistor 101 and the silicon through-hole structure 102 to be open. Based on this preliminary judgment, the silicon through-hole structure 102 that is broken is replaced, or the silicon through-hole structure 102 is electrically connected to both the first electrical connection layer 113 and the second electrical connection layer 123.

[0044] Therefore, the embodiments of this application are not only advantageous in obtaining the resistance value R of the through-silicon via structure 102 TSV To detect the connectivity of semiconductor structure 100, it can also be based on R TSV By analyzing the difference between the resistance value of the ideal silicon through-hole structure 102 and the resistance value of the semiconductor structure 100, the cause of the connectivity problem in the semiconductor structure 100 can be preliminarily inferred, thereby allowing for targeted repair of the semiconductor structure 100.

[0045] Continue to refer to Figure 1 The test method may further include: providing a calibration transistor 106, which has a calibration gate 116, a third port 126 and a fourth port 136, wherein the calibration gate 116 is used to receive a control signal, the third port 126 is used to receive a calibration working voltage, and the fourth port 136 is electrically connected to the second terminal 122; when the detection transistor 101 is turned on to receive a test signal, the calibration transistor 106 is turned off to receive a control signal.

[0046] In some embodiments, the test method may further include providing a control signal application structure 124 for applying a control signal to the calibration gate 116 of the calibration transistor 106.

[0047] In this transistor, the calibration transistor 106, like the detection transistor 101, is a PMOS transistor. When the detection transistor 101 operates in the deep transistor region, the test signal is low and the control signal is high, causing the calibration transistor 106 to be in the off state. When the test signal is high, the detection transistor 101 is in the off state, and the control signal is low, causing the calibration transistor 106 to operate in the deep transistor region.

[0048] After obtaining the resistance of the silicon through-hole structure 102, the testing method may further include: obtaining the intrinsic conductivity factor of the calibration transistor 106, wherein the intrinsic conductivity factor is the product of the carrier mobility and the capacitance per unit area of ​​the gate oxide layer under the condition that the calibration transistor 106 operates in the saturation region and the current in the calibration transistor 106 has a third current direction; changing the test signal to make the detection transistor 101 turn off; simultaneously changing the control signal to make the calibration transistor 106 turn on and provide a calibration test voltage to the first terminal 112, so that the current in the calibration transistor 106 has a fourth current direction, the third current direction being opposite to the fourth current direction, so that the calibration transistor 106 operates in the deep transistor region, and obtaining the calibration current flowing through the first terminal 112 during the period when the calibration transistor 106 operates in the deep transistor region; and obtaining the calibration resistance of the silicon through-hole structure 102 based on the intrinsic conductivity factor, the calibration operating voltage, the calibration test voltage, and the calibration current flowing through the first terminal 112.

[0049] Since both calibration transistor 106 and detection transistor 101 are PMOS transistors, the method for obtaining the intrinsic conductivity factor of calibration transistor 106 is the same as the method for obtaining the intrinsic conductivity factor of detection transistor 101, and will not be repeated here.

[0050] In some embodiments, after acquiring the current flowing through the second terminal 122 during the operation of the detection transistor 101 in the deep bipolar region, the first and second probes provided by the instrument are removed, and a third probe is provided by the instrument, making the third probe electrically connected to the first electrical connection layer 113 to apply a calibration test voltage to the first electrical connection layer 113, thereby providing a calibration test voltage to the first terminal 112; the instrument also provides a fourth probe, making the fourth probe electrically connected to the first electrical connection layer 113 to acquire the current flowing through the probe contact point 105 during the operation of the calibration transistor 106 in the deep bipolar region, thereby acquiring the current flowing through the first electrical connection layer 113 during the operation of the calibration transistor 106 in the deep bipolar region. In other embodiments, the instrument provides a third probe that can directly contact the first terminal to apply the calibration test voltage to the first terminal; the instrument also provides a fourth probe, making the fourth probe directly contact the first terminal to acquire the current flowing through the first terminal during the operation of the calibration transistor in the deep bipolar region.

[0051] When the calibration transistor 106 operates in the deep transistor region, the calibration test voltage is greater than the calibration operating voltage, and the direction of the fourth current is from the fourth port 136 to the third port 126. Furthermore, when the semiconductor structure 100 is in normal operating mode, both the test signal and the control signal can be at a high level, so that both the detection transistor 101 and the calibration transistor 106 are in the off state, thus not affecting the normal operation of the semiconductor structure 100.

[0052] Specifically, the equivalent resistance of the calibration transistor 106 can be calculated using the following formula:

[0053]

[0054] Among them, R′ on To calibrate the equivalent resistance of transistor 106, A′ is the intrinsic conductivity factor of transistor 106, and W′ is... P / L′ p To calibrate the aspect ratio of transistor 106, V′ G1 To calibrate the voltage at the gate 116 when transistor 106 is turned on, V′ TH To calibrate the threshold voltage of transistor 106, V′ DD To calibrate the operating voltage. It should be noted that the threshold voltage V′ of transistor 106 is being calibrated. TH Compared with the standard threshold voltage V TH same.

[0055] It should be noted that the aspect ratio W′ of the calibration transistor 106 P / L′ pTo obtain the ideal resistance of the silicon through-hole structure 102 as needed, a calibration transistor 106 of suitable size is designed. In practical applications, the aspect ratio W′ of the calibration transistor 106 varies depending on the ideal resistance of different silicon through-hole structures 102. P / L′ p They can be different.

[0056] Among them, the voltage V′ of the calibration gate 116 when the calibration transistor 106 is turned on. G1 It is 0V.

[0057] therefore,

[0058] Furthermore, the calibration resistance of the silicon through-hole structure can be calculated using the following formula:

[0059]

[0060] Among them, R′ on To calibrate the equivalent resistance of transistor 106, i′ D V′ is the current flowing through the first terminal 112. TSV To calibrate the test voltage, V′ DD To calibrate the operating voltage, R′ TSV This is the calibration resistor for the silicon through-hole structure 102.

[0061] After obtaining the calibration resistor of the through-silicon via (TSV) structure 102, the resistance R of the TSV structure 102 is compared. TSV The calibration resistor R′ of the silicon through-hole structure 102 TSV Used to determine the resistance R of the obtained silicon through-hole structure 102 TSV The accuracy, when R TSV With R′ TSV When the difference is large, for example, R TSV With R′ TSV The difference between R TSV When the ratio is greater than 5%, the obtained R TSV Or R′ TSV Inaccurate; by checking the connections between the structures in the testing method, a new R is obtained. TSV With R′ TSV The ratio is beneficial to improving the accuracy of the resistance of the silicon through-hole structure 102 obtained by the test method provided in this application.

[0062] In summary, based on the basic performance parameters of the PMOS transistor provided by the foundry, the intrinsic conductivity of the detection transistor 101 is obtained. By adjusting the test signal and applying a test voltage to the second terminal 122 of the through-silicon via (TSV) structure 102, the detection transistor 101 is made to operate in the deep transistor region, thereby obtaining the equivalent resistance of the detection transistor 101. The current flowing through the second terminal 122 during the operation of the detection transistor 101 in the deep transistor region is obtained. Based on the intrinsic conductivity of the detection transistor 101, the operating voltage, the test voltage, and the current flowing through the second terminal 122, the resistance of the TSV structure 102 is obtained. By comparing the obtained resistance of the TSV structure 102 with the ideal resistance of the TSV structure 102, it is possible to determine whether the connectivity of the semiconductor structure 100 is good. Furthermore, by judging the magnitude of the difference between the obtained resistance of the TSV structure 102 and the ideal resistance of the TSV structure 102, the cause of the connectivity problem in the semiconductor structure 100 can be preliminarily inferred, thereby allowing for targeted repair of the semiconductor structure 100. Furthermore, when the semiconductor structure 100 is in normal operating mode, the detection transistor 101 can be turned off by a test signal, so as not to affect the normal operation of the semiconductor structure 100.

[0063] Another embodiment of this application provides a test system for detecting the connectivity of semiconductor structures, used to implement the above-described test method for detecting the connectivity of semiconductor structures. Figure 3 A schematic diagram of the functional modules of a test system for detecting the connectivity of semiconductor structures provided in another embodiment of this application.

[0064] Reference Figure 2 and Figure 3 The test system 109 for detecting the connectivity of semiconductor structures includes: a semiconductor structure 100, which includes a silicon through-hole structure 102 having a first end 112 and a second end 122, the first end 112 being electrically connected to a first chip 110, and the second end 122 being electrically connected to a second chip 120; and a detection transistor 101 located in the first chip 110, which includes a detection gate 111, a first port 121, and a second port 131, the detection gate 111 being used to receive test signals, the first port 121 being used for... The second port 131 is electrically connected to the first terminal 112 to receive the operating voltage; the test voltage application module 107 provides a test voltage to the second terminal 122 when the detection transistor 101 is turned on to receive the test signal, so that the detection transistor operates in the deep transistor region; the current acquisition module 117 is used to acquire the current flowing through the second terminal during the period when the detection transistor is operating in the deep transistor region; the resistance acquisition module 127 acquires the resistance of the silicon through-hole structure 102 based on the intrinsic conductivity factor, the operating voltage, the test voltage and the current flowing through the second terminal 122.

[0065] The detection transistor 101 is a PMOS transistor. Its first port 121 receives the operating voltage, and its detection gate 111 receives the test signal, causing the detection transistor 101 to conduct. When no test voltage is supplied to the second port 122, the detection transistor 101 operates in the saturation region, and the current in the detection transistor 101 has a first current direction. The test voltage application module 107 is used to change the operating state of the detection transistor 101. Specifically, the test voltage application module 107 supplies a test voltage to the second port 122, causing the current in the detection transistor 101 to have a second current direction. The first current direction is opposite to the second current direction, so that the detection transistor 101 operates in the deep transistor region.

[0066] In some embodiments, the test system 109 may further include a calibration transistor 106 located in the second chip 120. The calibration transistor 106 includes a calibration gate 116, a third port 126, and a fourth port 136. The calibration gate 116 is used to receive a control signal, the third port 126 is used to receive a calibration working voltage, and the fourth port 136 is electrically connected to the second terminal 122. When the detection transistor 101 receives a test signal and is turned on, the calibration transistor 106 receives a control signal and is in a cut-off state.

[0067] The test system 109 may further include: a calibration test voltage application module 108, which provides a calibration test voltage to the first terminal 112 when the detection transistor 101 is in the off state and the calibration transistor 106 is in the on state when it receives a test signal, so that the calibration transistor 106 operates in the deep transistor region; a calibration current acquisition module 118, which acquires the current flowing through the first terminal 112 during the period when the calibration transistor 106 operates in the deep transistor region; and a calibration resistance acquisition module 128, which acquires the calibration resistance of the through-silicon via structure 102 based on the calibration intrinsic conductivity factor, the calibration operating voltage, the calibration test voltage, and the current flowing through the first terminal 112. The calibration transistor 106, like the detection transistor 101, is a PMOS transistor.

[0068] The third port 126 receives the calibration operating voltage, and the calibration gate 116 receives a control signal, causing the calibration transistor 106 to conduct. When no calibration test voltage is provided to the first terminal 112, the calibration transistor 106 operates in the saturation region, and the current in the calibration transistor 106 has a third current direction. The calibration test voltage application module 108 is used to change the operating state of the calibration transistor 106. Specifically, the calibration test voltage application module 108 provides a calibration test voltage to the first terminal 112, causing the current in the calibration transistor 106 to have a fourth current direction, which is opposite to the third current direction, so that the calibration transistor 106 operates in the deep transistor region.

[0069] In summary, by adjusting the test signal and applying a test voltage to the second terminal 122 of the through-silicon via (TSV) structure 102 via the test voltage application module 107, the detection transistor 101 is made to operate in the deep transistor region. The current flowing through the second terminal 122 during the operation of the detection transistor 101 in the deep transistor region is acquired by the current acquisition module 117. The resistance of the TSV structure 102 is acquired by the resistance acquisition module 127 based on the intrinsic conductivity factor of the detection transistor 101, the operating voltage, the test voltage, and the current flowing through the second terminal 122. By comparing the acquired resistance of the TSV structure 102 with the ideal resistance of the TSV structure 102, the connectivity of the semiconductor structure 100 can be determined. Furthermore, by judging the magnitude of the difference between the acquired resistance of the TSV structure 102 and the ideal resistance of the TSV structure 102, the cause of the connectivity problem in the semiconductor structure 100 can be preliminarily inferred, thereby allowing for targeted repair of the semiconductor structure 100.

[0070] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for testing the connectivity of a semiconductor structure, characterized in that, include: A semiconductor structure and a detection transistor are provided. The semiconductor structure includes a through-silicon via structure having opposing first and second ends. The detection transistor has a detection gate, a first port, and a second port. The detection gate is used to receive a test signal, the first port is used to receive an operating voltage, and the second port is electrically connected to the first end. The intrinsic conductivity factor of the detection transistor is obtained. The intrinsic conductivity factor is the product of the carrier mobility and the capacitance of the gate oxide layer per unit area, under the condition that the detection transistor is operating in the saturation region and the current in the detection transistor has a first current direction. The detection transistor receives the test signal and turns on, and provides a test voltage to the second terminal, so that the current in the detection transistor has a second current direction, the first current direction being opposite to the second current direction, so that the detection transistor operates in the deep transistor region, and acquires the current flowing through the second terminal during the period when the detection transistor operates in the deep transistor region; The resistance of the silicon through-hole structure is obtained based on the intrinsic conductivity factor, the operating voltage, the test voltage, and the current flowing through the second terminal.

2. The test method as described in claim 1, characterized in that, After obtaining the intrinsic conductivity factor and before obtaining the resistance of the through-silicon via structure, the method further includes: when the detection transistor is operating in the deep transistor region, obtaining the equivalent resistance of the detection transistor based on the intrinsic conductivity factor, the operating voltage, and the threshold voltage of the detection transistor.

3. The test method as described in claim 2, characterized in that, The detection transistor is a PMOS transistor. The test voltage is greater than the operating voltage. When the detection transistor is operating in the deep transistor region, the direction of the second current is from the second port to the first port.

4. The test method as described in claim 3, characterized in that, Also includes: A standard PMOS transistor is provided, the standard PMOS transistor having a standard aspect ratio, standard saturation current, standard gate-source voltage, and standard threshold voltage. The intrinsic conductivity factor of the detection transistor is the same as that of the standard PMOS transistor. Obtaining the intrinsic conductivity factor of the detection transistor includes: The intrinsic conductivity factor is obtained based on the standard gate-source voltage, the standard width-to-length ratio, the standard saturation current, and the standard threshold voltage. The intrinsic conductivity factor, the standard gate-source voltage, the standard width-to-length ratio, the standard saturation current, and the standard threshold voltage satisfy the following relationship: in, The standard saturation current, The intrinsic conductivity factor is... The standard width-to-length ratio, The standard gate-source voltage, The standard threshold voltage is denoted as .

5. The test method as described in claim 4, characterized in that, The step of obtaining the equivalent resistance of the detection transistor includes: The equivalent resistance of the detection transistor is calculated according to the following formula: in, The equivalent resistance of the detection transistor. The intrinsic conductivity factor is... The aspect ratio of the detection transistor is [missing information]. The voltage at the detection gate when the detection transistor is turned on. The standard threshold voltage, The operating voltage is [value].

6. The test method as described in claim 5, characterized in that, When the detection transistor is turned on, the voltage of the detection gate is 0V.

7. The test method as described in claim 6, characterized in that, The step of obtaining the resistance of the through-silicon via structure includes: The resistance of the through-silicon via structure is calculated using the following formula: in, The equivalent resistance of the detection transistor. The current flowing through the second terminal, The test voltage is... The operating voltage is... The resistance of the silicon through-hole structure is given.

8. The test method as described in claim 1, characterized in that, It also includes: providing a calibration transistor having a calibration gate, a third port and a fourth port, the calibration gate being used to receive a control signal, the third port being used to receive a calibration operating voltage, and the fourth port being electrically connected to the second terminal; When the detection transistor receives the test signal and is turned on, the calibration transistor receives the control signal and is in the off state.

9. The test method as described in claim 8, characterized in that, Both the detection transistor and the calibration transistor are PMOS transistors. When the detection transistor is operating in the deep transistor region, the test signal is low and the control signal is high, causing the calibration transistor to be in the off state.

10. The test method as described in claim 9, characterized in that, After obtaining the resistance of the through-silicon via structure, the process further includes: The intrinsic conductivity factor of the calibration transistor is obtained. The intrinsic conductivity factor is the product of the carrier mobility and the capacitance per unit area of ​​the gate oxide layer under the condition that the calibration transistor is operating in the saturation region and the current in the calibration transistor has a third current direction. The test signal is changed to put the detection transistor in the off state; Simultaneously, the control signal is changed to turn on the calibration transistor and provide a calibration test voltage to the first terminal, so that the current in the calibration transistor has a fourth current direction, the third current direction being opposite to the fourth current direction, so that the calibration transistor operates in the deep transistor region, and the calibration current flowing through the first terminal during the period when the calibration transistor operates in the deep transistor region is obtained. The calibration resistance of the through-silicon via structure is obtained based on the calibration intrinsic conductivity factor, the calibration operating voltage, the calibration test voltage, and the calibration current flowing through the first terminal.

11. The test method as described in claim 10, characterized in that, After obtaining the calibration resistor of the through-silicon via structure, the process further includes: The accuracy of the obtained resistance of the silicon through-hole structure is determined by comparing the resistance of the silicon through-hole structure with the calibration resistance of the silicon through-hole structure.

12. A test system for detecting the connectivity of semiconductor structures, characterized in that, include: A semiconductor structure, the semiconductor structure including a silicon through-hole structure having a first end and a second end opposite to each other, the first end being electrically connected to a first chip and the second end being electrically connected to a second chip; A detection transistor is located in the first chip. The detection transistor includes a detection gate, a first port, and a second port. The detection gate is used to receive a test signal, the first port is used to receive a working voltage, and the second port is electrically connected to the first port. The test voltage application module provides a test voltage to the second terminal when the detection transistor receives the test signal and turns on, so that the detection transistor operates in the deep transistor region; A current acquisition module is used to acquire the current flowing through the second terminal during the period when the detection transistor is operating in the deep transistor region; The resistance acquisition module acquires the resistance of the through-silicon via structure based on the intrinsic conductivity factor, the operating voltage, the test voltage, and the current flowing through the second terminal.

13. The testing system as described in claim 12, characterized in that, Also includes: A calibration transistor is located in the second chip. The calibration transistor includes a calibration gate, a third port, and a fourth port. The calibration gate is used to receive a control signal, the third port is used to receive a calibration working voltage, and the fourth port is electrically connected to the second terminal. When the detection transistor receives the test signal and is turned on, the calibration transistor receives the control signal and is turned off.

14. The testing system as described in claim 13, characterized in that, Also includes: The calibration test voltage application module provides a calibration test voltage to the first terminal when the detection transistor is in the off state when it receives the test signal and the calibration transistor is in the on state when it receives the control signal, so that the calibration transistor operates in the deep transistor region. A calibration current acquisition module is used to acquire the current flowing through the first terminal during the operation of the calibration transistor in the deep transistor region; The calibration resistance acquisition module acquires the calibration resistance of the silicon through-hole structure based on the calibration intrinsic conductivity factor, the calibration operating voltage, the calibration test voltage, and the current flowing through the first terminal.

15. The testing system as described in claim 13, characterized in that, Both the detection transistor and the calibration transistor are PMOS transistors.

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