An optimization method for the solder mask of a circuit board

Abstract

The present invention discloses an optimization method for the solder mask of a circuit board, comprising the following steps: a: inputting the information of the copper layer and the solder mask layer into Genesis, including the positions of the circuits, pads, and openings; b: preliminarily optimizing the pads and openings; c: identifying the cover lines and solder bridges, where the width of the cover line is A and the width of the solder bridge is B; d: inputting the optimal values and minimum values of A and B respectively into Genesis; e: comparing the widths of each cover line and solder bridge with the corresponding optimal values and minimum values and optimizing according to the results; f: copying the pad information; g: restoring the information in f to the state when input in a; h: copying the information restored in g and expanding the outer edge of the pad by C; i: taking the difference set between the pad positions after processing h and after processing g to obtain an annular region; j: copying the circuit information and taking the intersection with the annular region to obtain a tombstone pre-removal region; k: expanding the outer edge of the tombstone pre-removal region in j by D to obtain a tombstone removal region; m: deleting the solder mask covered by the tombstone removal region.

Description

Technical Field

[0001] The present invention relates to an optimization method for solder mask on a circuit board. Background Art

[0002] At present, the rapid development of electronic communication devices and automotive products has led to continuous upgrading of circuit boards, which serve as carriers for components. This has also imposed stricter requirements for the optimization of solder mask. For example, for the width of cover lines and solder bridges, the dimensions generally need to be adjusted and optimized according to the actual process conditions to improve production efficiency and benefits. Currently, this operation of dimension adjustment needs to be processed manually one by one. For the connection between the opening window and the circuit, in order to prevent the tombstone effect from occurring during subsequent component soldering, corresponding optimization treatment is also required. However, currently, it can only be processed manually one by one.

[0003] Generally, there are a large number of cover lines, solder bridges, and opening windows on a circuit board. The above optimization process can only be optimized through manual processing, which greatly limits the improvement of production efficiency. At the same time, due to the large amount of optimization work, the probability of manual processing errors is relatively high. Once an error occurs, it will further reduce the optimization efficiency.

[0004] Therefore, how to overcome the above-mentioned defects has become an important issue that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] The present invention overcomes the above-mentioned technical deficiencies and provides an optimization method for solder mask on a circuit board.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] An optimization method for solder mask on a circuit board includes the following steps:

[0008] Step a: Input the distribution information of the corresponding copper layer and solder mask layer 1 that need to be optimized for the circuit board into the Genesis software. The copper layer information includes the positions of the circuit 2 and the pad 3, and the solder mask layer 1 information includes the positions of the opening windows.

[0009] Step b: Initially optimize the dimensions of the pad 3 and the opening windows through the Genesis software.

[0010] Step c: Identify the cover line 4 and the solder bridge 5 by analyzing the positional relationship between the pad 3 and the circuit 2 through Genesis. The cover line 4 is the solder mask layer 1 between the pad 3 and the circuit 2, and the solder bridge 5 is the solder mask layer 1 between two pads. The width of the cover line 4 is represented by A, and the width of the solder bridge 5 is represented by B.

[0011] Step d: Input the optimal value and minimum value of the width A of the cover line 4 into Genesis, and input the optimal value and minimum value of the width B of the oil bridge 5 into Genesis;

[0012] Step e: Compare the widths of the respective cover lines 4 and oil bridges 5 identified in step d with their corresponding optimal values and minimum values. If the width of the cover line 4 / oil bridge 5 is greater than its corresponding optimal value, then correct the width of the cover line 4 / oil bridge 5 to the optimal value. If the width of the cover line 4 / oil bridge 5 is less than the corresponding optimal value but greater than the corresponding minimum value, then do not correct the width of the cover line 4 / oil bridge 5. If the width of the cover line 4 / oil bridge 5 is less than the corresponding minimum value, then issue an alarm to prompt manual intervention;

[0013] Step f: Copy a copy of the position information of the pad 3 in Genesis;

[0014] Step g: Restore the pad 3 information copied in step f to the state when inputting step a;

[0015] Step h: Copy a copy of the position information of the pad 3 restored in step g, and expand the edges of each pad 3 in this copy outward by C, where the unit of C is mil;

[0016] Step i: Perform a difference set operation on the position of the pad 3 processed in step h and the position of the pad 3 processed in step g to obtain a plurality of annular regions 6;

[0017] Step j: Copy a copy of the position information of the circuit 2 and perform an intersection operation with the annular region 6 obtained in step i to obtain a tombstone pre-removal region 7;

[0018] Step k: Expand the edge of the tombstone pre-removal region 7 obtained in step j outward by D, where the unit of D is mil, to obtain a tombstone removal region 8;

[0019] Step m: Delete the solder mask in the solder mask layer 1 covered by the tombstone removal region 8.

[0020] Preferably, the step b includes the following content:

[0021] One: Define the window opening type in Genesis. Among them, the window opening whose edge is completely located inside the pad 3 is defined as a full copper window opening 11, the window opening whose edge is not completely located inside the pad 3 is defined as a semi-copper window opening 12, and the window opening whose edge is not located inside the pad 3 at all is defined as a non-copper window opening 13;

[0022] Two: Analyze the positional inclusion relationship between each pad 3 and the corresponding window opening in the solder mask layer 1 through Genesis, and classify the window openings according to the window opening definition rules;

[0023] III: According to the actual process conditions, use Genesis to compensate and optimize the sizes of different types of openings and the corresponding pads 3 respectively.

[0024] Preferably, the optimal value of the width A of the cover line 4 is 3 mil, and the minimum value is 1.8 mil.

[0025] Preferably, the optimal value of the width B of the oil bridge 5 is 3.5 mil, and the minimum value is 3 mil.

[0026] Preferably, in step i, C = 4 mil.

[0027] Preferably, in step m, D = 4 mil.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] In the optimization method of this case, first input the distribution information of the copper layer and the solder mask layer of the circuit board into the Genesis software. Through Genesis, analyze the positional relationship between the pads and the traces to identify the cover line and the oil bridge. Then, the width dimensions of the cover line and the oil bridge can be automatically adjusted by Genesis according to the preset optimal values and minimum values respectively. In this way, the adjustment efficiency can be greatly improved, and at the same time, errors caused by the large amount of manual adjustment work and repetition can be avoided. In addition, by expanding the edge of the original pad outward and then taking the difference set with the original position of the pad, an annular region can be obtained. Then, taking the intersection of the annular region and the position of the trace can obtain the tombstone pre-removal region. Then, expanding the tombstone pre-removal region outward can obtain the tombstone removal region. Finally, delete the solder mask covered by the tombstone removal region from the solder mask layer, and thus the anti-tombstone effect treatment is completed. In this way, through the program to automatically perform the anti-tombstone effect treatment through a formulaic step, the treatment efficiency can be greatly improved, and the probability of making mistakes can also be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of the circuit board in this case.

[0031] Figure 2 is a schematic diagram of the trace distribution on the circuit board in this case.

[0032] Figure 3 is a schematic diagram of the pad distribution on the circuit board in this case.

[0033] Figure 4 is a schematic diagram of the solder mask layer distribution on the circuit board in this case.

[0034] Figure 5 is a schematic diagram of the annular region and the tombstone pre-removal region in this case.

[0035] Figure 6 is a schematic diagram of the tombstone removal region in this case.

[0036] Figure 7 It is a schematic diagram of the solder mask layer distribution after deleting the solder mask layer covered by the area to be removed by the tombstone.

[0037] Figure 8 It is a schematic diagram of the circuit board in this case after completing the treatment of preventing tombstone effect. Specific embodiments

[0038] The features of the present invention and other related features will be further described in detail below through embodiments for the understanding of those skilled in the same industry:

[0039] As Figures 1 to 8 shown, an optimization method for the solder mask of a circuit board includes the following steps:

[0040] Step a: Input the distribution information of the corresponding copper layer and the solder mask layer 1 that needs to be optimized for the circuit board into the Genesis software. The copper layer information includes the positions of the lines 2 and the pads 3, and the solder mask layer 1 information includes the positions of the openings;

[0041] Step b: Preliminarily optimize the sizes of the pads 3 and the openings through the Genesis software;

[0042] Step c: Identify the cover lines 4 and the solder bridges 5 by analyzing the positional relationship between the pads 3 and the lines 2 through the Genesis. Among them, the cover line 4 is the solder mask layer 1 between the pad 3 and the line 2, and the solder bridge 5 is the solder mask layer 1 between two pads. The width of the cover line 4 is represented by A, and the width of the solder bridge 5 is represented by B;

[0043] Step d: Input the optimal value and the minimum value of the width A of the cover line 4 into the Genesis, and input the optimal value and the minimum value of the width B of the solder bridge 5 into the Genesis. The optimal value refers to the width value with the best benefit under comprehensive consideration, and the minimum value refers to the limit value that can be achieved in terms of process technology;

[0044] Step e: Compare the widths of the respective cover lines 4 and solder bridges 5 identified in step d with their corresponding optimal values and minimum values. If the width of the cover line 4 / solder bridge 5 is greater than its corresponding optimal value, then correct the width of the cover line 4 / solder bridge 5 to the optimal value. If the width of the cover line 4 / solder bridge 5 is less than the corresponding optimal value and greater than the corresponding minimum value, then do not correct the width of the cover line 4 / solder bridge 5. If the width of the cover line 4 / solder bridge 5 is less than the corresponding minimum value, then issue an alarm prompt for manual intervention;

[0045] Step f: Copy a copy of the position information of the pad 3 in the Genesis;

[0046] Step g: Restore the pad 3 information copied in step f to the state when it was input in step a;

[0047] Step h: Copy the position information of the pad 3 after restoration in step g, and expand the edges of each pad 3 in this copy outward by C, where the unit of C is mil;

[0048] Step i: Perform a difference set operation on the position of the pad 3 processed in step h and the position of the pad 3 processed in step g to obtain multiple annular regions 6;

[0049] Step j: Copy the position information of the circuit 2 and perform an intersection operation with the annular region 6 obtained in step i to obtain the tombstone pre-removal region 7;

[0050] Step k: Expand the edges of the tombstone pre-removal region 7 obtained in step j outward by D, where the unit of D is mil, to obtain the tombstone removal region 8;

[0051] Step m: Delete the solder mask in the solder mask layer 1 covered by the tombstone removal region 8.

[0052] As described above, in the optimization method of this case, the distribution information of the copper layer and the solder mask layer 1 of the circuit board is first input into the Genesis software. By analyzing the positional relationship between the pad 3 and the circuit 2 in Genesis, the covering line 4 and the oil bridge 5 are identified. Then, the width dimensions of the covering line 4 and the oil bridge 5 can be automatically adjusted according to the preset optimal value and minimum value respectively through Genesis. In this way, the adjustment efficiency can be greatly improved, and at the same time, errors caused by large and repeated manual adjustments can be avoided; in addition, by expanding the edges of the original pad 3 outward and then performing a difference set operation with the original position of the pad 3, the annular region 6 can be obtained. Then, by performing an intersection operation between the annular region 6 and the position of the circuit 2, the tombstone pre-removal region 7 can be obtained. Then, by expanding the tombstone pre-removal region 7 outward, the tombstone removal region 8 can be obtained. Finally, the solder mask covered by the tombstone removal region 8 is deleted from the solder mask layer 1, thus completing the anti-tombstone effect treatment. In this way, through the program to automatically perform the anti-tombstone effect treatment through formulaic steps, the processing efficiency can be greatly improved, and the probability of making mistakes can also be reduced.

[0053] As Figures 1 to 8 shown, preferably, step b includes the following contents:

[0054] One: Define the window opening types in Genesis. Among them, the window opening whose edge is completely located inside the pad 3 is defined as the full copper window opening 11, the window opening whose edge is not completely located inside the pad 3 is defined as the half copper window opening 12, and the window opening whose edge is not located inside the pad 3 at all is defined as the non-copper window opening 13;

[0055] II: Analyze the positional inclusion relationship between each pad 3 and the opening of the corresponding solder mask layer 1 through Genesis, and classify the openings according to the opening definition rules;

[0056] III: According to the actual process conditions, use Genesis to respectively compensate and optimize the sizes of different types of openings and the corresponding pads 3.

[0057] As described above, the functions built into the Genesis software cannot automatically classify and identify the types of openings. By pre-defining the types of openings, Genesis can automatically identify the types of openings to which different openings belong. In this way, the process of manually classifying and defining each opening one by one can be omitted, and full-automatic classification recognition and size compensation optimization can be achieved.

[0058] As Figures 1 to 8 shown, preferably, the optimal value of the width A of the cover line 4 is 3 mil, and the minimum value is 1.8 mil.

[0059] As Figures 1 to 8 shown, preferably, the optimal value of the width B of the solder bridge 5 is 3.5 mil, and the minimum value is 3 mil.

[0060] As Figures 1 to 8 shown, preferably, C = 4 mil in step i.

[0061] As Figures 1 to 8 shown, preferably, D = 4 mil in step m.

[0062] As described above, the present case protects an optimization method for the solder mask of a circuit board. All technical solutions identical or similar to the present case should be considered as falling within the protection scope of the present case.

Claims

1. An optimization method for the green solder mask of a circuit board, characterized in that It includes the following steps: Step a: Input the distribution information of the corresponding copper layer and solder mask layer (1) that needs to be optimized for the circuit board into the Genesis software. The copper layer information includes the positions of the traces (2) and pads (3), and the solder mask layer (1) information includes the positions of the openings; Step b: Initially optimize the sizes of the pads (3) and openings through the Genesis software; Step c: Identify the cover lines (4) and oil bridges (5) by analyzing the positional relationship between the pads (3) and the traces (2) through Genesis. Among them, the cover line (4) is the solder mask layer (1) between the pad (3) and the trace (2), and the oil bridge (5) is the solder mask layer (1) between two pads. The width of the cover line (4) is represented by A, and the width of the oil bridge (5) is represented by B; Step d: Input the optimal value and minimum value of the width A of the cover line (4) into Genesis, and input the optimal value and minimum value of the width B of the oil bridge (5) into Genesis; Step e: Compare the widths of each identified cover line (4) and oil bridge (5) with their respective optimal values and minimum values. If the width of the cover line (4) / oil bridge (5) is greater than its corresponding optimal value, then correct the width of the cover line (4) / oil bridge (5) to the optimal value. If the width of the cover line (4) / oil bridge (5) is less than the corresponding optimal value and greater than the corresponding minimum value, then do not correct the width of the cover line (4) / oil bridge (5). If the width of the cover line (4) / oil bridge (5) is less than the corresponding minimum value, then issue an alarm to prompt manual intervention; Step f: Copy a copy of the position information of the pads (3) in Genesis; Step g: Restore the pad (3) information copied in step f to the state when input in step a; Step h: Copy a copy of the pad (3) position information restored in step g, and expand each pad (3) edge outward by C, where the unit of C is mil; Step i: Perform a difference set operation on the pad (3) positions processed in step h and the pad (3) positions processed in step g to obtain multiple annular regions (6); Step j: Copy a copy of the position information of the traces (2) and perform an intersection operation with the annular regions (6) obtained in step i to obtain the tombstone pre-removal region (7); Step k: Expand the edge of the tombstone pre-removal region (7) obtained in step j outward by D, where the unit of D is mil, to obtain the tombstone removal region (8); Step m: Delete the solder mask covered by the tombstone removal region (8) in the solder mask layer (1).

2. The optimization method of a circuit board green oil according to claim 1, characterized in that Step b includes the following content: One: Define the opening types in Genesis. Among them, the opening whose edge is completely located within the pad (3) is defined as a full-copper opening (11), the opening whose edge is not completely located within the pad (3) is defined as a semi-copper opening (12), and the opening whose edge is not located within the pad (3) at all is defined as a non-copper opening (13); Two: Classify the openings according to the opening definition rules by analyzing the positional inclusion relationship between each pad (3) and the openings in the corresponding solder mask layer (1) through Genesis; III: According to the actual process conditions, use Genesis to perform compensation optimization on the sizes of different types of openings and the corresponding pads (3) respectively.

3. The optimization method of a circuit board green oil according to claim 1, characterized in that The optimal value of the width A of the cover line (4) is 3 mil, and the minimum value is 1.8 mil.

4. The optimization method of a circuit board green oil according to claim 1, characterized in that The optimal value of the width B of the oil bridge (5) is 3.5 mil, and the minimum value is 3 mil.

5. The optimization method of a circuit board green oil according to claim 1, characterized in that In step h, C = 4 mil.

6. The optimization method of a circuit board green oil according to claim 1, wherein In step k, D = 4 mil.

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