Pixel circuit and display panel including the same

Abstract

A pixel circuit and a display panel including the pixel circuit are disclosed according to an embodiment. The pixel circuit according to the embodiment includes: a first pixel circuit including a first EM transistor to which a pulse of a first EM signal is applied, and a first driving transistor for driving a first light-emitting element; a second pixel circuit including a second EM transistor to which a pulse of a second EM signal is applied, and a second driving transistor for driving a second light-emitting element. A node between the first EM transistor and the first driving transistor is connected to a node between the second EM transistor and the second driving transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2021 - 0100602, filed on July 30, 2021, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a pixel circuit and a display panel including the pixel circuit. Background art

[0004] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDPs), etc.

[0005] According to the material of the light - emitting layer, electroluminescent display devices are divided into inorganic light - emitting display devices and organic light - emitting display devices. An active - matrix organic light - emitting display device uses self - emitting elements (e.g., organic light - emitting diodes (hereinafter referred to as "OLEDs")) that emit light by themselves to reproduce an input image. The advantages of an organic light - emitting display device are fast response speed, high luminous efficiency, high brightness, and wide viewing angle.

[0006] Some display devices, such as liquid crystal display devices or organic light - emitting display devices, include a display panel having a plurality of sub - pixels, a driver that outputs a driving signal for driving the display panel, a power supply that generates power supplied to the display panel or the driver, etc. The driver includes a gate driver that provides a scan signal or a gate signal to the display panel, and a data driver that provides a data signal to the display panel.

[0007] In such a display device, when driving signals such as a scan signal, an EM signal, and a data signal are provided to a plurality of sub - pixels formed in the display panel, the selected sub - pixels transmit light or emit light directly to display an image.

[0008] An EM transistor to which an EM signal is applied can be duty - driven, and compared with a scan transistor and a sense transistor, the EM transistor is continuously driven to maintain the brightness based on one frame. Therefore, when driven at 100% duty ratio, the reliability of the EM transistor is low. Summary of the invention

[0009] The present disclosure aims to solve all the above - mentioned needs and problems.

[0010] The present disclosure provides a pixel circuit and a display panel including the pixel circuit that can ensure the reliability of an EM transistor.

[0011] It should be noted that the purpose of the present disclosure is not limited to the above purposes, and other purposes of the present disclosure will be obvious to those skilled in the art from the following description.

[0012] The pixel circuit according to the present disclosure includes: a first pixel circuit including a first EM transistor to which a pulse of a first EM signal is applied, and a first driving transistor for driving a first light-emitting element; and a second pixel circuit including a second EM transistor to which a pulse of a second EM signal is applied, and a second driving transistor for driving a second light-emitting element, and a node between the first EM transistor and the first driving transistor is connected to a node between the second EM transistor and the second driving transistor.

[0013] The display panel according to the present disclosure includes a plurality of pixel circuits, each pixel circuit including: a light-emitting element that emits light by a current flowing through a current path formed between a high-potential voltage line and a low-potential voltage line; and an EM transistor that switches the current path in response to an EM signal, and the current path is connected between at least two pixel circuits.

[0014] According to the present disclosure, source nodes of EM elements between adjacent pixels sharing a data line are connected to drive a plurality of light-emitting elements through one EM device, thereby reducing the duty ratio of driving the EM element, reducing stress, and ensuring reliability.

[0015] According to the present disclosure, the driving ratio of the EM transistor can be reduced without increasing EM lines and EM signals.

[0016] The effects of the present disclosure are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] By referring to the accompanying drawings and describing in detail the exemplary embodiments of the present disclosure, the above and other purposes, features, and advantages of the present disclosure will become clearer to those of ordinary skill in the art. In the drawings:

[0018] Figure 1 is a diagram showing a pixel circuit according to a first embodiment of the present disclosure;

[0019] Figure 2A and Figure 2B is a diagram showing Figure 1 the operating principle of the pixel circuit shown;

[0020] Figure 3 and Figure 4 are circuit diagrams showing pixel circuits according to other embodiments of the present disclosure;

[0021] Figure 5It is a diagram showing the connection state of pixel circuits in a display panel;

[0022] Figure 6 It is a diagram showing Figure 5 the driving timing of the pixel circuits shown;

[0023] Figure 7A and Figure 7B It is a diagram showing Figure 5 the operating principle of the pixel circuits shown;

[0024] Figure 8 It is a diagram showing the pixel circuit according to the fourth embodiment of the present disclosure;

[0025] Figures 9A to 9C It is a diagram showing Figure 8 the operating principle of the pixel circuits shown;

[0026] Figure 10 It is a diagram showing the pixel circuit according to the fifth embodiment of the present disclosure;

[0027] Figure 11 and Figure 12 It is a circuit diagram showing the pixel circuits according to other embodiments of the present disclosure;

[0028] Figure 13A and Figure 13B It is a diagram showing Figure 10 the operating principle of the pixel circuits shown;

[0029] Figure 14 It is a diagram showing the pixel circuit according to the eighth embodiment of the present disclosure;

[0030] Figure 15 and Figure 16 It is a diagram showing various pixel circuits applicable to the pixel circuits of the present disclosure;

[0031] Figure 17 It is a block diagram showing a display device according to an embodiment of the present disclosure. Detailed Description of the Invention

[0032] The advantages and features of the present disclosure and its implementation method will be more clearly understood through the embodiments described below with reference to the drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited within the scope of the appended claims.

[0033] The shapes, dimensions, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0034] Terms such as "comprising", "including", "having", and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise expressly stated.

[0035] Even if not expressly stated, components are interpreted as including a normal error range.

[0036] When terms such as "above", "over", "below", and "next to" are used to describe the positional relationship between two components, one or more components may be located between the two components, unless these terms are used together with the terms "immediately" or "directly".

[0037] Terms such as "first", "second", etc. may be used to distinguish components, but the functions or structures of the components are not limited by the serial numbers or component names in front of the components.

[0038] Throughout the present disclosure, the same reference numerals may refer to substantially the same elements.

[0039] The following embodiments may be partially or completely combined or combined with each other, and may be linked and operated in various ways technically. These embodiments may be implemented independently or in relation to each other.

[0040] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the drawings.

[0041] Figure 1 is a diagram showing a pixel circuit according to a first embodiment of the present disclosure. Figure 2A and Figure 2B is a diagram showing Figure 1 the operating principle of the pixel circuit shown.

[0042] Referring to Figure 1 , the pixel circuit according to the embodiment includes a first pixel circuit PXL1 and a second pixel circuit PXL2 arranged in the column direction. Each of the first pixel circuit PXL1 and the second pixel circuit PXL2 includes a light-emitting element EL, a driving transistor DT for driving the light-emitting element EL, and an EM transistor Tem for switching the current path connected to the driving transistor DT. The driving transistor DT and the EM transistor Tem may be implemented as n-channel oxide transistors.

[0043] The first pixel circuit PXL1 includes a first light-emitting element EL1, a first driving transistor DT1, and a first EM transistor Tem1. The first EM transistor Tem1 is connected between the first power supply line and the first a-node N1a, the first driving transistor DT1 is connected between the first a-node N1a and the second a-node N2a, and the first light-emitting element EL1 is connected between the second a-node N2a and the low-potential voltage line.

[0044] When the applied EM signal is a gate conduction voltage, the first EM transistor Tem1 conducts and supplies the pixel driving voltage EVDD to the first a-node N1a. The first EM transistor Tem1 includes a gate connected to the gate line to which the EM signal is applied, a first electrode connected to the first power supply line to which the pixel driving voltage is supplied, and a second electrode connected to the first a-node N1a.

[0045] The first driving transistor DT1 drives the first light-emitting element EL1 by supplying current to the first light-emitting element EL1 according to the gate-source voltage Vgs. The first driving transistor DT1 includes a gate (or gate electrode) to which the data voltage is applied, a first electrode (or drain electrode) connected to the first a-node N1a, and a second electrode (or source electrode) connected to the second a-node N2a.

[0046] The second pixel circuit PXL2 includes a second light-emitting element EL2, a second driving transistor DT2, and a second EM transistor Tem2. The second EM transistor Tem2 is connected between the first power supply line and the first b-node N1b, the second driving transistor DT2 is connected between the first b-node N1b and the second b-node N2b, and the second light-emitting element EL2 is connected between the second b-node N2b and the second power supply line.

[0047] When the applied EM signal is a gate conduction voltage, the second EM transistor Tem2 conducts and supplies the pixel driving voltage EVDD to the first b-node N1b. The second EM transistor Tem2 includes a gate connected to the gate line to which the EM signal is applied, a first electrode connected to the first power supply line to which the pixel driving voltage is supplied, and a second electrode connected to the first b-node N1b.

[0048] The second driving transistor DT2 drives the second light-emitting element EL2 by supplying current to the second light-emitting element EL2 according to the gate-source voltage Vgs. The second driving transistor DT2 includes a gate to which the data voltage is applied, a first electrode connected to the first b-node N1b, and a second electrode connected to the second b-node N2b.

[0049] In this case, the first a-node N1a in the first pixel circuit PXL1 and the first b-node N1b in the second pixel circuit PXL2 are connected to each other. The first a-node N1a and the first b-node N1b are a first node N1 connected by a connection line. When the gate-on voltage of the EM signal is applied to the first EM transistor Tem1, the first EM transistor Tem1 conducts and supplies the pixel driving voltage to the first a-node N1a and the first b-node N1b. The first driving transistor DT1 connected to the first a-node N1a and the second driving transistor DT2 connected to the first b-node N1b supply current to the first light-emitting element EL1 and the second light-emitting element EL2 according to the gate-source voltage, thereby driving the first light-emitting element EL1 and the second light-emitting element EL2.

[0050] In addition, when the gate-on voltage of the EM signal is applied to the second EM transistor Tem2, the second EM transistor Tem2 conducts and supplies the pixel driving voltage to the first b-node N1b and the first a-node N1a. The second driving transistor DT2 connected to the first b-node N1b and the first driving transistor DT1 connected to the first a-node N1a supply current to the second light-emitting element EL2 and the first light-emitting element EL1 according to the gate-source voltage, thereby driving the second light-emitting element EL2 and the first light-emitting element EL1.

[0051] Referring to Figure 2A and Figure 2B , in the case where the first pixel circuit PXL1 and the second pixel circuit PXL2 are connected, when the first EM transistor Tem1 conducts, the pixel driving voltage is applied, so both the first light-emitting element EL1 and the second light-emitting element EL2 are driven, and when the second EM transistor Tem2 conducts, the pixel driving voltage is applied, so both the first light-emitting element EL1 and the second light-emitting element EL2 are driven.

[0052] In this case, the duty ratios of light emission of the first light-emitting element EL1 and the second light-emitting element EL2 are different from the duty ratio of the EM signal applied to the first EM transistor Tem1 and the second EM transistor Tem2. In an embodiment, the duty ratio of light emission is greater than the duty ratio of the EM signal. Here, the duty ratio of light emission refers to the ratio of the light-emitting interval in a cycle including the light-emitting interval and the non-light-emitting interval. The duty ratio of the EM signal refers to the ratio of the on interval in a cycle including the on interval and the off interval.

[0053] For example, as Figure 2A shown, when the duty ratio of the EM signal is 25%, the duty ratio of light emission can be 50%. As Figure 2B shown, when the duty ratio of the EM signal is 50%, the duty ratio of light emission can be 100%.

[0054] The duty ratio of the EM signal is the value of (emission duty ratio / number of pixel circuits). According to an embodiment, when two pixel circuits are connected, the duty ratio of the EM signal is half of the emission duty ratio. Therefore, the number of times the switching element is driven is reduced, thereby reducing stress.

[0055] Figure 3 and Figure 4 is a circuit diagram showing a pixel circuit according to other embodiments of the present disclosure.

[0056] Referring to Figure 3 According to the second embodiment, the pixel circuit includes a first pixel circuit PLX1 and a second pixel circuit PLX2 arranged in a column direction and sharing a data line. Each of the first pixel circuit PLX1 and the second pixel circuit PLX1 includes a light-emitting element EL, a driving transistor DT for driving the light-emitting element EL, an EM transistor Tem for switching a current path connected to the driving transistor DT, a sensing transistor Tsense, a scanning transistor Tscan, and a capacitor Cst for storing the gate-source voltage Vgs of the driving transistor DT. The driving transistor DT, the EM transistor Tem, the sensing transistor Tsense, and the scanning transistor Tscan can be implemented as n-channel oxide transistors.

[0057] The light-emitting element EL emits light by a current applied through the channel of the driving element DT based on the gate-source voltage Vgs of the driving element DT that varies based on the data voltage Vdata. The light-emitting element EL can be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EM1), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light-emitting element EL is connected to the driving element DT through a second node n2, and the cathode of the light-emitting element EL is connected to a second power line 42 to which a low-potential power supply voltage EVSS is applied.

[0058] The organic light-emitting diode used as the light-emitting element may have a tandem structure in which a plurality of light-emitting layers are stacked. The organic light-emitting diode having a tandem structure can improve the brightness and lifetime of the pixel.

[0059] The scanning transistor Tscan is turned on with a gate conduction voltage VGH according to a scan signal SCAN, connects the data line to a third node N3, and supplies a data voltage Vdata to the driving transistor DTN3 connected to the third node. The third node N3 is connected to the gate of the driving transistor DT. Therefore, the gate voltage of the driving transistor DT is equal to the voltage of the third node N3. The scanning transistor Tscan includes a gate connected to a first gate line to which the scan signal SCAN is applied, a first electrode connected to the data line, and a second electrode connected to the third node N3.

[0060] The sensing transistor Tsense is turned on by the gate conduction voltage VGH according to the sensing signal SENSE, and supplies the reference voltage Vref to the second node N2. The sensing transistor Tsense includes a gate connected to the first gate line to which the scan signal SCAN is applied, a first electrode connected to the reference voltage line to which the reference voltage Vref is applied, and a second electrode connected to the second node N2.

[0061] The EM transistor Tem is turned on by the gate conduction voltage VEH of the EM signal EM, and supplies the pixel driving voltage EVDD to the first node N1. The EM transistor Tem includes a gate connected to the EM line to which the EM signal EM is applied, a first electrode connected to the first power supply line to which the pixel driving voltage EVDD is supplied, and a second electrode connected to the first node N1.

[0062] The source nodes of the third switching elements in the first pixel circuit PLX1 and the second pixel circuit PLX2 are connected to each other. That is, the first nodes N1 of the first pixel circuit PLX1 and the second pixel circuit PLX2 are connected to each other.

[0063] The driving transistor DT drives the light-emitting element EL by supplying a current to the light-emitting element EL according to the gate-source voltage Vgs. The driving transistor DT includes a gate connected to the third node N3, a first electrode (or drain) connected to the first node N1, and a second electrode (or source) connected to the anode of the light-emitting element EL through the second node N2.

[0064] The storage capacitor Cst is connected between the third node N3 and the second node N2. The storage capacitor Cst charges the gate-source voltage Vgs of the driving transistor DT.

[0065] In the sensing mode, the current flowing through the channel of the driving transistor DT or the voltage between the driving transistor DT and the light-emitting element EL is sensed through the reference voltage line. The current flowing through the reference voltage line is converted into a voltage by an integrator and converted into digital data by an analog-to-digital converter ADC. This digital data is sensing data including the threshold voltage or mobility information of the driving transistor DT. The sensing data is transmitted to the data operation unit. The data operation unit can receive the sensing data from the ADC and compensate for the driving deviation and deterioration of the pixel by adding or multiplying a compensation value selected based on the sensing data to the pixel data.

[0066] Refer to Figure 4, the pixel circuit according to the third embodiment includes a first pixel circuit PLX1 and a second pixel circuit PLX2 that are arranged in a column direction and share a data line. In addition to the configuration of the second embodiment, each of the first pixel circuit PLX1 and the second pixel circuit PLX2 further includes an initialization transistor Tinit connected between an initialization voltage line and a third node N3. In this pixel circuit, the driving transistor DT, the EM transistor Tem, the sensing transistor Tsense, the scanning transistor Tscan, and the initialization transistor Tinit can be implemented as n-channel oxide transistors.

[0067] The initialization transistor Tinit applies an initialization voltage V in response to an initialization signal INIT. INIT . In this case, the initialization voltage V INIT is applied to the third node N3 through the initialization voltage line.

[0068] Figure 5 is a diagram showing the connection state of the pixel circuit in the display panel. Figure 6 is a diagram showing Figure 5 the driving timing of the pixel circuit shown. Figure 7A and Figure 7B is a diagram showing Figure 5 the operating principle of the pixel circuit shown.

[0069] Referring to Figure 5 and Figure 6 , the display panel includes a plurality of pixel circuits PXL that share a data line. The plurality of pixel circuits PXL are connected in parallel in pairs. That is, the source nodes of the EM elements between two adjacent pixel circuits are connected, so that the two pixel circuits are connected in parallel.

[0070] In this case, the EM signal can be driven by being divided into an internal compensation part and a duty ratio driving part. The EM signal is alternately applied every frame, but the driving timing is the same.

[0071] Referring to Figure 7A, the gate-on voltage of the EM signal is applied to the odd-numbered EM lines in the first frame period, and the EM transistors Tem in the first pixel circuits PXL_11, …, PXL_N1 connected to the first EM line and the third pixel circuits PXL_13, …, PXL_N3 connected to the third EM line are turned on. That is, when the EM transistors Tem in the first pixel circuits PXL_11, …, PXL_N1 are turned on, a pixel driving voltage is applied to drive the light-emitting elements of the first pixel circuits PXL_11, …, PXL_N1 and the second pixel circuits PXL_12, …, PXL_N2. When the EM transistors Tem in the third pixel circuits PXL_13, …, PXL_N3 are turned on, a pixel driving voltage is applied to drive the light-emitting elements of the third pixel circuits PXL_13, …, PXL_N3 and the fourth pixel circuits PXL_14, …, PXL_N4.

[0072] Referring to Figure 7B , the gate-on voltage of the EM signal is applied to the even-numbered EM lines in the second frame period, and the EM transistors Tem in the second pixel circuits PXL_12, …, PXL_N2 connected to the second EM line and the fourth pixel circuits PXL_14, …, PXL_N4 connected to the fourth EM line are turned on. That is, when the EM transistors Tem in the second pixel circuits PXL_12, …, PXL_N2 are turned on, a pixel driving voltage is applied to drive the light-emitting elements of the second pixel circuits PXL_12, …, PXL_N2 and the first pixel circuits PXL_11, …, PXL_N1. When the EM transistors Tem in the fourth pixel circuits PXL_14, …, PXL_N4 are turned on, a pixel driving voltage is applied to drive the light-emitting elements of the fourth pixel circuits PXL_14, …, PXL_N4 and the third pixel circuits PXL_13, …, PXL_N3.

[0073] In a state where the light-emitting element is driven with a 100% duty ratio, the duty ratio of driving the EM transistor is 50%. In this case, the EM transistor shares the EM signal in units of two horizontal periods (2H).

[0074] In this way, in the odd frame period, the EM elements in the odd pixel circuits are turned on to drive the light-emitting elements in the parallel pixel circuits, and in the even frame period, the EM elements in the even pixel circuits are turned on to drive the light-emitting elements in the parallel pixel circuits. Therefore, all the light-emitting elements can be driven by alternately driving the two EM elements.

[0075] Figure 8 is a diagram showing a pixel circuit according to a fourth embodiment of the present disclosure. Figures 9A to 9C is a diagram showing Figure 8 the operating principle of the pixel circuit shown.

[0076] Refer to Figure 8 Figure 8 , the pixel circuit according to the fourth embodiment includes a first pixel circuit PXL1, a second pixel circuit PXL2, and a third pixel circuit PXL3 arranged in a column direction. Each of the first pixel circuit PXL1, the second pixel circuit PXL2, and the third pixel circuit PXL3 includes a light-emitting element EL, a driving transistor DT for driving the light-emitting element EL, and an EM transistor Tem for switching a current path connected to the driving transistor DT.

[0077] In this case, a first a-node N1a in the first pixel circuit PXL1, a first b-node N1b in the second pixel circuit PXL2, and a first c-node N1c in the third pixel circuit PXL3 are connected to each other. The first a-node N1a, the first b-node N1b, and the first c-node N1c are a first node N1 connected by a connection line. When the gate conduction voltage of the EM signal is applied to the first EM transistor Tem1 in the first pixel circuit PXL1, the second EM transistor Tem2 in the second pixel circuit PXL2, or the third EM transistor Tem3 in the third pixel circuit PXL3, the first EM transistor Tem1, the second EM transistor Tem2, or the third EM transistor Tem3 conducts and supplies a pixel driving voltage to the first node N1 of the first pixel circuit PXL1, the second pixel circuit PXL2, and the third pixel circuit PXL3. The driving transistors DT connected to the first node N1 in the first pixel circuit PXL1, the driving transistors DT connected to the first node N1 in the second pixel circuit PXL2, and the driving transistors DT connected to the first node N1 in the third pixel circuit supply current to the first light-emitting element EL1, the second light-emitting element EL2, and the third light-emitting element EL3 according to the gate-source voltage, thereby driving the first light-emitting element EL1, the second light-emitting element EL2, and the third light-emitting element EL3.

[0078] In this case, the light emission duty ratios of the first light-emitting element EL1, the second light-emitting element EL2, and the third light-emitting element EL3 are different from the duty ratio of the EM signal applied to the first EM transistor, the second EM transistor, and the third EM transistor. In the embodiment, the light emission duty ratio is greater than the duty ratio of the EM signal.

[0079] Although the case where two pixel circuits or three pixel circuits are connected is exemplarily described herein, the present disclosure is not limited to this case, and more pixel circuits can be connected. That is, in the embodiment, at least two pixel circuits can be connected. As the number of connected pixel circuits increases, the duty ratio of the EM signal can be reduced. As the duty ratio of the EM signal is reduced, the stress on the switching element is also reduced.

[0080] Refer to Figure 9A, the gate-on voltage of the EM signal is applied to the first EM line in the first frame period, and the EM transistors Tem in the first pixel circuits PXL_11, …, PXL_N1 connected to the first EM line are turned on. That is, when the EM transistors Tem in the first pixel circuits PXL_11, …, PXL_N1 are turned on, a pixel driving voltage is applied to drive the light-emitting elements EL in the first pixel circuits PXL_11, …, PXL_N1, the second pixel circuits PXL_12, …, PXL_N2, and the third pixel circuits PXL_13, …, PXL_N3.

[0081] At this time, a gate-off voltage is applied to the EM transistors Tem in the second pixel circuits PXL_12, …, PXL_N2 and the third pixel circuits PXL_13, …, PXL_N3 to turn them off.

[0082] Refer to Figure 9B , the gate-on voltage of the EM signal is applied to the second EM line in the second frame period, and the EM transistors Tem in the second pixel circuits PXL_12, …, PXL_N2 connected to the second EM line are turned on. That is, when the EM transistors Tem in the second pixel circuits PXL_12, …, PXL_N2 are turned on, a pixel driving voltage is applied to drive the light-emitting elements EL in the second pixel circuits PXL_12, …, PXL_N2, the third pixel circuits PXL_13, …, PXL_N3, and the first pixel circuits PXL_11, …, PXL_N1.

[0083] At this time, a gate-off voltage is applied to the EM transistors Tem in the first pixel circuits PXL_11, …, PXL_N1 and the third pixel circuits PXL_13, …, PXL_N3 to turn them off.

[0084] Refer to Figure 9C , the gate-on voltage of the EM signal is applied to the third EM line in the third frame period, and the EM transistors Tem in the third pixel circuits PXL_13, …, PXL_N3 connected to the third EM line are turned on. That is, when the EM transistors Tem in the third pixel circuits PXL_13, …, PXL_N3 are turned on, a pixel driving voltage is applied to drive the light-emitting elements EL in the third pixel circuits PXL_13, …, PXL_N3, the first pixel circuits PXL_11, …, PXL_N1, and the second pixel circuits PXL_12, …, PXL_N2.

[0085] At this time, a gate-off voltage is applied to the EM transistors Tem in the first pixel circuits PXL_11, …, PXL_N1 and the second pixel circuits PXL_12, …, PXL_N2 to turn them off.

[0086] In a state where the light-emitting element is driven at a 100% duty cycle, the duty cycle for driving the EM transistor is approximately 33%. In this case, the EM transistor shares the EM signal in units of three horizontal periods (3H).

[0087] In this way, when three pixel circuits are connected, the EM elements of the three pixel circuits are sequentially turned on during each frame period, and the light-emitting elements in the three pixel circuits are all driven. Therefore, all the light-emitting elements can be driven by alternately driving the three EM elements.

[0088] Figure 10 FIG. is a diagram showing a pixel circuit according to a fifth embodiment of the present disclosure.

[0089] Refer to Figure 10 , a pixel circuit according to another embodiment includes a first pixel circuit PXL1 and a second pixel circuit PXL2 arranged in a row direction. Each of the first pixel circuit PXL1 and the second pixel circuit PXL2 includes a light-emitting element EL, a driving transistor DT for driving the light-emitting element EL, and an EM transistor Tem for switching a current path connected to the driving transistor DT.

[0090] The first pixel circuit PXL1 includes a first light-emitting element EL1, a first driving transistor DT1, and a first EM transistor Tem1. The first EM transistor Tem1 is connected between a first power supply line and a first a node N1a, the first driving transistor DT1 is connected between the first a node N1a and a second a node N2a, and the first light-emitting element EL1 is connected between the second a node N2a and a low-potential voltage line.

[0091] When the applied first EM signal EM1 is a gate-conducting voltage, the first EM transistor Tem1 is turned on and supplies a pixel driving voltage EVDD to the first a node N1a. The first EM transistor Tem1 includes a gate connected to a gate line to which the first EM signal EM1 is applied, a first electrode connected to the first power supply line to which the pixel driving voltage is supplied, and a second electrode connected to the first a node N1a.

[0092] The first driving transistor DT1 drives the first light-emitting element EL1 by supplying current to the first light-emitting element EL1 according to the gate-source voltage Vgs. The first driving transistor DT1 includes a gate to which a data voltage is applied, a first electrode connected to the first a node N1a, and a second electrode connected to the second a node N2a.

[0093] The second pixel circuit PXL2 includes a second light-emitting element EL2, a second driving transistor DT2, and a second EM transistor Tem2. The second EM transistor Tem2 is connected between a first power supply line and a first b node N1b, the second driving transistor DT2 is connected between the first b node N1b and a second b node N2b, and the second light-emitting element EL2 is connected between the second b node N2b and a second power supply line.

[0094] When the second EM signal EM2 is applied as a gate-on voltage, the second EM transistor Tem2 conducts and supplies the pixel driving voltage EVDD to the first b node N1b. The second EM transistor Tem2 includes a gate connected to a gate line to which the second EM signal EM2 is applied, a first electrode connected to the first power supply line to which the pixel driving voltage is supplied, and a second electrode connected to the first b node N1b.

[0095] The second driving transistor DT2 drives the second light-emitting element EL2 by supplying current to the second light-emitting element EL2 according to the gate-source voltage Vgs. The second driving transistor DT2 includes a gate to which a data voltage is applied, a first electrode connected to the first b node N1b, and a second electrode connected to the second b node N2b.

[0096] In this case, a first a node N1a in the first pixel circuit PXL1 and a first b node N1b in the second pixel circuit PXL2 are connected to each other. The first a node N1a and the first b node N1b are a single first node N1 connected by a connection line. When the gate-on voltage of the first EM signal EM1 is applied to the first EM transistor Tem1, the first EM transistor Tem1 conducts and supplies the pixel driving voltage to the first a node N1a and the first b node N1b. The first driving transistor DT1 connected to the first a node N1a and the second driving transistor DT2 connected to the first b node N1b supply current to the first light-emitting element EL1 and the second light-emitting element EL2 according to the gate-source voltage, thereby driving the first light-emitting element EL1 and the second light-emitting element EL2.

[0097] In addition, when the gate-on voltage of the second EM signal EM2 is applied to the second EM transistor Tem2, the second EM transistor Tem2 conducts and supplies the pixel driving voltage to the first b node N1b and the first a node N1a. The second driving transistor DT2 connected to the first b node N1b and the first driving transistor DT1 connected to the first a node N1a supply current to the second light-emitting element EL2 and the first light-emitting element EL1 according to the gate-source voltage, thereby driving the second light-emitting element EL2 and the first light-emitting element EL1.

[0098] Figure 11 and Figure 12is a circuit diagram showing a pixel circuit according to other embodiments of the present disclosure.

[0099] Referring to Figure 11 , the pixel circuit according to an embodiment includes a first pixel circuit PLX1 and a second pixel circuit PLX2 arranged in a row direction. Each of the first pixel circuit PLX1 and the second pixel circuit PLX1 includes a light-emitting element EL, a driving transistor DT for driving the light-emitting element EL, an EM transistor Tem for switching a current path connected to the driving transistor DT, a sensing transistor Tsense, a scanning transistor Tscan, and a capacitor Cst for storing a gate-source voltage Vgs of the driving transistor DT.

[0100] Referring to Figure 12 , the pixel circuit according to an embodiment includes a first pixel circuit PLX1 and a second pixel circuit PLX2 arranged in a row direction. Each of the first pixel circuit PLX1 and the second pixel circuit PLX2 further includes an initialization transistor Tinit connected between an initialization voltage line and a third node. In this pixel circuit, the driving transistor DT, the EM transistor Tem, the sensing transistor Tsense, the scanning transistor Tscan, and the initialization transistor Tinit can be implemented as n-channel oxide transistors.

[0101] The initialization transistor Tinit applies an initialization voltage V INIT . The initialization voltage V INIT is applied to the first node N1 through the initialization voltage line.

[0102] Figure 13A And Figure 13B is a diagram showing Figure 10 the operating principle of the pixel circuit shown.

[0103] Referring to Figure 13A , in an odd frame period, a gate conduction voltage of a first EM signal EM1 is applied to an odd EM line, and the EM transistor Tem in each odd pixel circuit PXL_11, PXL_21, PXL_31, and PXL_41 connected to the odd EM line is turned on. When the EM transistor Tem in the odd pixel circuits PXL_11, PXL_21, PXL_31, and PXL_41 is turned on, a pixel driving voltage is applied, and all the light-emitting elements EL of the odd pixel circuits PXL_11, PXL_21, PXL_31, PXL_41 and the even pixel circuits PXL_12, PXL_22, PXL_32, PXL_42 are driven.

[0104] At this time, a gate cut-off voltage is applied to the EM transistor in the even pixel circuit to turn it off.

[0105] Refer to Figure 13B During the even frame period, the gate conduction voltage of the second EM signal EM2 is applied to the even EM lines, and the EM transistors Tem in the even pixel circuits PXL_12, PXL_22, PXL_32, and PXL_42 connected to the even EM lines are turned on. When the EM transistors Tem in the even pixel circuits PXL_12, PXL_22, PXL_32, and PXL_42 are turned on, the pixel driving voltage is applied, and all the light-emitting elements EL of the even pixel circuits PXL_12, PXL_22, PXL_32, PXL_42 and the odd pixel circuits PXL_11, PXL_21, PXL_31, PXL_41 are driven.

[0106] At this time, the gate cut-off voltage is applied to the EM transistors in the odd pixel circuits to turn them off.

[0107] In a state where the light-emitting elements are driven with a 100% duty ratio, the duty ratio of driving the EM transistors is 50%. In this case, the EM transistors share the EM signal in units of two horizontal periods (2H).

[0108] Figure 14 FIG. is a diagram showing a pixel circuit according to an eighth embodiment of the present disclosure.

[0109] Refer to Figure 14 According to the eighth embodiment, the pixel circuit includes a first pixel circuit PLX1, a second pixel circuit PXL2, and a third pixel circuit PXL3 arranged in the row direction. Each of the first pixel circuit PXL1, the second pixel circuit PXL2, and the third pixel circuit PXL3 includes a light-emitting element EL1, EL2, or EL3, a driving transistor DT1, DT2, or DT3 for driving the light-emitting element EL1, EL2, or EL3, and an EM transistor Tem1, Tem2, or Tem3 for switching the current path connected to the driving transistor DT1, DT2, or DT3.

[0110] In this case, a first a-node N1a in the first pixel circuit PXL1, a first b-node N1b in the second pixel circuit PXL2, and a first c-node N1c in the third pixel circuit PXL3 are connected to each other. The first a-node N1a, the first b-node N1b, and the first c-node N1c are a first node N1 connected by a connection line. When the gate conduction voltage of the EM signal is applied to the EM transistor Tem in the first pixel circuit PXL1, the EM transistor Tem in the second pixel circuit PXL2, or the EM transistor Tem in the third pixel circuit PXL3, the EM transistor Tem conducts and supplies the pixel driving voltage EVDD to the first node N1 of the first pixel circuit PXL1, the second pixel circuit PXL2, and the third pixel circuit PXL3. The driving transistor DT1 connected to the first a-node N1a in the first pixel circuit PXL1, the driving transistor DT2 connected to the first b-node N1b in the second pixel circuit PXL2, and the driving transistor DT3 connected to the first c-node N1c in the third pixel circuit PXL3 supply current to the first light-emitting element EL1, the second light-emitting element EL2, and the third light-emitting element EL3 according to the gate-source voltage, thereby driving the first light-emitting element EL1, the second light-emitting element EL2, and the third light-emitting element EL3.

[0111] In a state where the light-emitting element is driven at a 100% duty cycle, the duty cycle of driving the EM transistor is approximately 33%. In this case, the EM transistor shares the EM signal in units of three horizontal periods (3H).

[0112] Figure 15 and Figure 16 are diagrams showing various pixel circuits applicable to the pixel circuit of the present disclosure.

[0113] Referring to Figure 15 , the pixel circuit includes a light-emitting element EL, a driving transistor DT for driving the light-emitting element EL, and an EM transistor Tem for switching the current path connected to the driving transistor DT.

[0114] The EM transistor Tem is connected between the driving transistor DT and the light-emitting element EL, and is connected to the light-emitting element EL through an EM common node 100. The EM transistor Tem is connected to all the light-emitting elements in at least one other pixel circuit through the EM common node 100.

[0115] Referring to Figure 16 , the pixel circuit includes a light-emitting element EL, a driving transistor DT for driving the light-emitting element EL, and a first EM transistor Tem1 and a second EM transistor Tem2 for switching the current path connected to the driving transistor DT.

[0116] The first EM transistor Tem1 is connected between the driving transistor DT and the first power supply line to which the pixel driving voltage EVDD is applied, and is connected to the driving transistor DT through the first EM common node 101. The first EM transistor Tem1 is connected to all the driving transistors in at least one other pixel circuit through the first EM common node 101.

[0117] The second EM transistor Tem2 is connected between the driving transistor DT and the light-emitting element EL, and is connected to the light-emitting element EL through the second EM common node 102. The second EM transistor Tem2 is connected to all the light-emitting elements in at least one other pixel circuit through the second EM common node 102.

[0118] Embodiments may, but are not limited to, be implemented using various pixel circuits as described above and may apply any type of pixel circuit capable of sharing EM signals.

[0119] Hereinafter, a display device including a display panel to which a pixel circuit according to an embodiment is applied will be described.

[0120] Figure 17 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0121] Referring to Figure 17 , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to the pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit.

[0122] The display panel 100 includes a pixel array AA for displaying an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form.

[0123] The pixel array AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a row of pixels arranged in the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share the gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is a time obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0124] Pixels are connected to each other at least every two pixels in the column direction or the row direction. In this case, the source nodes of the EM transistors in the plurality of pixels are connected to each other and share the EM signal.

[0125] A touch sensor may be disposed on the display panel 100. A separate touch sensor may be used to sense a touch input or the touch input may be sensed through pixels. The touch sensor may be disposed as an on-cell type or an add-on type on the screen of the display panel or implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0126] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic thin film may be disposed on the backplane of the plastic OLED panel, and a pixel array AA may be formed on the organic thin film.

[0127] The backplane of the plastic OLED may be a polyethylene terephthalate (PET) substrate. The organic thin film is formed on the backplane. The pixel array AA and the touch sensor array may be formed on the organic thin film. The backplane blocks moisture penetration so that the pixel array AA is not exposed to moisture. The organic thin film may be a thin polyimide (PI) film substrate. A multilayer buffer film may be formed of an insulating material (not shown) on the organic thin film. Lines may be formed on the organic thin film to supply power or signals applied to the pixel array AA and the touch sensor array.

[0128] To achieve colors, each pixel may be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each pixel may also include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit. The pixel circuit is connected to a data line 102 and a gate line 103.

[0129] Hereinafter, a pixel may be interpreted to have the same meaning as a sub-pixel.

[0130] A power supply 140 generates DC power required for a display panel driving circuit that drives the pixel array AA and the display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 may adjust a DC input voltage from a host system (not shown) to generate DC voltages, for example, a gamma reference voltage VGMA, a gate-on voltage VGH and VEH, a gate-off voltage VGL and VEL, a pixel driving voltage EVDD, and a pixel low potential power supply voltage EVSS. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltage VGH and VEH and the gate-off voltage VGL and VEL are supplied to the gate driver 120. The pixel driving voltage EVDD and the pixel low potential power supply voltage EVSS are generally supplied to the pixels.

[0131] The display panel driving circuit writes pixel data (digital data) of an input image into the pixels of the display panel 100 under the control of the timing controller (TCON) 130.

[0132] The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0133] A demultiplexer (DEMUX) 112 can be provided between the data driver 110 and the data lines 102. The demultiplexer 112 sequentially connects one channel of the data driver 110 to multiple data lines 102 and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer array 112 can be omitted. In this case, the output buffer AMP of the data driver 110 is directly connected to the data lines 102.

[0134] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. Figure 1 The touch sensor driver is omitted. In a mobile device, the timing controller 130, the power supply 140, the data driver 110, etc. can be integrated into one driving integrated circuit (IC).

[0135] The data driver 110 generates a data voltage Vdata by converting the pixel data of the input image received from the timing controller 130 into a gamma-compensated voltage using a digital-to-analog converter (DAC) in each frame period. The gamma reference voltage VGMA is divided for each gray level by a voltage divider circuit. The gamma-compensated voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output through the output buffer AMP in each channel of the data driver 110.

[0136] In the data driver 110, the output buffer AMP included in one channel can be connected to adjacent data lines 102 through the demultiplexer array 112. The demultiplexer array 112 can be directly formed on the substrate of the display panel 100 or integrated into one driving IC together with the data driver 110.

[0137] The gate driver 120 can be implemented as an in-panel gate (GIP) circuit directly formed on the border BZ area of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially provide the gate signals to the gate lines 103 by shifting the gate signals using a shift register.

[0138] The gate signal may include a scan signal for selecting a row of pixels into which data is written in synchronization with a data voltage, and an EM signal that defines a light emission time of the pixels charged with the data voltage.

[0139] The gate driver 120 may include a scan driver 121 and an EM driver 122.

[0140] The scan driver 121 outputs a scan signal SCAN in response to a start pulse and a shift clock from the timing controller 130, and shifts the scan signal SCAN according to the shift clock timing. The EM driver 122 outputs an EM signal EM in response to a start pulse and a shift clock from the timing controller 130, and sequentially shifts the EM signal EM according to the shift clock. Accordingly, the scan signal SCAN and the EM signal EM are sequentially provided to the gate lines 103 of the pixel lines L1 to Ln. In the case of a borderless model, at least some transistors constituting the gate driver 120 and clock wirings may be dispersedly disposed in the pixel array AA.

[0141] The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0142] The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system.

[0143] The timing controller 130 multiplies an input frame frequency by i and controls an operation timing of the display panel driving circuit at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternating Line) scheme.

[0144] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling an operation timing of the data driver 110, MUX signals MUX1 and MUX2 for controlling an operation timing of the demultiplexer array 112, and a gate timing control signal for controlling an operation timing of the gate driver 120.

[0145] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be understood to fall within the scope of the present disclosure.

Claims

1. A pixel circuit, comprising: A first pixel circuit, the first pixel circuit including a gate electrode of a first EM transistor to which a pulse of a first EM signal is applied and a first driving transistor for driving a first light-emitting element; And A second pixel circuit, the second pixel circuit including a gate electrode of a second EM transistor to which a pulse of a second EM signal is applied and a second driving transistor for driving a second light-emitting element, Wherein, a node between the first EM transistor and the first driving transistor is connected to a node between the second EM transistor and the second driving transistor, Wherein, the first EM transistor is connected between a first power supply line and the first driving transistor, and when the first EM transistor is turned on, a pixel driving voltage of the first power supply line is supplied to the first driving transistor, so that the first driving transistor drives the first light-emitting element to emit light, Wherein, the second EM transistor is connected between a second power supply line and the second driving transistor, and when the second EM transistor is turned on, a pixel driving voltage of the second power supply line is supplied to the second driving transistor, so that the second driving transistor drives the second light-emitting element to emit light, Wherein, the first pixel circuit and the second pixel circuit share a data line with each other.

2. The pixel circuit according to claim 1, wherein, The first pixel circuit and the second pixel circuit share a scan line with each other, and the EM lines of the first pixel circuit and the second pixel circuit are different from each other.

3. The pixel circuit according to claim 1, wherein, The light-emitting duty cycle of the first light-emitting element during a frame period and the light-emitting duty cycle of the second light-emitting element during a frame period are greater than the duty cycles of the first EM signal and the second EM signal.

4. The pixel circuit according to claim 1, wherein, The second pixel circuit includes at least one pixel circuit, and The first pixel circuit and the at least one pixel circuit receive pulses of the EM signal in different frame periods.

5. The pixel circuit according to claim 1, wherein, The first pixel circuit further includes: A first scan transistor, the first scan transistor being connected between the data line and the gate electrode of the driving transistor; A first sensing transistor, the first sensing transistor being connected between the source electrode of the driving transistor and a reference voltage line; and A first capacitor, the first capacitor being connected between the gate electrode and the source electrode.

6. The pixel circuit according to claim 1, wherein, The second pixel circuit further includes: A second scan transistor, the second scan transistor being connected between the data line and the gate electrode of the driving transistor; A second sensing transistor, the second sensing transistor being connected between the source electrode of the driving transistor and a reference voltage line; and A second capacitor, the second capacitor being connected between the gate electrode and the source electrode.

7. A display panel, comprising: A plurality of pixels, each pixel including: a light-emitting element, the light-emitting element emitting light by a current flowing through a current path formed between a high-potential voltage line and a low-potential voltage line; and, The pixel circuit according to claim 1, configured to drive the light-emitting elements of the plurality of pixels, Wherein, the current path is connected between at least two pixel circuits.

8. The display panel according to claim 7, wherein, The light emission duty ratio of the first light-emitting element during one frame period and the light emission duty ratio of the second light-emitting element during one frame period are greater than the duty ratios of the first EM signal and the second EM signal.

9. The display panel according to claim 7, wherein, The at least two pixel circuits receive pulses of the EM signal in different frame periods.

10. The display panel according to claim 7, wherein, Each of the at least two pixel circuits further includes: A driving transistor that supplies current through the current path; A scanning transistor connected between the data line and the gate electrode of the driving transistor; A sensing transistor connected between the source electrode of the driving transistor and the reference voltage line; and A capacitor connected between the gate electrode and the source electrode.

11. The display panel according to claim 7, wherein, The at least two pixel circuits share a scanning line with each other, and the EM lines of the at least two pixel circuits are different from each other.

12. The display panel according to claim 7, wherein, All transistors in the panel including the pixel circuit are implemented as oxide thin film transistors (TFTs) including n-channel oxide semiconductors.

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