Memory device and its false signal prevention method
By introducing a data strobe signal input circuit, a transmission signal generation circuit, and a blocking circuit into the DDR SDRAM device, and using a burst counter circuit to count and block the input of the data strobe signal, the problem of synchronization failure after writing is solved, and the accuracy and fast response of high-frequency data transmission are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2022-05-18
- Publication Date
- 2026-05-29
AI Technical Summary
In DDR SDRAM devices, as the system clock frequency increases, timing budget becomes tight, leading to frequent post-write synchronization failures, especially due to false signals causing the width of the data write signal ODD_D to decrease, resulting in the capture of incorrect data.
The system employs a data strobe signal input circuit, a transmission signal generation circuit, a data alignment circuit, and a blocking circuit. A burst counter circuit counts the number of data transmission bursts, generates a transmission signal synchronized with the rising or falling edge of the data strobe signal, and blocks the input of the data strobe signal in the subsequent synchronization timing to prevent the generation of false signals.
It effectively prevents false signals in the post-synchronization timing, ensures the accuracy of the data writing signal, realizes the rapid response of the high-frequency data strobe signal, and reduces data capture errors.
Smart Images
Figure CN115691589B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a memory device and a method for preventing false signals therefrom. Background Technology
[0002] Currently, double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices use a data strobe signal (DQS) for data gating. DQS latches data into the DRAM using a specific burst length (BL) and specific pre / post input timing. By using DQS to gating data, the skew between data and the system clock caused by the location difference between the system clock and the memory device can be reduced. However, as the system clock frequency increases, the timing budget becomes increasingly tight, and postamble failures occasionally occur in practical applications.
[0003] Figure 1 This is a timing diagram for a standard DDR SDRAM. (Reference) Figure 1 In conventional DDR SDRAM, when a write command is input, the DDR SDRAM receives the data signal DQ along with a data strobe signal commonly referred to as DQS. DQS is used as a clock signal to capture the corresponding input data from the data signal DQ. The DQS is amplified to generate an internal DQS, and a data write signal EVEN_D with a pulse synchronized with the rising edge of the internal DQS is generated, as well as a data write signal ODD_D with a pulse synchronized with the falling edge of the internal DQS. The data write signals EVEN_D and ODD_D are used to capture input data from the data signal DQ, respectively. Figure 1 As shown, when a spurious signal appears in the preceding pulse of the DQS, the falling edge of the internal DQS is incorrectly identified, and therefore the width of the data write signal ODD_D generated based on the preceding falling edge of the internal DQS becomes smaller. Consequently, a smaller amount of valid data is captured based on the data write signal ODD_D. Referring to data DHS1 to data DHS8 shown in the lower section, alignment data DHS1 and alignment data DHS2 are synchronized with the rising edges of the data write signals EVEN_D and ODD_D. Due to the spurious signal, the value of alignment data DHS2 changes prematurely, and therefore incorrect data is captured.
[0004] Therefore, there is a need to provide a device that can prevent synchronization failures after writing. Summary of the Invention
[0005] In view of the above, this disclosure provides a memory device and a method for preventing false signals therein, which can prevent unwanted false signals from appearing in the post-synchronization timing.
[0006] This disclosure provides a memory device including a data strobe signal input circuit, a transmission signal generation circuit, a data alignment circuit, and a blocking circuit. The data strobe signal input circuit is configured to input a data strobe signal. The transmission signal generation circuit is configured to generate a transmission signal having pulses synchronized with the rising or falling edge of the data strobe signal in response to a transmission command. The data alignment circuit is configured to align a data signal to be transmitted in response to the generated transmission signal. The blocking circuit is configured to block the input of the data strobe signal in the post-synchronization timing of the data strobe signal according to the number of bursts counted in each data transmission.
[0007] The blocking circuit includes a burst counter circuit configured to count the number of bursts at the start of data transmission and to output a blocking signal to block the input of the data strobe signal in response to the counted number of bursts exceeding the burst length of the memory device.
[0008] The burst counter circuit includes a first inverter, an asynchronous counter, a first logic circuit, and a second logic circuit. The first inverter is configured to invert a data strobe signal and output an inverted data strobe signal. The asynchronous counter includes a first flip-flop and a second flip-flop. The first flip-flop has a first data terminal, a first clock terminal, and a first asynchronous output terminal, wherein the first data terminal is configured to receive a reference signal, and the first clock terminal is configured to receive the inverted data strobe signal. The second flip-flop has a second data terminal, a second clock terminal, and a second asynchronous output terminal, wherein the second data terminal is connected to the second asynchronous output terminal, and the second clock terminal is configured to receive the output signal from the first asynchronous output terminal and the reference signal. The first logic circuit is configured to output an enable signal in response to the reference signal and the enabled output signal of the second asynchronous output terminal. The second logic circuit is configured to output a block signal in response to the output signal of the first logic circuit and the enabled inverted data strobe signal.
[0009] The burst counter circuit further includes a switch configured to provide a reference signal to a first input in response to a reset signal, wherein the reset signal is input to the reset terminals of the first and second flip-flops to reset the data latched in the first and second flip-flops.
[0010] Each of the first and second logic circuits includes a NAND gate and an inverter connected in series.
[0011] The burst length includes one of four, eight, and sixteen.
[0012] The transmission signal generation circuit includes a first transmission signal that generates pulses synchronized with the rising edge of the data strobe signal and a second transmission signal that generates pulses synchronized with the falling edge of the data strobe signal.
[0013] The data alignment circuit includes synchronously aligning the data signal to be transmitted in response to a first transmission signal and a second transmission signal.
[0014] The memory device further includes an amplifier configured to amplify a data strobe signal.
[0015] This disclosure provides a spoofing prevention method for a memory device. In the spoofing prevention method, a data strobe signal is a first input. A transmission signal is generated in response to a transmission command, having pulses synchronized with the rising or falling edge of the data strobe signal. A data signal to be transmitted is aligned in response to the generated transmission signal. The input of the data strobe signal is blocked in the post-synchronization timing of the data strobe signal based on the number of bursts counted in each data transmission.
[0016] The post-synchronization timing is the timing from the previous falling edge of the data strobe signal corresponding to the data transmission to the next rising edge of the data strobe signal.
[0017] The step of blocking the input of the data strobe signal in the post-synchronization timing of the data strobe signal based on the number of bursts counted in each data transmission includes counting the number of bursts counted from the start of data transmission, and outputting a blocking signal to block the input of the data strobe signal in response to the counted number of bursts exceeding the burst length of the memory device.
[0018] The step of generating a transmission signal having pulses synchronized with the rising or falling edge of a data strobe signal in response to a transmission command includes generating a first transmission signal having pulses synchronized with the rising edge of the data strobe signal, and generating a second transmission signal having pulses synchronized with the falling edge of the data strobe signal.
[0019] The step of aligning the data signal to be transmitted in response to the generated transmission signal includes synchronizing the data signal to be transmitted in response to the first transmission signal and the second transmission signal. Attached Figure Description
[0020] Figure 1 This is a timing diagram for a standard DDR SDRAM.
[0021] Figure 2 A block diagram of a memory device according to an embodiment of the present disclosure;
[0022] Figure 3 A flowchart illustrating a spurious signal prevention method for a memory device according to an embodiment of the present disclosure;
[0023] Figure 4 A circuit diagram of a memory device according to an embodiment of the present disclosure;
[0024] Figure 5 A circuit diagram of a burst counter circuit according to an embodiment of the present disclosure;
[0025] Figures 6 to 7 This is a timing diagram of a memory device according to an embodiment of the present disclosure.
[0026] Explanation of icon numbers
[0027] 20, 40: Memory devices;
[0028] 22: Data strobe signal input circuit;
[0029] 24: Signal generation circuit;
[0030] 26: Data alignment circuit;
[0031] 28: Blocking the circuit;
[0032] 50: Burst counter circuit;
[0033] 52: Asynchronous counter;
[0034] 54: Logic circuits;
[0035] 56: Logic circuits;
[0036] A: Amplifier;
[0037] BLK: Block signal;
[0038] D, D': Data end;
[0039] DATA_LAT: Block signal;
[0040] DHS3, DHS4, DHS5, DHS6, DHS7, DHS8: Data;
[0041] DHS1, DHS2: Alignment data;
[0042] DQ: Data signal;
[0043] DQS: Data strobe signal;
[0044] Inverting data strobe signal;
[0045] DQSb: Inverse data strobe signal;
[0046] EVEN_D, ODD_D: Data write signals;
[0047] FF, FF1, FF2: triggers;
[0048] INV1, INV2, INV3: Inverters;
[0049] M1: Switch;
[0050] ND2, ND3: NAND gates;
[0051] Q, Clock input and asynchronous output;
[0052] Q0, Q1, Q2, Q3: Mode signals;
[0053] RESET: Reset signal;
[0054] S302, S304, S306, S308: Steps;
[0055] VDD: Reference signal. Detailed Implementation
[0056] refer to Figure 2 In this embodiment, the memory device 20 is, for example, a double data rate (DDR) synchronous dynamic random access memory (SDRAM) or a low-power DDR (LPDDR) SDRAM that uses a data strobe signal (DQS) for data strobing. The memory device 20 includes a data strobe signal input circuit 22, a transmission signal generation circuit 24, a data alignment circuit 26, and a blocking circuit 28.
[0057] In some embodiments, the memory device 20 may further include a command interface for receiving various signals provided by a processor or controller to facilitate the transfer and reception of data to be written to or read from the memory device 20. The received signals include one or more clock signals from an external device. In DDR memory, a differential pair of clock signals comprising a positive clock signal and an inverse clock signal is used, and a clock input circuit can generate an internal clock signal based on the received positive and inverse clock signals, and supply the internal clock signal to an internal clock generator (e.g., a delay-locked loop (DLL) circuit) to generate a phase-controlled internal clock signal. The phase-controlled internal clock signal is supplied to the I / O interface and acts as a timing signal that determines the output timing of data.
[0058] To accelerate data rates within memory devices, a data strobe signal, commonly known as DQS, is used in memory devices such as DDR memory. The DQS is driven by an external processor or controller that sends data to be written, or by the memory device 20 that reads data, and serves as a clock signal to capture the corresponding input data. Like positive and negative clock signals, DQS can be provided as a differential pair of data strobe signals, thereby providing differential pair commands during read and write operations.
[0059] refer to Figure 3 The false signal prevention method is applicable to the memory device 20, and the detailed steps of the false signal prevention method of this embodiment will be described below with reference to the various components of the memory device 20.
[0060] First, in step S302, the data strobe signal input circuit 22 is configured to input a data strobe signal.
[0061] refer to Figure 4 In memory device 40, a data strobe signal DQS received from an external device (e.g., a processor) may be accompanied by an inverse data strobe signal DQSb, which is complementary to the data strobe signal DQS. These signals may be transmitted to amplifier A to generate an internal DQS and a complementary internal DQSF (dummy data strobe signal). Amplifier A modifies the power of the data strobe signal DQS from an external level to a level suitable for use in memory device 40.
[0062] The internal DQS is used to capture the data signal DQ at the correct cycle using the trigger FF to successfully initiate a write burst and to capture incoming write data using the captured write data DHS in the DQS domain. There may be an unknown phase relationship between the data strobe signal DQS and the external clock signal that generates the data signal DQ. The phase relationship of the data strobe signal DQS will be calibrated relative to the external clock to position the data strobe signal DQS correctly for capturing the data signal DQ. In some embodiments, the trigger FF may capture the data signal DQ at the falling edge of the internal DQS. Alternatively, in some embodiments, the trigger FF may capture the data signal DQ at the rising edge of the internal DQS.
[0063] In step S304, the transmission signal generation circuit 24 is configured to generate a transmission signal having pulses synchronized with the rising or falling edge of the data strobe signal in response to a transmission command. The transmission signal generation circuit 24 can generate a first transmission signal having pulses synchronized with the rising edge of the data strobe signal, and generate a second transmission signal having pulses synchronized with the falling edge of the data strobe signal.
[0064] In step S306, the data alignment circuit 26 is configured to align the data signal to be transmitted in response to the generated transmission signal. The data alignment circuit 26 can synchronously align the data signal to be transmitted in response to the first transmission signal and the second transmission signal.
[0065] In step S308, the blocking circuit 28 is configured to block the input of the data strobe signal in the post-synchronization timing of the data strobe signal according to the number of bursts counted in each data transmission. The post-synchronization timing is, for example, the timing from the previous falling edge of the data strobe signal corresponding to the data transmission to the next rising edge of the data strobe signal.
[0066] In some embodiments, the blocking circuit 28 is implemented by a burst counter circuit configured to count the number of bursts from the start of data transmission and to output a blocking signal to block the input of a data strobe signal in response to the number of bursts exceeding the burst length of the memory device. The burst length may be four, eight, or sixteen, depending on the type of memory device 20.
[0067] refer to Figure 5 The burst counter circuit 50 in this embodiment includes an inverter INV1, an asynchronous counter 52, logic circuit 54, and logic circuit 56. The inverter INV1 is configured to invert the data strobe signal DQS and output an inverted data strobe signal. The asynchronous counter 52 includes flip-flops FF1 and FF2. In some embodiments, flip-flops FF1 and FF2 are D flip-flops, which are not limited herein. Flip-flop FF1 has a data terminal D, a clock terminal, and an asynchronous output terminal Q, wherein the data terminal D is configured to receive a reference signal VDD, and the clock terminal is configured to receive an inverted data strobe signal. The flip-flop FF2 has a data input D', a clock input, and an asynchronous output. The data terminal D' is connected to the asynchronous output terminal. The clock input is configured to receive the output signal of the asynchronous output Q and the reference signal VDD. The logic circuit 54 includes a NAND gate ND2 and an inverter INV2, and is configured to respond to the reference signal VDD and the asynchronous output. The output signal is enabled, and an enable signal is output. Logic circuit 56 includes a NAND gate ND3 and an inverter INV3, and is configured to respond to the output signal of logic circuit 54 and the inverted data strobe signal. When enabled, the output blocking signal BLK is provided. Additionally, switch M1 is configured to provide a reference signal VDD to input D in response to the reset signal RESET, wherein the reset signal RESET is input to the reset terminals of flip-flops FF1 and FF2 to reset the data latched in flip-flops FF1 and FF2.
[0068] refer to Figure 6 This embodiment shows Figure 5 The relationship between the data strobe signal DQS and the mode signals Q0 to Q3 in the burst counter circuit 50 is illustrated. The mode signals Q0 to Q3 of the burst counter circuit 50 correspond to different burst counts on the rising edge (represented by the number "1") of the data strobe signal DQS. When the counted burst count reaches a predetermined value (represented by the number "8"), the mode signal Q3 is output and used to block the input of the data strobe signal DQS at the post-synchronization timing (i.e., the timing after the previous falling edge of DQS). By using the mode signal Q3 of the burst counter circuit 50 as the blocking signal, spurious signals that may appear at the post-synchronization timing of the data strobe signal DQS can be prevented. Compared to the internal delay blocking method, the effects of PVT (process, voltage, temperature) variations can be minimized, and a fast response with a high-frequency data strobe signal DQS can be achieved. It should be noted that different counters may be used for different types of memory devices. For example, 8-bit counters are used for DDR3 SDRAM or DDR4 SDRAM, while 16-bit counters are used instead for LPDDR4 SDRAM.
[0069] refer to Figure 7 In this embodiment, when a write command is input, the memory device receives a data signal DQ along with a data strobe signal commonly referred to as DQS. DQS is used as a clock signal to capture the corresponding input data from the data signal DQ. The DQS is amplified to generate an internal DQS, and a data write signal EVEN_D with a pulse synchronized with the rising edge of the internal DQS is generated, as well as a data write signal ODD_D with a pulse synchronized with the falling edge of the internal DQS. The data write signals EVEN_D and ODD_D are used to capture input data from the data signal DQ, respectively.
[0070] like Figure 7 As shown, when a spurious signal appears in the preceding pulse of the data strobe signal DQS, the falling edge of the data strobe signal DQS may be incorrectly identified. However, the blocking signal DATA_LAT generated according to the above embodiment can block the pulse caused by the spurious signal in the internal DQS. Therefore, the data write signals EVEN_D and ODD_D generated based on the rising and falling edges of the internal DQS are corrected and used to capture input data from the data signal DQ. Referring to the data DHS1 to data DHS8 shown below, the aligned data DHS1 and aligned data DHS2 are correctly synchronized with the rising edges of the data write signals EVEN_D and ODD_D.
[0071] In summary, according to embodiments of this disclosure, a memory device and a spurious signal prevention method thereof are proposed to perform programmed burst counting using a counter. Based on the number of bursts, the input of extended spurious signals in the data strobe signal on the subsequent synchronization timing can be prevented, and rapid response of high-frequency data strobe signals can be achieved.
[0072] Although this disclosure has been made public through the above embodiments, these embodiments are not intended to limit this disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the structure of this disclosure without departing from its scope or spirit. Therefore, the scope of protection of this disclosure falls within the appended claims.
Claims
1. A memory device, comprising: The data strobe signal input circuit is configured to input a data strobe signal. A transmission signal generation circuit is configured to generate a transmission signal having pulses synchronized with the rising or falling edge of the data strobe signal in response to a transmission command. A data alignment circuit is configured to align the data signal to be transmitted in response to the generated transmission signal. as well as A blocking circuit configured to block the input of the data strobe signal in the post-synchronization timing of the data strobe signal based on the number of bursts counted in each data transmission, wherein the blocking circuit includes: A burst counter circuit is configured to count the number of bursts at the start of the data transmission, and to output a blocking signal to block the input of the data strobe signal when the counted number of bursts exceeds the burst length of the memory device, wherein the burst counter circuit includes: A first inverter is configured to invert the data strobe signal and output an inverted data strobe signal; Asynchronous counters, including: A first flip-flop has a first data terminal, a first clock terminal, and a first asynchronous output terminal, wherein the first data terminal is configured to receive a reference signal, and the first clock terminal is configured to receive the inverted data strobe signal; and The second flip-flop has a second data terminal, a second clock terminal, and a second asynchronous output terminal, wherein the second data terminal is connected to the second asynchronous output terminal, and the second clock terminal is configured to receive the output signal of the first asynchronous output terminal and the reference signal; A first logic circuit is configured to output an enable signal in response to the reference signal and an output signal in which the second asynchronous output terminal is enabled. A second logic circuit is configured to output the blocking signal in response to the output signal of the first logic circuit and the enabled inverted data strobe signal; and A switch configured to provide a reference signal to a first input in response to a reset signal, wherein the reset signal is input to the reset terminals of the first and second flip-flops to reset data latched in the first and second flip-flops, wherein each of the first and second logic circuits includes a NAND gate and an inverter connected in series.
2. The memory device of claim 1, wherein the post-synchronization timing is the timing from the previous falling edge of the data strobe signal corresponding to the data transmission to the next rising edge of the data strobe signal.
3. The memory device of claim 1, wherein the burst length comprises one of four, eight, and sixteen.
4. The memory device of claim 1, wherein the transmission signal generation circuit includes generating a first transmission signal having a pulse synchronized with the rising edge of the data strobe signal and generating a second transmission signal having a pulse synchronized with the falling edge of the data strobe signal, wherein the data alignment circuit includes aligning the data signal to be transmitted synchronously in response to the first transmission signal and the second transmission signal.
5. The memory device according to claim 1, further comprising: An amplifier configured to amplify the data strobe signal.
6. A method for preventing spurious signals in a memory device, comprising: Input data strobe signal; A transmission signal that generates a pulse synchronized with the rising or falling edge of the data strobe signal in response to a transmission command; The data signal to be transmitted is aligned in response to the generated transmission signal. as well as The input of the data strobe signal is blocked in the post-synchronization timing of the data strobe signal according to the number of bursts counted in each data transmission, which includes: The function counts the number of bursts at the start of data transmission and outputs a blocking signal to block the input of the data strobe signal when the counted number of bursts exceeds the burst length of the memory device. This includes: The data gating signal is inverted by the first inverter and an inverted data gating signal is output. By inputting the reference signal and the inverted data gating signal into the first flip-flop, the first flip-flop generates a first output signal; By inputting the first output signal and the reference signal into the second flip-flop, the second flip-flop generates a second output signal, wherein the data terminal of the second flip-flop is connected to the asynchronous output terminal of the second flip-flop; The first logic circuit responds to the reference signal and the output signal that the second asynchronous output terminal is enabled, and outputs an enable signal; The blocking signal is output by the second logic circuit in response to the output signal of the first logic circuit and the enabled inverted data strobe signal; and A reference signal is provided to a first input terminal by responding to a reset signal via a switch, wherein the reset signal is input to the reset terminals of the first and second flip-flops to reset the data latched in the first and second flip-flops, wherein each of the first and second logic circuits includes a NAND gate and an inverter connected in series.
7. The spurious signal prevention method for a memory device according to claim 6, wherein the post-synchronization timing is the timing from the previous falling edge of the data strobe signal corresponding to the data transmission to the next rising edge of the data strobe signal.
8. The spurious signal prevention method for a memory device according to claim 6, wherein the step of blocking the input of the data strobe signal in the post-synchronization timing of the data strobe signal based on the number of bursts counted in each data transmission comprises: The number of bursts counted from the start of the data transmission is counted, and a blocking signal is output in response to the counted number of bursts exceeding the burst length of the memory device to block the input of the data strobe signal.
9. The spurious signal prevention method for a memory device according to claim 6, wherein the step of generating a transmission signal having a pulse synchronized with the rising or falling edge of the data strobe signal in response to a transmission command comprises: Generating a first transmission signal having a pulse synchronized with the rising edge of the data strobe signal, and generating a second transmission signal having a pulse synchronized with the falling edge of the data strobe signal, wherein the step of aligning the data signal to be transmitted in response to the generated transmission signals includes: The data signal to be transmitted is synchronized in response to the first transmission signal and the second transmission signal.