Hammer strike location determination method, circuit, and electronic equipment

Abstract

This disclosure relates to a hammer address determination method, a hammer address determination circuit, and an electronic device, belonging to the field of integrated circuit technology. The hammer address determination method is characterized by comprising: obtaining the first number of times the array receives an activation command within two adjacent refresh intervals; a current bit determination step: counting the second number of times the current bit of the row address in the array appears with a first preset value within two refresh intervals; if the second number is greater than half of the first number, then the first preset value is determined as the value of the current bit; if the second number is less than or equal to half of the first number, then a second preset value is determined as the value of the current bit; and taking the next bit in the hammer address as the current bit and proceeding to the current bit determination step to determine the value of the next bit, until the values ​​of all bits in the hammer address are determined. This disclosure provides a method for obtaining a row attack address.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a hammer address determination method, a hammer address determination circuit, and an electronic device. Background Technology

[0002] As the manufacturing precision of DRAM (Dynamic Random Access Memory) continues to improve, the integration of various components within DRAM is also increasing. This means that reading from or writing to one memory cell in DRAM may interfere with neighboring memory cells, causing current to flow into or out of adjacent memory cells.

[0003] Repeatedly performing the above read and write process is equivalent to performing a row hammer attack on memory cells, which may change the contents of adjacent memory cells, causing 0 to become 1, or 1 to become 0. This phenomenon is called bit flipping.

[0004] To implement appropriate row attack protection for adjacent memory cells and prevent bit flipping, obtaining the row attack address is an essential step.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a hammer address determination method, a hammer address determination circuit, and an electronic device, so as to provide a method for obtaining a row attack address.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0008] According to a first aspect of this disclosure, a method for determining a hammer impact location is provided, comprising:

[0009] Within two adjacent refresh intervals, obtain the first number of times the array receives the activation command;

[0010] Current bit determination step: Count the number of times the current bit of the row address in the array appears with a first preset value within the two refresh intervals; if the second number is greater than half of the first number, then the first preset value is determined as the value of the current bit; if the second number is less than or equal to half of the first number, then the second preset value is determined as the value of the current bit.

[0011] The next bit in the hammer address is used as the current bit to enter the current bit determination step, so as to determine the value of the next bit, until the values ​​of all bits in the hammer address are determined.

[0012] In an exemplary embodiment of this disclosure, when the number of counting bits for the first number of times and the second number of times are the same, the current bit determination step includes:

[0013] Remove the least significant bit from the first count and the most significant bit from the second count, compare the corresponding bits in the remaining first count and the remaining second count, and determine the comparison result for each corresponding bit;

[0014] The value of the current bit is determined based on the highest bit of the second count or the comparison result of each corresponding bit.

[0015] In one exemplary embodiment of this disclosure, determining the value of the current bit based on the comparison result between the highest bit of the second count and each corresponding bit includes:

[0016] If at least one of the comparison results between the highest bit of the second count and each corresponding bit is 1, the value of the current bit is determined to be 1.

[0017] According to a second aspect of this disclosure, a hammer address determination circuit is provided, comprising:

[0018] The first count determination module is used to obtain the first count of the row activation command within the interval between two adjacent refresh commands;

[0019] The address determination module is used to determine the value of all bits in the hammer impact address, and the address determination module includes at least one bit determination submodule;

[0020] The bit determination submodule is used to count the second number of times a preset value appears in the current bit of the row address in the array within the two refresh intervals; if the second number is greater than half of the first number, the preset value is determined as the value of the current bit; if the second number is less than or equal to half of the first number, a value other than the preset value is determined as the value of the current bit.

[0021] In one exemplary embodiment of this disclosure, the bit determination submodule includes: a comparison circuit, a multiplexer, and an OR gate; wherein,

[0022] The comparison circuit is used to compare the corresponding bits of the remaining first count and the remaining second count after removing the least significant bit in the first count and the most significant bit in the second count, and to determine the comparison result of each corresponding bit.

[0023] The OR gate is used to input the comparison result of the corresponding bit and the value of the highest bit in the second count, and to control the multiplexer to output the value of the current bit.

[0024] In one exemplary embodiment of this disclosure, the comparison circuit includes a first comparator and a second comparator; wherein,

[0025] The first comparator is used to compare the value of the second most significant bit of the second count with the value of the most significant bit of the first count, and output the comparison result;

[0026] The second comparator is used to compare the next corresponding bit in the remaining first count and the second count, and determine the comparison result of the corresponding bit.

[0027] In one exemplary embodiment of this disclosure, the first comparator includes a first preset comparison circuit. The input terminal of the first preset comparison circuit is connected to the value of the second most significant bit of the second number of times and the value of the most significant bit of the first number of times. The first result output by the first preset comparison circuit is the comparison result of the first comparator, and the second result output by the first preset comparison circuit is an intermediate result.

[0028] In one exemplary embodiment of this disclosure, the first preset comparison circuit includes a NAND gate, a NOR gate, and two second AND gates; wherein...

[0029] The NAND gate is used to connect the value of the second most significant bit of the second iteration with the value of the most significant bit of the first iteration;

[0030] One of the second AND gates is used to input the output signal of the NAND gate and the value of the second most significant bit of the second iteration, and outputs the first result;

[0031] Another second AND gate is used to access the output signal of the NAND gate and the value of the most significant bit of the first iteration;

[0032] The NOR gate is used to receive the output signals of the two second AND gates, and the output terminal of the NOR gate outputs the second result.

[0033] In one exemplary embodiment of this disclosure, the first result is used to indicate whether the value of the second most significant bit of the second number is greater than the value of the most significant bit of the first number;

[0034] The second result is used to indicate whether the value of the second highest bit of the second number is equal to the value of the highest bit of the first number.

[0035] In one exemplary embodiment of this disclosure, the second comparator includes a second preset comparison circuit and two first AND gates; wherein...

[0036] The second preset comparison circuit is used to input the value of the next corresponding bit in the remaining first count and second count;

[0037] One of the first AND gates is connected to the third result output by the second preset comparison circuit and the intermediate result after the previous corresponding bit comparison, and outputs the comparison result of the second comparator;

[0038] Another first AND gate is connected to the fourth result output by the second preset comparison circuit and the intermediate result after the previous corresponding bit comparison, and outputs the intermediate result of the second comparator.

[0039] In one exemplary embodiment of this disclosure, the second preset comparison circuit includes a NAND gate, a NOR gate, and two second AND gates; wherein...

[0040] The NAND gate is used to access the value of the next corresponding bit;

[0041] One of the second AND gates is used to input the output signal of the NAND gate and one of the values ​​in the next corresponding bit, and outputs a third result;

[0042] Another second AND gate is used to access the output signal of the NAND gate and another value in the next corresponding bit;

[0043] The NOR gate is used to receive the output signals of the two second AND gates, and the output terminal of the NOR gate outputs a fourth result.

[0044] In one exemplary embodiment of this disclosure, the third result is used to mark whether the value of the bit corresponding to the second number of times in the next corresponding bit is greater than the value of the bit corresponding to the first number of times;

[0045] The fourth result is used to mark whether the value of the bit corresponding to the second number of times in the next corresponding bit is equal to the value of the bit corresponding to the first number of times.

[0046] According to a third aspect of this disclosure, an electronic device is provided, characterized in that it comprises:

[0047] Command decoder, used to decode commands received by the array;

[0048] An address latch is used to latch the row addresses in the array;

[0049] The hammer impact address determination circuit described above;

[0050] The outputs of the command decoder and the address latch are connected to the input of the hammer address determination circuit.

[0051] In one exemplary embodiment of this disclosure, an AND gate is also included; wherein,

[0052] The input of the AND gate is connected to the output of the command decoder and the address latch;

[0053] The output of the AND gate is connected to the address determination module in the hammer address determination circuit.

[0054] In one exemplary embodiment of this disclosure, a NOT gate is also included; wherein,

[0055] When the first preset value in the hammer address determination circuit is 0, the NOT gate is positioned between the address latch and the AND gate to invert the row address before counting the second number of times.

[0056] The technical solution provided in this disclosure may include the following beneficial effects:

[0057] The hammer address determination method provided in the exemplary embodiments of this disclosure can count the number of times the hammer address is activated, i.e. the number of times it is accessed, within two adjacent refresh intervals by obtaining the first number of activation instructions. At the same time, within two refresh intervals, the second number of times each bit of the row address appears at a first preset value is counted, and the second number is compared with half of the first number to determine the value of each bit, thereby achieving the purpose of determining the hammer address.

[0058] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0059] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0060] Figure 1 A flowchart illustrating an exemplary embodiment of a hammer impact location determination method according to the present disclosure is shown schematically.

[0061] Figure 2 The diagram illustrates the structure of a counter used in a hammer impact address determination method according to an exemplary embodiment of the present disclosure.

[0062] Figure 3 A block diagram of a hammer address determination circuit according to an exemplary embodiment of the present disclosure is shown schematically.

[0063] Figure 4The schematic diagram illustrates a circuit diagram of a bit determination submodule in a hammer address determination circuit according to an exemplary embodiment of the present disclosure;

[0064] Figure 5 A schematic diagram of the structure of a comparison circuit according to an exemplary embodiment of the present disclosure is shown.

[0065] Figure 6 The diagram illustrates the structure of a first preset comparison circuit in a comparison circuit according to an exemplary embodiment of the present disclosure.

[0066] Figure 7 The schematic diagram illustrates a structural schematic of an electronic device according to an exemplary embodiment of the present disclosure;

[0067] Figure 8 The schematic diagram illustrates a structural schematic of another electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0068] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0069] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0070] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0071] Inside the chip, memory data is written to an array in units of bits. Each unit is called a cell. By specifying a row and a column, a cell can be accurately located. This is the basic principle of memory chip addressing.

[0072] If a row in an array is continuously hammered to execute read or write instructions, the adjacent rows will experience bit flips. Therefore, determining the address of the hammered row is crucial to preventing bit flips.

[0073] Typically, a row address consists of multiple bits. In binary counting, each bit can take the value of either 0 or 1. Therefore, to determine the row address to be hammered, it is necessary to determine the specific value of each bit of the row address.

[0074] This disclosure provides an exemplary embodiment of a hammer address determination method for determining the row address that is continuously hammered within two adjacent refresh intervals. (Refer to...) Figure 1 The method for determining the hammer impact location may specifically include the following steps:

[0075] S110. Within two adjacent refresh intervals, obtain the first number of times the array receives the activation command.

[0076] Bit flips typically occur within two adjacent refresh intervals. If a refresh command is executed, the impact of a row attack is reduced. Therefore, the exemplary embodiments of this disclosure only count the number of activations within two adjacent refresh intervals, that is, count the first occurrence of an activation command.

[0077] S130. Current bit determination steps: Count the number of times the current bit of the row address in the array appears with the first preset value within the two refresh intervals; if the second number is greater than half of the first number, then the first preset value is determined as the value of the current bit; if the second number is less than or equal to half of the first number, then the second preset value is determined as the value of the current bit.

[0078] In determining the hammer address that is continuously accessed by the active instruction, it is necessary to determine the value of each bit of the hammer address. Step S130 is equivalent to a specific method for determining the specific value of each bit. Taking binary counting as an example, if the first preset value is 1, the second preset value is 0. Then, when the second number of times the current bit appears as 1 is greater than half of the first number, the value of the current bit is determined to be 1; when the second number of times the current bit appears as 1 is less than or equal to half of the first number, the value of the current bit is determined to be 0. In the actual process of determining each bit, the current bit can be determined starting from the highest bit of the hammer address, or it can be determined starting from the lowest bit or other bits. This exemplary embodiment does not make any special limitations on this.

[0079] It should be noted that, based on the above-described approach, any specific value of a digit in other counting methods falls within the protection scope of this disclosure.

[0080] S150. Take the next bit in the hammer address as the current bit and proceed to the current bit determination step to determine the value of the next bit, until the values ​​of all bits in the hammer address are determined.

[0081] By following the method for determining the specific value of the current bit in step S130, the values ​​of the remaining bits in the hammer address are determined, thereby determining the specific hammer address.

[0082] The hammer address determination method provided in the exemplary embodiments of this disclosure can count the number of times the hammer address is activated, i.e. the number of times it is accessed, within two adjacent refresh intervals by obtaining the first number of activation instructions. At the same time, within two refresh intervals, the second number of times each bit of the row address appears at a first preset value is counted, and the second number is compared with half of the first number to determine the value of each bit, thereby achieving the purpose of determining the hammer address.

[0083] In the exemplary embodiments of this disclosure, to facilitate comparison of the first count and the second count, the number of counters used to count the first count and the second count is the same; that is, the number of bits used to count the first count and the second count is the same. For example, if the number of bits for the first count and the second count are both 11 bits, and these 11 bits are used to count binary numbers, the maximum countable value is 2. 11 =2048. Typically, the array can receive no more than 2000 activation commands within two consecutive refresh intervals. Therefore, using an 11-bit binary counting method can satisfy the counting of the first and second counts without overflow.

[0084] Of course, it should be noted that in practical applications, the number of counters used to count the first and second counts can be set according to the actual situation. That is to say, the number of digits of the first count and the number of digits of the second count are not limited to 11 digits, but can be other digits. The exemplary implementation of this disclosure does not make any special limitation on this.

[0085] This disclosure provides an exemplary implementation using an 11-bit binary number as an example to illustrate the statistical process of the first and second counts. Other number systems can be implemented by referring to this method.

[0086] Reference Figure 2 The diagram shows a schematic of a counter used to count the first or second number. Figure 2 In this system, counter 1 201 is used to count the most significant bit, counter 2 202 is used to count the next most significant bit, and so on, with counter 11 211 used to count the least significant bit.

[0087] In an exemplary embodiment of this disclosure, when the number of digits in the first count and the second count are the same, the current digit determination step may specifically include: removing the least significant digit in the first count and the most significant digit in the second count, comparing the corresponding digits in the remaining first count and the remaining second count, and determining the comparison result for each corresponding digit; finally, the value of the current digit may be determined based on the most significant digit of the second count or the comparison result for each corresponding digit.

[0088] For binary numbers, if the highest bit of the second number is A_CNT <10> If the value is 1, it means that the second number is more than half of the first number. In this case, the value of the current digit can be determined as 1 based on the highest digit of the second number.

[0089] If the highest bit of the second number is not 1, then we need to compare the first number of times the lowest bit is removed with the second number of times the highest bit is removed, bit by bit. After removing the lowest bit of the first number, the resulting number is half of the first number. Therefore, to compare the second number with half of the first number, we need to compare them bit by bit, starting from the highest bit. Taking 11 bits as an example, the comparison result can be Compare... <9> Compare <8> ...Compare <0> There are a total of 10 comparison results. If any one of these 10 results is 1, then the value of the current bit can be determined as 1.

[0090] It should be noted that during the comparison process, if the result of the higher-order bit is 1, then the remaining bits do not need to be compared again, thus reducing the workload of comparison. For example, in Compare... <9> When the value is 1, the current bit can be set to 1 without needing to determine the subsequent Compare bit. <8> ...Compare <0> The same principle applies to other cases to reduce unnecessary workload.

[0091] In an exemplary embodiment of this disclosure, when the first preset value is 0, the second preset value is 1. Therefore, when the second occurrence of 0 in the current bit is greater than half the number of occurrences in the first bit, the value of the current bit is determined to be 0; when the second occurrence of 0 in the current bit is less than or equal to half the number of occurrences in the first bit, the value of the current bit is determined to be 1. Specifically, in determining the value of each bit, the row address can be inverted before counting the second number, thus allowing for processing with the first preset value being 1 and the second preset value being 0 as described above.

[0092] This disclosure also provides an exemplary embodiment of a hammer impact address determination circuit, which is used to implement the various steps in the hammer impact address determination method. (Refer to...) Figure 3 As shown, the hammer address determination circuit 300 may include: a first number determination module 310 and an address determination module 330; wherein,

[0093] The first count determination module 310 can be used to obtain the first count of the row activation instruction within the interval between two adjacent refresh instructions; the address determination module 330 can be used to determine the value of all bits in the hammer address. The address determination module includes at least one bit determination submodule 331, which is used to determine the value of each bit in the hammer address. Assuming that the hammer address has a total of 16 bits, there can be 16 bit determination submodules 331, with one bit determination submodule 331 corresponding to determine the value of one bit.

[0094] The bit determination submodule 331 can be used to count the second number of times the current bit of the row address in the array appears with a preset value within two refresh intervals; if the second number is greater than half of the first number, the preset value is determined as the value of the current bit; if the second number is less than or equal to half of the first number, the value other than the preset value is determined as the value of the current bit.

[0095] The hammer address determination circuit provided in the exemplary embodiment of this disclosure obtains the first number of activation instructions within two adjacent refresh intervals through the first number determination module 310, and can count the number of times the hammer address is activated, i.e. the number of times it is accessed, within two refresh intervals; at the same time, the address determination module 330 counts the second number of times each bit of the row address appears at the first preset value within two refresh intervals, and compares the second number with half of the first number, thereby determining the value of each bit, and thus achieving the purpose of determining the hammer address.

[0096] Reference Figure 4 In an exemplary embodiment of this disclosure, the bit determination submodule 331 may include: a comparison circuit 410, a multiplexer 420, and an OR gate 430; wherein,

[0097] The comparison circuit 410 can be used to compare corresponding bits in the remaining first and second rounds after removing the least significant bit in the first round and the most significant bit in the second round, and determine the comparison result for each corresponding bit. For example, determining the comparison result described above... <9> Compare <8> ...Compare <0> The comparison results for a total of 10 corresponding bits.

[0098] OR gate 430 can be used to input the comparison result of the corresponding bits mentioned above and the value of the most significant bit of the second number, and control the multiplexer 420 to output the value of the current bit. Specifically, when at least one of the comparison results of the most significant bit of the second number and each corresponding bit is 1, the multiplexer 420 can be controlled to output 1 to determine the value of the current bit as 1.

[0099] Reference Figure 5In an exemplary embodiment of this disclosure, the comparison circuit 410 includes at least a first comparator 411, which can be used to compare the value A16_CNT of the second most significant bit of the second number. <9> The value of the highest bit of the first number, ACT_CNT <10> and output the comparison result Compare <9> A16 represents the 16th bit of the hammer address; the other bits can be named accordingly.

[0100] The first comparator 411 is used to compare the value of the second most significant bit of the second number (A16_CNT) when the most significant bit of the second number is not 1. <9> With the highest bit of the first number ACT_CNT <10> Compare them.

[0101] The first comparator 411 includes a first preset comparison circuit, the input of which is connected to the value A16_CNT of the second most significant bit of the second number. <9> The value of the highest bit of the first number, ACT_CNT <10> The first result output by the first preset comparison circuit is the comparison result of the first comparator 411. <9> The second result output by the first preset comparator circuit is the intermediate result Middle9_10.

[0102] Reference Figure 6 The first preset comparison circuit may include a NAND gate 610, a NOR gate 620, and two second AND gates 630 and 640; wherein, the first preset comparison circuit is used to input signals A and B, and output signals X, Y, and Z. Figure 6 As shown, the input terminal of NAND gate 610 is used to receive signals A and B; the input terminal of second AND gate 630 is used to receive signal A and the output signal of NAND gate 610; the output terminal of second AND gate 630 is used to output signal X; the input terminal of second AND gate 640 is used to receive signal B and the output signal of NAND gate 610; the output terminal of second AND gate 640 is used to output signal Z; the input terminal of NOR gate 620 is used to receive the output signals of second AND gate 630 and second AND gate 640; the output terminal of NOR gate 620 is used to output signal Y.

[0103] for Figure 6 The first preset comparator circuit shown outputs signals X=1 and Y=Z=0 when the input signals A=1 and B=0, indicating that signal A is greater than signal B. When the input signals A=B, the output signals Y=1 and X=Z=0, indicating that signals A and B are equal. When the input signals A=0 and B=1, the output signals Z=1 and X=Y=0, indicating that signal A is less than signal B.

[0104] Based on the first preset comparison circuit described above, in the exemplary embodiment of this disclosure, the NAND gate 610 is used to input the value A16_CNT of the second most significant bit of the second number. <9> (Equivalent to signal A) and the value of the most significant bit of the first number, ACT_CNT <10> (Equivalent to signal B); one of the second AND gates 630 is used to input the output signal of the NAND gate 610 and the value of the second most significant bit A16_CNT. <9> and output the first result Compare <9> (equivalent to signal X); another second AND gate 640 is used to connect the output signal of NAND gate 610 and the value of the highest bit of the first number, ACT_CNT. <10> The NOR gate 620 is used to input the output signals of two second AND gates 630 and 640, and the output of the NOR gate 620 outputs the second result Middle9_10 (equivalent to signal Y). If the first result is compared... <9> It is 1, that is, A16_CNT <9> Greater than ACT_CNT <10> ,but Figure 4 The multiplexer 420 will output a high level VDD1, thus setting the 16th bit of the hammer address to 1. The first result, Compare... <9> The second result, Middle9_10, is used to indicate whether the value of the second most significant digit of the second number is greater than the value of the most significant digit of the first number.

[0105] However, if we compare the first result of the output (Compare) <9> If it is 0, it means A16_CNT <9> Not greater than ACT_CNT <10> That is, A16_CNT <9> Equal to ACT_CNT <10> Or A16_CNT <9> Less than ACT_CNT <10> If A16_CNT <9> Equal to ACT_CNT <10> If the second result Middle9_10 = 1, it means that this bit is equal, and we need to continue comparing the next bit. If A16_CNT <9> Less than ACT_CNT <10> If the result is true, it means that the second result Middle9_10 = 0, and the code proceeds to the next comparator.

[0106] In an exemplary embodiment of this disclosure, the comparison circuit 410 further includes a second comparator 412, which is used to compare the next corresponding bit in the remaining first and second counts and determine the comparison result of the corresponding bit. Assume that the value of the 16th bit of the hammer address is determined by the statistically analyzed second and first counts of the 11 bits. Then, referring to... Figure 5 As shown, the second comparator 412 requires a maximum of 9 units.

[0107] like Figure 5 As shown, the second comparator 412 includes a second preset comparator circuit 4121 and two first AND gates 4122 and 4123; wherein,

[0108] The second preset comparison circuit 4121 is used to input the value of the next corresponding bit in the remaining first and second counts. If the second comparator 412 is immediately after the first comparator 411, then the second preset comparison circuit 4121 is used to input the value A16_CNT of the next bit after the second most significant bit of the second count. <8> The value of the second most significant digit of the first number, ACT_CNT <9> .

[0109] One of the first AND gates 4122 is connected to the third result output by the second preset comparison circuit 4121 and the intermediate result Middle9_10 after comparing the previous corresponding bit, and outputs the comparison result Compare of the second comparator. <8> Another first AND gate 4123 is connected to the fourth result output by the second preset comparison circuit 4121 and the intermediate result Middle9_10 after the previous corresponding bit comparison, and outputs the intermediate result Middle8_10 of the second comparator. In the exemplary embodiment of this disclosure, the second preset comparison circuit 4121 is essentially ANDed with the fourth result output by the second preset comparison circuit 4121 and the intermediate result Middle8_10 of the second comparator. Figure 6 The internal structures of the first preset comparison circuits shown are the same; the difference lies in the specific values ​​they input. The second preset comparison circuit 4121 also includes a NAND gate, a NOR gate, and two second AND gates; wherein the NAND gate is used to input the value of the next corresponding bit, for example, the value of the bit following the second most significant bit of the second number, A16_CNT. <8> The value of the second most significant digit of the first number, ACT_CNT <9> .

[0110] One of the second AND gates is used to connect the output signal of the NAND gate to one of the values ​​in the next corresponding bit, such as A16_CNT. <8> And output the third result Compare <8> Another second AND gate is used to input the output signal of the NAND gate and another value in the next corresponding bit, such as ACT_CNT. <9> The NOR gate is used to connect the output signals of two second AND gates, and the output of the NOR gate outputs the fourth result, Middle8_10. The third result is used to indicate whether the value of the bit corresponding to the second number in the next corresponding bit is greater than the value of the bit corresponding to the first number; the fourth result is used to indicate whether the value of the bit corresponding to the second number in the next corresponding bit is equal to the value of the bit corresponding to the first number.

[0111] If the second result Middle9_10 = 0, then after passing through the second comparator 412, the output of this second result will always be 0, i.e., Compare <8> =0, and Middle8_10 =0, then, referring to Figure 5 This 0 will be passed on indefinitely, ensuring that all subsequent comparisons result in 0. This also indicates that A16_CNT... <9> Less than ACT_CNT <10> This means that the second number is less than half of the first number.

[0112] Additionally, it should be noted that the third result, Compare... <8> It contains not only comparison information for the current bit, but also information for Middle9_10. For example, the third result Compare <8> The value equal to 1 means that a result has been found in the current bit comparison. <8> The condition for Middle9_10 to equal 1 is that Middle9_10 = 1 (i.e., the previous digit is equal), and the current digit is greater than the result, meaning the second number is greater than half of the first number. The fourth result, Middle8_10, means the highest two digits are equal, so we need to continue comparing the next digit. Middle8_10 also contains information from Middle9_10. Comparing from the highest digit to the lowest, only when the preceding highest digits are equal is there any meaning in continuing to compare the lowest digits. If, at this time, the signals X and Y output by the second preset comparison circuit 4121 are both 0, then the comparison result indicates that the second number is less than half of the first number. Middle8_10 is 0, which will cause subsequent comparison results to all output 0, which also conforms to the less-than comparison result. Therefore, the comparison circuit 410 provided in the exemplary embodiment of this disclosure conforms to the comparison logic required in practice.

[0113] If the comparison result of the previous bit is equal, then the remaining second comparator 412 is needed to continue the comparison of the next bit successively, and output the corresponding comparison result Compare. <7> ...Compare <0> The intermediate results Middle7_10...Middle0_10 will not be described in detail here.

[0114] Based on the methods listed above, the 16th bit of the hammer address can be determined. The values ​​of the other 15 bits of the hammer address can be determined by referring to the above methods, which will not be elaborated here.

[0115] This disclosure also provides an electronic device, with reference to exemplary embodiments thereof. Figure 7 As shown, the electronic device may include: a command decoder 710, an address latch 720, and the aforementioned hammer address determination circuit 300; wherein,

[0116] Command decoder 710 can be used to decode commands received by the array, for example, Figure 7 The commands RESET_n, CKE, etc., shown are used; address latch 720 can be used to latch row addresses in the array; the outputs of command decoder 710 and address latch 720 are connected to the input of hammer address determination circuit 300. The specific structure and working principle of hammer address determination circuit 300 have been described in detail in the above embodiments and will not be repeated here. Command decoder 710 and address latch 720 can be selected and determined with reference to existing technologies, and this exemplary embodiment does not impose any special limitations on them.

[0117] In an exemplary embodiment of this disclosure, the electronic device further includes an AND gate 730, wherein the input of the AND gate 730 is connected to the output of the command decoder 710 and the address latch 720; the output of the AND gate 730 is connected to the address determination module in the hammer address determination circuit 300. The hammer address determination circuit 300 is used to determine the hammer address only when the command decoder 710 and the address latch 720 are simultaneously triggered to output signals.

[0118] In one optional exemplary embodiment, if the first preset value in the hammer address determination circuit is 0 and the second preset value is 1, then, referring to Figure 8 The electronic device may also include a NOT gate 810; the NOT gate 810 is disposed between the address latch 720 and the AND gate 730 for inverting the row address before counting the second number.

[0119] The electronic device provided in the exemplary embodiments of this disclosure, by setting a hammer address determination circuit, can determine the hammer address within two adjacent refresh intervals. This allows for row hammer protection of addresses adjacent to the hammer address before a bit flip occurs in the array, preventing bit flips from happening, improving the effectiveness of the data stored in the memory cell, and increasing the accuracy of data storage.

[0120] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this disclosure are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device including one or more servers, data centers, etc., that can be integrated with the medium. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)). In the embodiments of this disclosure, the computer may include the aforementioned devices.

[0121] Although this disclosure has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed disclosure. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0122] Although this disclosure has been described in conjunction with specific features and embodiments, it will be apparent that various modifications and combinations can be made therein without departing from the spirit and scope of this disclosure. Accordingly, this specification and drawings are merely exemplary illustrations of the disclosure as defined by the appended claims and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this disclosure. It is obvious that those skilled in the art can make various alterations and modifications to this disclosure without departing from its spirit and scope. Thus, this disclosure is also intended to include any such modifications and modifications that fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A method for determining the hammer impact location, characterized in that, include: Within two adjacent refresh intervals, obtain the first number of times the array receives the activation command; Current bit determination step: Count the number of times the current bit of the row address in the array appears with a first preset value within the two refresh intervals; if the second number is greater than half of the first number, then the first preset value is determined as the value of the current bit; if the second number is less than or equal to half of the first number, then the second preset value is determined as the value of the current bit, wherein the second preset value and the first preset value are two binary values ​​that are logically opposite. The next bit in the hammer address is used as the current bit to enter the current bit determination step, so as to determine the value of the next bit, until the values ​​of all bits in the hammer address are determined.

2. The hammer impact location determination method according to claim 1, characterized in that, When the number of digits in the first count and the second count are the same, the current digit determination step includes: Remove the least significant bit from the first count and the most significant bit from the second count, compare the corresponding bits in the remaining first count and the remaining second count, and determine the comparison result for each corresponding bit; The value of the current bit is determined based on the highest bit of the second count or the comparison result of each corresponding bit.

3. The hammer impact location determination method according to claim 2, characterized in that, Determining the value of the current bit based on the comparison result between the highest bit of the second count and each corresponding bit includes: If at least one of the comparison results between the highest bit of the second count and each corresponding bit is 1, the value of the current bit is determined to be 1.

4. A hammer impact address determination circuit, characterized in that, include: The first count determination module is used to obtain the first count of activation commands received by the array within the interval between two adjacent refresh commands; The address determination module is used to determine the value of all bits in the hammer impact address, and the address determination module includes at least one bit determination submodule; The bit determination submodule is used to count the second number of times a preset value appears in the current bit of the row address in the array within the two refresh intervals; if the second number is greater than half of the first number, the preset value is determined as the value of the current bit; if the second number is less than or equal to half of the first number, the value other than the preset value is determined as the value of the current bit, and the value other than the preset value is a second preset value, which is a logically opposite binary value to the preset value.

5. The hammer impact address determination circuit according to claim 4, characterized in that, The bit determination submodule includes: a comparison circuit, a multiplexer, and an OR gate; wherein... The comparison circuit is used to compare the corresponding bits of the remaining first count and the remaining second count after removing the least significant bit in the first count and the most significant bit in the second count, and to determine the comparison result of each corresponding bit. The OR gate is used to input the comparison result of the corresponding bit and the value of the highest bit in the second count, and to control the multiplexer to output the value of the current bit.

6. The hammer impact address determination circuit according to claim 5, characterized in that, The comparison circuit includes a first comparator and a second comparator; wherein... The first comparator is used to compare the value of the second most significant bit of the second count with the value of the most significant bit of the first count, and output the comparison result; The second comparator is used to compare the next corresponding bit in the remaining first count and the second count, and determine the comparison result of the corresponding bit.

7. The hammer impact address determination circuit according to claim 6, characterized in that, The first comparator includes a first preset comparison circuit. The input terminal of the first preset comparison circuit is connected to the value of the second most significant bit of the second number of times and the value of the most significant bit of the first number of times. The first result output by the first preset comparison circuit is the comparison result of the first comparator, and the second result output by the first preset comparison circuit is an intermediate result.

8. The hammer impact address determination circuit according to claim 7, characterized in that, The first preset comparison circuit includes a NAND gate, a NOR gate, and two second AND gates; wherein, The NAND gate is used to connect the value of the second most significant bit of the second iteration with the value of the most significant bit of the first iteration; One of the second AND gates is used to input the output signal of the NAND gate and the value of the second most significant bit of the second iteration, and outputs the first result; Another second AND gate is used to access the output signal of the NAND gate and the value of the most significant bit of the first iteration; The NOR gate is used to receive the output signals of the two second AND gates, and the output terminal of the NOR gate outputs the second result.

9. The hammer impact address determination circuit according to claim 8, characterized in that, The first result is used to indicate whether the value of the second most significant bit of the second count is greater than the value of the most significant bit of the first count; The second result is used to indicate whether the value of the second highest bit of the second number is equal to the value of the highest bit of the first number.

10. The hammer impact address determination circuit according to claim 6, characterized in that, The second comparator includes a second preset comparator circuit and two first AND gates; wherein, The second preset comparison circuit is used to input the value of the next corresponding bit in the remaining first count and second count; One of the first AND gates is connected to the third result output by the second preset comparison circuit and the intermediate result after the previous corresponding bit comparison, and outputs the comparison result of the second comparator; Another first AND gate is connected to the fourth result output by the second preset comparison circuit and the intermediate result after the previous corresponding bit comparison, and outputs the intermediate result of the second comparator.

11. The hammer impact address determination circuit according to claim 10, characterized in that, The second preset comparison circuit includes a NAND gate, a NOR gate, and two second AND gates; wherein, The NAND gate is used to access the value of the next corresponding bit; One of the second AND gates is used to input the output signal of the NAND gate and one of the values ​​in the next corresponding bit, and outputs a third result; Another second AND gate is used to access the output signal of the NAND gate and another value in the next corresponding bit; The NOR gate is used to receive the output signals of the two second AND gates, and the output terminal of the NOR gate outputs a fourth result.

12. The hammer impact address determination circuit according to claim 11, characterized in that, The third result is used to indicate whether the value of the bit corresponding to the second number of times in the next corresponding bit is greater than the value of the bit corresponding to the first number of times. The fourth result is used to mark whether the value of the bit corresponding to the second number of times in the next corresponding bit is equal to the value of the bit corresponding to the first number of times.

13. An electronic device, characterized in that, include: Command decoder, used to decode commands received by the array; An address latch is used to latch the row addresses in the array; Hammer strike address determination circuit as described in any one of claims 4-12; The outputs of the command decoder and the address latch are connected to the input of the hammer address determination circuit.

14. The electronic device according to claim 13, characterized in that, It also includes AND gates; among which, The input of the AND gate is connected to the output of the command decoder and the address latch; The output of the AND gate is connected to the address determination module in the hammer address determination circuit.

15. The electronic device according to claim 14, characterized in that, It also includes NOT gates; among which, When the preset value in the hammer address determination circuit is 0, the NOT gate is set between the address latch and the AND gate to invert the row address before counting the second number of times.

Images