An in-memory computing circuit, in-memory write-backable multiplication computing circuit, and chip

Abstract

The present application relates to the technical field of in-memory computing, and particularly relates to an in-memory computing circuit, an in-memory writable multiplication computing circuit and a chip. The in-memory computing circuit comprises a weight layer, a computing layer, a first storage layer and a second storage layer arranged in sequence from top to bottom. The weight layer is used for storing binary weights. The computing layer is used for performing multiplication operation on the binary weights input from outside and the binary weights stored in the weight layer. The first storage layer is used for storing high four-bit operation results. The second storage layer is used for storing low four-bit operation results. When the in-memory computing circuit performs multiplication operation, the multiplication operation on the four-bit weights input by the input signal line IN_B and the four-bit weights stored in the weight layer is split into four-period addition operation, and the operation results are stored in the first storage layer and the second storage layer. The circuit of the present application introduces multiplication from analog domain-based operation to digital domain-based operation, and stores the operation results, thereby avoiding the problems encountered in analog domain multiplication.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, and in particular to an in-memory computing circuit, as well as an in-memory rewritable multiplication computing circuit and chip that uses the in-memory computing circuit as the basic circuit. Background Technology

[0002] The traditional von Neumann architecture separates the processor's computational units from its memory. Data is read from memory during computation and written back after processing. However, in computationally intensive fields such as machine learning and image recognition, including convolutional neural networks, the memory's processing speed is out of sync with the processor's speed. Memory access speed lags significantly behind the processor's computational speed, severely impacting the processor's processing rate.

[0003] Embedding computation in memory offers two significant advantages. First, data input / output to and from memory is greatly reduced because filter weights are not explicitly read; only the computational output is sent out of memory. Second, the massively parallel nature of CNNs allows for simultaneous access to multiple memory addresses. Therefore, this approach enables higher memory bandwidth, overcoming some of the major limitations imposed by the traditional "von Neumann bottleneck."

[0004] Most existing in-memory multiplication operations are performed in the analog domain. In proposed analog IMC (In-Memory Compute) architectures, one operand is typically pre-stored in an SRAM array, while the other operand is modulated into the voltage level of a word line or the number of word line pulses. The multiplication result of the two operands is then represented by the different discharge amounts of the bit cells. When multiple word lines are activated simultaneously, the bit lines discharge through the corresponding bit cells, causing the multiplication result to accumulate on the bit lines. Finally, the analog-to-digital converter (ADC) outputs the accumulated result. This method of implementing multiplication in the analog domain faces challenges related to read interference, computational accuracy, and ADC quantization. Summary of the Invention

[0005] Based on this, it is necessary to provide an in-memory computing circuit, as well as an in-memory write-back multiplication computing circuit and chip that use the in-memory computing circuit as the basic circuit, to address the problems of read interference, calculation accuracy error and ADC quantization accuracy error in in-memory analog domain multiplication calculation.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] An in-memory computing circuit includes, from top to bottom, a weighting layer, a computing layer, a first storage layer, and a second storage layer. The computing layer includes two sets of input terminals A0-A3 and B0-B3, as well as original code output terminals S0-S4 and inverse code output terminals. One set of input terminals B0 to B3 of the computation layer and the four storage nodes QB of the weight layer 20 ~QB 23 A one-to-one correspondence is established, and another set of input terminals A0 to A3 are connected to the four storage nodes Q of the first storage layer. 10 ~Q 13 One-to-one connection. The original code output terminals S1 to S4 of the computation layer are connected to the four storage nodes Q of the first storage layer. 10 ~Q 13 A one-to-one correspondence is established, with the original code output terminal S0 connected to the four storage nodes Q of the second storage layer. 00 ~Q 03 Connected. The inverse code output of the computation layer. With the four storage nodes QB of the first storage layer 10 ~QB 13 One-to-one correspondence connection, inverse code output terminal Each of the four storage nodes QB in the second storage layer 00 ~QB 03 connect.

[0008] The input terminal of the weight layer and the control signal line WL <2> The input terminals B0-B3 of the computation layer are connected to the input signal line IN_B, and the input terminal of the first storage layer is connected to the control signal line WL. <1> Connected, the input terminal of the second storage layer is connected to the control signal line WL <0> Connected.

[0009] When the in-memory computing circuit performs a multiplication operation, it breaks down the multiplication operation of the four-bit weight input by the input signal line IN_B and the four-bit weight stored in the weight layer into a four-cycle addition operation, and stores the result in the first storage layer and the second storage layer.

[0010] Furthermore, the computation layer includes a full adder, four NOR gates, and 20 switching transistors M0 to M10. 19 .

[0011] One input of each of the four NOR gates is connected to the input signal line IN_B. The other input of each of the four NOR gates is connected to one of the four storage nodes QB of the weight layer. 20 ~QB 23 Each of the four NOR gates is connected in a one-to-one correspondence to the four inputs B0 to B3 of the full adder.

[0012] Switching transistor M 16 ~M 19 The drain of the transistor is connected one-to-one with the four input terminals A0 to A3 of the full adder. Switch M 16 ~M 19 The source and the four storage nodes Q of the first storage layer 10 ~Q 13They are connected in a one-to-one correspondence and serve as the input terminals A0 to A3 of the computation layer. Switch M 16 ~M 19 The gate is connected to the control signal line WL_A.

[0013] The output terminals C0 and M of the full adder 15 The source is connected to the output terminal. With M 14 The drains are connected together. The output terminal S3 of the full adder is connected to M. 13 The source is connected to the output terminal. With M 12 The drains are connected together. The output terminal S2 of the full adder is connected to M. 11 The source is connected to the output terminal. With M 10 The drains of the two terminals are connected together. The output terminal S1 of the full adder is connected to the source of M9, and the output terminal... The output terminal S0 of the full adder is connected to the drain of M8. The output terminal S0 of the full adder is connected to the sources of M1, M3, M5, and M7 respectively. Connected to the drains of M0, M2, M4, and M6 respectively. M8~M 15 The gates of M0 and M1 are connected to the control signal line WL_SH; the gates of M2 and M3 are connected to the control signal line WL_SL1; the gates of M4 and M5 are connected to the control signal line WL_SL2; and the gates of M6 and M7 are connected to the control signal line WL_SL3. 15 M 13 M 11 The drains of M9 and M9 serve as the original code output terminals S4 to S1 of the computation layer, respectively. 14 M 12 M 10 The sources of M8 serve as the inverse code outputs of the computation layer. The drains of M7, M5, M3, and M1 serve as the original code output S0 of the computation layer. The sources of M6, M4, M2, and M0 serve as the inverse code output of the computation layer. .

[0014] Furthermore, the weight layer, the first storage layer, and the second storage layer each consist of four storage cells. Each storage cell uses a 6T storage cell containing six transistors.

[0015] Furthermore, the 6T memory cell includes two PMOS transistors P1-P2 and four NMOS transistors N1-N4. P1 and N1 form one inverter structure, P2 and N2 form another inverter structure, and N3 and N4 serve as transmission transistors. The sources of P1 and P2 are both connected to VDD, and the sources of N1 and N2 are both grounded. The drains of P1, N1, P2, and N2 are connected together as memory node Q and connected to the drain of N3. The source of N3 is connected to the bit line BL. The drains of P2, N2, P1, and N1 are connected together as memory node QB and connected to the drain of N4. The gates of N3 and N4 are connected to the word line WL, and the source of N4 is connected to the bit line BLB.

[0016] Furthermore, when performing a write operation, the in-memory computing circuit controls the signal line WL. <2> Four binary weights (w3, w2, w1, w0) are written to the weight layer and controlled via signal line WL. <1> and control signal line WL <0> Write "0" to both the first and second storage layers respectively.

[0017] Furthermore, when the in-memory computing circuit performs a multiplication operation, it inputs the external four-bit binary weights (i3, i2, i1, i0) to the computing layer through the input signal line IN_B, and performs a four-cycle operation with the four-bit binary weights (w3, w2, w1, w0). The four-cycle operation is as follows:

[0018] First cycle. Input signal line IN_B inputs weight i0. This weight is ORed with the four weights (w3, w2, w1, w0) in the weight layer. The result is input to the input terminals B3-B0 of the full adder. Setting control signal line WL_A = 1, the weight 0000 stored in the first storage layer is input to the input terminals A3-A0 of the full adder. The full adder produces a five-bit original code output and a five-bit inverse code output, which are S... 40 ~S 10 S 00 and The calculation process is shown in the following formula:

[0019] [w3, w2, w1, w0]·i0=[w3i0, w2i0, w1i0, w0i0],

[0020] [w3i0,w2i0,w1i0,w0i0]+0000|2=[0,w3i0,w2i0,w1i0,w0i0]

[0021] =[S 40 S 30 S 20 S 10 S 00 ].

[0022] Then, the control signal lines WL_SH = 1 and WL_SL0 = 1 are set, and the high four bits of the full adder output result are stored in the first storage layer, and the low least bit is stored in the low least bit of the second storage layer.

[0023] The second cycle. Input signal line IN_B inputs weight i1. The operation process is the same as the first cycle, except that the first storage layer stores the high four bits of the first cycle's output result S. 40 ~S 10 The inputs are fed to the full adder input terminals A3 to A0, and the calculation process is shown in the following formula:

[0024] [w3i1,w2i1,w1i1,w0i1]+[0,w3i0,w2i0,w1i0]

[0025] =[S 41 S 31 S 21 S 11 S 01 ].

[0026] Then set WL_SH=1 and WL_SL1=1, store the high four bits of the full adder output in the first storage level, and store the low bit in the low bit of the second storage level.

[0027] The third cycle. Input signal line IN_B inputs weight i2. The operation process is the same as the second cycle, the difference being that the first storage layer stores the high four bits of the second cycle's output result S. 41 ~S 11 The inputs are fed to the full adder input terminals A3 to A0, and the calculation process is shown in the following formula:

[0028] [w3i2,w2i2,w1i2,w0i2]+[S 41 S 31 S 21 S 11 ]

[0029] =[S 42 S 32 S 22 S 12 S 02 ].

[0030] Then set WL_SH=1 and WL_SL2=1, store the high four bits of the full adder output in the first storage level, and store the low four bits in the high bits of the second storage level.

[0031] Fourth cycle. Input signal line IN_B inputs weight i3. The operation process is the same as the third cycle, except that the first storage layer stores the high four bits of the third cycle's output result S. 42 ~S 12The inputs are fed to the full adder input terminals A3 to A0, and the calculation process is shown in the following formula:

[0032] [w3i3, w2i3, w1i3, w0i3]+[S 42 S 32 S 22 S 12 ]

[0033] =[S 43 S 33 S 23 S 13 S 03 ].

[0034] Then set WL_SH=1 and WL_SL3=1, store the high four bits of the full adder output in the first storage layer, and store the low least bit in the high most bit of the second storage layer.

[0035] Therefore, the result of the multiplication operation of the four-bit binary weights (i3, i2, i1, i0) and the four-bit binary weights (w3, w2, w1, w0) is the [S] stored in the first storage layer and the second storage layer. 43 S 33 S 23 S 13 S 03 S 02 S 01 S 00 ].

[0036] Furthermore, the switching transistors M0 to M... 19 NOMS tubes are used.

[0037] The present invention also relates to an in-memory write-back multiplication calculation circuit, comprising an in-memory calculation unit array, word lines WL, bit line pairs, input signal lines IN_B, a decoding circuit, a switching circuit, a mode control circuit, a timing circuit, and an output circuit.

[0038] The in-memory computing unit array consists of NM in-memory computing units arranged in an N×M array. Here, N represents the number of rows of in-memory computing units, and M represents the number of columns in the in-memory computing unit array.

[0039] The word line WL is used to control the on and off of the transmission tubes in each memory computing unit in the memory computing unit array during reading and writing.

[0040] Bit line pairs consist of 2M pairs of bit lines BL and BLB. Each in-memory computing unit in each column is connected to the same set of bit lines BL and BLB.

[0041] The input signal line IN_B is used to input four-bit binary weights into the computing layer of the in-memory computing unit array.

[0042] The decoding circuit is used to decode the externally input row address selection signal and control the word line WL according to the decoding result.

[0043] The switching circuit is used to select the four-bit binary weight of the input signal line IN_B to coordinate with the different cycles of the in-memory computing unit array.

[0044] The mode control circuit is used to process the externally input mode selection signal to adjust the different operating modes of the circuit.

[0045] The timing circuitry is used to provide the pulse signals required for reading, writing, and multiplication calculations to the in-memory computing unit array.

[0046] The output circuit is connected to the bit lines BL and BLB of each column of the in-memory computing unit in the storage array through a sensitive amplifier SA, thereby outputting the data or calculation results stored in the in-memory computing unit in any column.

[0047] In particular, the in-memory computing unit adopts the circuit structure of the in-memory computing circuit as described above, and can realize the complete function of the in-memory computing circuit.

[0048] The present invention also relates to an in-memory rewritable multiplication calculation chip, which is packaged from the aforementioned in-memory rewritable multiplication calculation circuit.

[0049] Furthermore, the interface of the in-memory write-back multiplication calculation chip includes at least the following interfaces: power interface VDD, ground interface VSS, row address selection interface A, enable signal interface CEN, external clock signal interface CLKIN, row data interface DATA_IN, read / write control interface WEN, mode selection interface MODE, input signal interface MUL_IN, and output signal interface OUT.

[0050] The system includes the following interfaces: Power Interface VDD for connecting to the power supply; Ground Interface VSS for grounding; Row Address Selection Interface A for inputting a row strobe signal to the circuit, which adjusts the connection status of each in-memory compute unit on each word line; Enable Signal Interface CEN for inputting an enable signal to adjust the circuit's operating state; External Clock Signal Interface CLKIN for inputting an external clock signal to the circuit, which adjusts the different operating modes of the circuit and the clock frequency required by each in-memory compute unit in the in-memory compute unit array; Row Data Interface DATA_IN for inputting pre-stored data to each in-memory compute unit in the in-memory compute unit array; Read / Write Control Interface WEN for inputting control signals to adjust the read / write operations of each in-memory compute unit; Mode Selection Interface MODE for inputting a mode selection signal to the circuit, which adjusts the switching between read / write and multiplication operations of each in-memory compute unit in the in-memory compute unit array to adjust the different operating modes of the circuit; and Input Signal Interface MUL_IN for inputting the external weights to be calculated to each in-memory compute unit. The output signal interface OUT is used to output the data or calculation results stored in each memory computing unit.

[0051] The technical solution provided by this invention has the following beneficial effects:

[0052] The circuit of this invention introduces multiplication from analog-domain to digital-domain operations, avoiding the problems encountered in analog-domain multiplication. The multiplication results can be written back to the in-memory computing unit for processing at appropriate times. Its multi-cycle operation scheme significantly reduces area overhead, and full-array operations can be performed within its array. The digital-domain-based operation method avoids the effects of read interference, computational accuracy errors, and ADC quantization accuracy errors, and the ability to store the computation results makes data processing more flexible. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of an in-memory computing circuit according to Embodiment 1 of the present invention;

[0054] Figure 2 For based on Figure 1 A schematic diagram of the in-memory computing circuit performing multiplication operations;

[0055] Figure 3 For based on Figure 2 A schematic diagram of the in-memory computing circuit performing a calculation in cycle 1;

[0056] Figure 4 For based on Figure 3 A schematic diagram of the in-memory computing circuit with a 1-cycle write-back.

[0057] Figure 5 For based on Figure 4 A schematic diagram of the data storage state during the execution cycle 1 of the in-memory computing circuit;

[0058] Figure 6 For based on Figure 4 A schematic diagram of the in-memory computing circuit performing a calculation in cycle 2;

[0059] Figure 7 For based on Figure 6 A schematic diagram of the in-memory computing circuit with a 2-cycle write-back.

[0060] Figure 8 For based on Figure 7 A schematic diagram of the data storage state during the execution cycle 2 of the in-memory computing circuit;

[0061] Figure 9 For based on Figure 7 A schematic diagram of the in-memory computing circuit performing calculations in cycle 3;

[0062] Figure 10 For based on Figure 9 A schematic diagram of the in-memory computing circuit with a 3-cycle write-back.

[0063] Figure 11 For based on Figure 10 A schematic diagram of the data storage status during the execution cycle 3 of the in-memory computing circuit;

[0064] Figure 12 For based on Figure 10 A schematic diagram of the in-memory computing circuit performing calculations in cycle 4;

[0065] Figure 13 For based on Figure 12 A schematic diagram of the in-memory computing circuit with a 4-cycle write-back.

[0066] Figure 14 For based on Figure 13 A schematic diagram of the data storage status during the 4-cycle execution of the in-memory computing circuit;

[0067] Figure 15 For based on Figure 1 A circuit diagram of a 6T storage unit;

[0068] Figure 16 This is a schematic diagram of an in-memory write-back multiplication calculation circuit according to Embodiment 2 of the present invention;

[0069] Figure 17 This is a waveform diagram illustrating the multiplication operation process performed by the in-memory computing circuit of the present invention. Detailed Implementation

[0070] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0071] Example 1

[0072] Please see Figure 1 This embodiment introduces an in-memory computing circuit, including a weight layer, a computing layer, a first storage layer, and a second storage layer arranged sequentially from top to bottom. The computing layer includes two sets of input terminals A0-A3 and B0-B3, as well as original code output terminals S0-S4 and inverse code output terminals. One set of input terminals B0-B3 of the computation layer is connected to the four storage nodes QB of the weight layer. 20 ~QB 23 A one-to-one correspondence is established, and another set of input terminals A0 to A3 are connected to the four storage nodes Q of the first storage layer. 10 ~Q 13 One-to-one connection. The original code output terminals S1 to S4 of the computation layer are connected to the four storage nodes Q of the first storage layer. 10 ~Q 13 A one-to-one correspondence is established, with the original code output terminal S0 connected to the four storage nodes Q of the second storage layer. 00 ~Q 03 Connected. The inverse code output of the computation layer. With the four storage nodes QB of the first storage layer 10 ~QB 13 One-to-one correspondence connection, inverse code output terminal Each of the four storage nodes QB in the second storage layer 00 ~QB 03 connect.

[0073] The input terminal of the weight layer and the control signal line WL <2> The input terminals B0-B3 of the computation layer are connected to the input signal line IN_B, and the input terminal of the first storage layer is connected to the control signal line WL. <1> Connected, the input terminal of the second storage layer is connected to the control signal line WL <0> Connected.

[0074] When the in-memory computing circuit performs a multiplication operation, it breaks down the multiplication operation of the four-bit weight input by the input signal line IN_B and the four-bit weight stored in the weight layer into a four-cycle addition operation, and stores the result in the first storage layer and the second storage layer.

[0075] Based on the aforementioned in-memory computing circuit, the logic for performing multiplication is as follows: external data is input to the computing layer through four cycles, and then multiplied by the four weights of the weight layer through NOR gates. The result is accumulated by a full adder. The accumulated sum can be written back to the first and second storage layers. The weight layer, the first storage layer, and the second storage layer each consist of four storage units. The computing layer includes a full adder, four NOR gates, and 20 switching transistors M0 to M10. 19 .

[0076] Based on this, the circuit in this embodiment operates in two modes: SRAM read / write mode and multiplication mode. The detailed calculation process is as follows:

[0077] 1. Initialization: The system first operates in SRAM mode. In this mode, the four-bit binary weights (w3, w2, w1, w0) to be calculated are written to the weight layer. Since the result of the calculation needs to be stored in the memory layer, all bits in the memory layer also need to be cleared to zero, i.e., all bits are written as 0.

[0078] 2. Multiplication Mode Enabled: At this time, the system switches from SRAM mode to CIM (multiplication) mode. In CIM mode, the timing circuit automatically generates four cycles of pulses for multiplication calculation. During these four cycles, external input data (i3, i2, i1, i0) will be processed, and data will be written back in the corresponding cycles.

[0079] 3. Multiplication operations: Please refer to [link / reference]. Figure 2 , Figure 2 The diagram illustrates the circuit diagram of the in-memory computation unit performing multiplication. This CIM macro implements the product of 4-bit weights and an external 4-bit input. The four weights (w3, w2, w1, w0) are multiplied (i.e., ANDed) with the external weight IN_B, and the output four-bit result is sent to one end of the full adder. The other four bits of the full adder are provided by the high four bits of the first memory layer. Therefore, the high four bits serve two purposes: storing the high 4-bit value generated by the calculation and transmitting this 4-bit value to the full adder. Specifically, it is divided into the following four cycles:

[0080] a. Period 1:

[0081] Calculation: such as Figure 3As shown, in this cycle, the external input i0, i.e., IN_B = i0, is processed. This data is ORed with the four weights (w3, w2, w1, w0) in the weight layer, and the result is the product of (w3, w3, w3, w3) and i0, i.e., (w3, w2, w1, w0)·i0. This result is input to the input terminals B3~B0 of the full adder. Then, the control signal WL_A = 1 is set. Since the high four bits of the first storage layer are initialized to 0000, 0000 is sent to the input terminals A3~A0 of the full adder. The full adder produces a five-bit original code output and a five-bit inverse code output, which are S 40 ~S 10 S 00 and The calculation process is shown in the following formula:

[0082] [w3, w2, w1, w0]·i0=[w3i0, w2i0, w1i0, w0i0]

[0083] [w3i0,w2i0,w1i0,w0i0]+0000|2=[0,w3i0,w2i0,w1i0,w0i0]

[0084] =[S 40 S 30 S 20 S 10 S 00 ]

[0085] Save back: such as Figure 4 As shown, the output of the full adder acts as a local word line. The write-back operation is similar to a write operation on the 6T unit. The local word line is enabled, i.e., WL_SH = 1 and WL_SL0 = 1. At this time, the high four bits and the least significant bit of the full adder output are stored in the first and second storage layers, respectively. This least significant bit is also the least significant bit (LSB) of the result [w3, w2, w1, w0] × [i3, i2, i1, i0]. The data storage state during write-back is as follows: Figure 5 As shown.

[0086] b. Period 2:

[0087] Calculation: such as Figure 6 As shown, the external input data for this cycle is IN_B = i1. The entire process is similar to cycle 1. It is worth noting that since the high four bits of the first storage layer are the high four bits of the data generated by the full adder in cycle 1, i.e., S 40 ~S 10 This result is then fed into the input terminals A3 to A0 of the full adder. When the control signal WL_A = 1, the calculation process of the full adder is expressed by the following formula:

[0088] [w3i1,w2i1,w1i1,w0i1]+[0,w3i0,w2i0,w1i0]

[0089] =[S 41 S 31 S 21 S 11 S 01 ]

[0090] In other words, the value stored in the high four bits (6T cells) of the first storage layer is used as an intermediate result and is reused in the calculation of the next cycle.

[0091] Save back: such as Figure 7 As shown, the local word line is also opened, but unlike cycle 1, the least significant bit is stored using WL_SL1, i.e., WL_SH = 1, WL_SL1 = 1. At this time, the high four bits and the least significant bit of the full adder output are stored in the first and second storage layers respectively. This least significant bit is the second least significant bit of the result [w3, w2, w1, w0]·[i3, i2, i1, i0], i.e., LSB+1. The data storage state during write-back is as follows... Figure 8 As shown

[0092] c. Period 3:

[0093] Calculation: such as Figure 9 As shown, the external input data for this cycle is IN_B = i2. The entire process is similar to cycles 1 and 2. At this time, the high four bits of the first storage layer are the high four bits of the data generated by the full adder in cycle 2, i.e., S. 41 ~S 11 This result is then fed into the input terminals A3 to A0 of the full adder. When the control signal WL_A = 1, the calculation process of the full adder is expressed by the following formula:

[0094] [w3i2,w2i2,w1i2,w0i2]+[S 41 S 31 S 21 S 11 ]

[0095] =[S 42 S 32 S 22 S 12 S 02 ]

[0096] Save back: such as Figure 10As shown, when the local word lines are enabled (WL_SH = 1, WL_SL2 = 1), the high four bits and the least significant bit of the full adder output are stored in the first and second storage layers, respectively. The least significant bit is the LSB+2 of the result of [w3, w2, w1, w0]·[i3, i2, i1, i0]. The data storage state during write-back is as follows... Figure 11 As shown.

[0097] d. Period 4:

[0098] Calculation: such as Figure 12 As shown, the external input data for this cycle is IN_B = i3. At this time, the high four bits of the first storage layer are the high four bits of the data generated by the full adder in cycle 3, i.e., S. 42 ~S 12 This result is then fed into the input terminals A3 to A0 of the full adder. When the control signal WL_A = 1, the calculation process of the full adder is expressed by the following formula:

[0099] [w3i3, w2i3, w1i3, w0i3]+[S 42 S 32 S 22 S 12 ]

[0100] =[S 43 S 33 S 23 S 13 S 03 ]

[0101] Save back: such as Figure 13 As shown, when the local word lines are enabled (WL_SH = 1, WL_SL3 = 1), the high four bits and the least significant bit of the full adder output are stored in the first and second storage layers, respectively. The least significant bit is the LSB+3 of the result of [w3, w2, w1, w0]·[i3, i2, i1, i0]. The data storage state during write-back is as follows... Figure 14 As shown

[0102] Through the above four cycles, the eight-bit storage value in the first and second storage layers is [S]. 43 S 33 S 23 S 13 S 03 S 02 S 01 S 00 This 8-bit data represents the result of multiplying the internal weights [w3, w2, w1, w0] with the external weights [i3, i2, i1, i0].

[0103] The storage cells in the weighting layer, first storage layer, and second storage layer mentioned in this embodiment can include 6T storage cells with 6 transistors, or conventional storage cells with different numbers of transistors such as 6T, 8T, 10T, 12T, etc., but are not limited to the mentioned storage cells, as long as they can achieve the same function of the aforementioned storage cells in the circuit. Furthermore, the internal circuit connections are not limited to any particular form.

[0104] To clearly illustrate the circuit of this embodiment, a specific circuit structure is provided for the weight layer, computation layer, first storage layer, and second storage layer, as follows:

[0105] The weight layer, the first storage layer, and the second storage layer all use 6TB storage units. Please refer to [link / reference]. Figure 15 The 6T memory cell includes two PMOS transistors P1-P2 and four NMOS transistors N1-N4. P1 and N1 form one inverter structure, P2 and N2 form another inverter structure, and N3 and N4 serve as transmission transistors. The sources of P1 and P2 are both connected to VDD, and the sources of N1 and N2 are both grounded. The drains of P1, N1, P2, and N2 are connected together as memory node Q and connected to the drain of N3. The source of N3 is connected to the bit line BL. The drains of P2, N2, P1, and N1 are connected together as memory node QB and connected to the drain of N4. The gates of N3 and N4 are connected to the word line WL, and the source of N4 is connected to the bit line BLB.

[0106] For the computation layer, using switching transistors M0 to M... 19 Taking NOMS transistors as an example, the specific connection method is as follows: one input terminal of the four NOR gates is connected to the input signal line IN_B. The other input terminal of the four NOR gates is connected to the four storage nodes QB of the weight layer. 20 ~QB 23 Each of the four NOR gates is connected in a one-to-one correspondence to the four inputs B0 to B3 of the full adder.

[0107] Switching transistor M 16 ~M 19 The drain of the transistor is connected one-to-one with the four input terminals A0 to A3 of the full adder. Switch M 16 ~M 19 The source and the four storage nodes Q of the first storage layer 10 ~Q 13 They are connected in a one-to-one correspondence and serve as the input terminals A0 to A3 of the computation layer. Switch M 16 ~M 19 The gate is connected to the control signal line WL_A.

[0108] The output terminals C0 and M of the full adder 15 The source is connected to the output terminal. With M 14 The drains are connected together. The output terminal S3 of the full adder is connected to M. 13 The source is connected to the output terminal. With M 12 The drains are connected together. The output terminal S2 of the full adder is connected to M. 11 The source is connected to the output terminal. With M 10 The drains of the two terminals are connected together. The output terminal S1 of the full adder is connected to the source of M9, and the output terminal... The output terminal S0 of the full adder is connected to the drain of M8. The output terminal S0 of the full adder is connected to the sources of M1, M3, M5, and M7 respectively. Connected to the drains of M0, M2, M4, and M6 respectively. M8~M 15 The gates of M0 and M1 are connected to the control signal line WL_SH; the gates of M2 and M3 are connected to the control signal line WL_SL1; the gates of M4 and M5 are connected to the control signal line WL_SL2; and the gates of M6 and M7 are connected to the control signal line WL_SL3. 15 M 13 M 11 The drains of M9 and M9 serve as the original code output terminals S4 to S1 of the computation layer, respectively. 14 M 12 M 10 The sources of M8 serve as the inverse code outputs of the computation layer. The drains of M7, M5, M3, and M1 serve as the original code output S0 of the computation layer. The sources of M6, M4, M2, and M0 serve as the inverse code output of the computation layer. .

[0109] The circuit described in this embodiment implements 4-bit multiplication in-memory computation. This circuit introduces multiplication from analog-domain operations to digital-domain operations, avoiding the challenges encountered in analog-domain multiplication, such as read interference, computational accuracy, and ADC quantization. The multiplication results can be written back to the in-memory compute unit (IMCU) for processing at appropriate times. Its multi-cycle operation scheme significantly reduces area overhead.

[0110] Example 2

[0111] Please see Figure 16This embodiment introduces an in-memory write-back multiplication calculation circuit, including an in-memory calculation unit array, word lines WL, bit line pairs, input signal lines IN_B, decoding circuit (precharge control / decoding / word line drive circuit), switching circuit (external weight data drive circuit), mode control circuit (mode control drive circuit), timing circuit, and output circuit (sensitive amplifier and output circuit).

[0112] The in-memory computing unit array consists of NM in-memory computing units arranged in an N×M array. Here, N represents the number of rows of in-memory computing units, and M represents the number of columns in the in-memory computing unit array.

[0113] The word line WL is used to control the on and off of the transmission tubes in each memory computing unit in the memory computing unit array during reading and writing.

[0114] Bit line pairs consist of 2M pairs of bit lines BL and BLB. Each in-memory computing unit in each column is connected to the same set of bit lines BL and BLB.

[0115] The input signal line IN_B is used to input four-bit binary weights into the computing layer of the in-memory computing unit array.

[0116] The decoding circuit is used to decode the externally input row address selection signal and control the word line WL according to the decoding result.

[0117] The switching circuit is used to select the four-bit binary weight of the input signal line IN_B to coordinate with the different cycles of the in-memory computing unit array.

[0118] The mode control circuit is used to process the externally input mode selection signal to adjust the different operating modes of the circuit.

[0119] The timing circuitry is used to provide the pulse signals required for reading, writing, and multiplication calculations to the in-memory computing unit array.

[0120] The output circuit is connected to the bit lines BL and BLB of each column of the in-memory computing unit in the storage array through a sensitive amplifier SA, thereby outputting the data or calculation results stored in the in-memory computing unit in any column.

[0121] In particular, the in-memory computing unit adopts the circuit structure of the in-memory computing circuit as described above, and can realize the complete function of the in-memory computing circuit.

[0122] The difference between this embodiment and Embodiment 1 is that this embodiment uses an array to form a large-scale in-memory arithmetic circuit array, which, in conjunction with other circuits, constitutes a complete in-memory write-back multiplication circuit. Therefore, this embodiment can realize the storage and multiplication operations in Embodiment 1.

[0123] according to Figure 16 The solution of this embodiment will be described in detail: In Figure 16 In the original design, the 6TB storage units were arranged in a 64x64 pattern. Considering that the in-memory computing unit in this embodiment contains 12 6TB storage units arranged in a 3x4 pattern, the final designed in-memory computing unit array has a 21x16 distribution. To achieve the 64x64 distribution, since each in-memory computing unit contains only 3 rows of 6TB storage units, the actual in-memory computing unit array only has 63 rows of 6TB storage units based on the distribution of the in-memory computing units. Therefore, there is one additional row consisting only of 6TB storage units. The final row and column distribution is a 21x16 in-memory computing unit array plus one row of 6TB storage units.

[0124] Furthermore, 6T memory cells in the same row are connected to the same word line (signal control line), and compute layers in the same row are connected to the same signal input line; for 6T memory cells in the same column, the left and right sides are connected to bit lines BLB and BL respectively.

[0125] For example, the in-memory computing unit in the first row contains three rows of 6T storage units, and the word lines WL for all 6T storage units in the bottom row are... <0> All 6TB storage units in the middle row are connected to WL <1> All 6TB storage units at the top are connected to WL <2> For the in-memory computing unit in the first column, which contains four columns of 6T memory cells, all 6T memory cells in the rightmost column are connected to the bit line BLB. <0> and BL <0> All 6T memory cells in the second column from the right are connected to the BLB line. <1> and BL <1> All 6T memory cells in the third column from the right are connected to the BLB line. <2> and BL <2> All 6T memory cells in the fourth column from the right are connected to the BLB line. <3> and BL <3> .

[0126] Based on the above circuit structure, the implementation of the storage function remains the same as the original SRAM storage cell, that is, the storage cell is located through word lines and bit lines, and the data in the storage node corresponding to the storage cell is obtained.

[0127] It should be noted that the 6T-SRAM storage cells and the 64×64 in-memory computing unit array distribution are examples listed in this embodiment to illustrate the solution, and are not intended to limit the scope of this case. In other embodiments, based on the same technical concept, other types of storage cells can be used to form other arrays of a larger scale to obtain the required "computing unit array".

[0128] This embodiment not only has the same effect as Embodiment 1, but also allows for full array operations in the array constructed based on Embodiment 1.

[0129] Example 3

[0130] This embodiment introduces an in-memory write-back multiplication calculation chip, which is packaged from the aforementioned in-memory write-back multiplication calculation circuit. The in-memory write-back multiplication calculation chip's interfaces include at least a power interface VDD, a ground interface VSS, a row address selection interface, an enable signal interface CEN, an external clock signal interface CLKIN, a row data interface DATA_IN, a read / write control interface WEN, a mode selection interface MODE, an input signal interface MUL_IN, and an output signal interface OUT.

[0131] The power interface VDD is used to connect to the power supply. The ground interface VSS is used for grounding. The row address selection interface A is used to input a row strobe signal to the circuit, which is used to adjust the access status of each in-memory computing unit on each word line. The enable signal interface CEN is used to input an enable signal to adjust the circuit's operating state. The external clock signal interface CLKIN is used to input an external clock signal to the circuit, which is used to adjust the different operating modes of the circuit and the clock frequency required by each in-memory computing unit in the in-memory computing unit array. The row data interface DATA_IN is used to input pre-stored data to each in-memory computing unit in the in-memory computing unit array. The read / write control interface WEN is used to input control signals to adjust the read / write operations of each in-memory computing unit. The mode selection interface MODE is used to input a mode selection signal to the circuit, which is used to adjust the switching between read / write operations and multiplication operations of each in-memory computing unit in the in-memory computing unit array to adjust the different operating modes of the circuit. The input signal interface MUL_IN is used to input the external weights to be calculated to each in-memory computing unit. The output signal interface OUT is used to output the data or calculation results stored in each memory computing unit.

[0132] This implementation, by packaging it into a chip, makes it easier to promote and apply the in-memory rewritable multiplication calculation circuit.

[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An in-memory computing circuit, characterized in that, The in-memory computing circuit includes a weighting layer, a computing layer, a first storage layer, and a second storage layer arranged sequentially from top to bottom; the computing layer includes two sets of input terminals A0~A3 and B0~B3, as well as original code output terminals S0~S4 and inverse code output terminals. ~ One set of input terminals B0~B3 of the computation layer is connected to the four storage nodes QB of the weight layer. 20 ~ QB 23 A one-to-one correspondence is established, and another set of input terminals A0~A3 are connected to the four storage nodes Q of the first storage layer. 10 ~ Q 13 One-to-one correspondence connection; the original code output terminals S1~S4 of the computation layer are connected to the four storage nodes Q of the first storage layer. 10 ~Q 13 A one-to-one correspondence is established, with the original code output terminal S0 connected to the four storage nodes Q of the second storage layer. 00 ~Q 03 Connected; the inverse code output terminal of the computation layer ~ With the four storage nodes QB of the first storage layer 10 ~QB 13 One-to-one correspondence connection, inverse code output terminal Each of the four storage nodes QB in the second storage layer 00 ~QB 03 connect; The input terminal of the weight layer and the control signal line WL <2> The input terminals B0~B3 of the computing layer are connected to the input signal line IN_B, and the input terminal of the first storage layer is connected to the control signal line WL. <1> Connected, the input terminal of the second storage layer is connected to the control signal line WL <0> Connected; When the in-memory computing circuit performs a multiplication operation, it breaks down the multiplication operation of the four-bit weight input by the input signal line IN_B and the four-bit weight stored in the weight layer into a four-cycle addition operation, and stores the operation result in the first storage layer and the second storage layer.

2. The in-memory computing circuit according to claim 1, characterized in that, The computation layer includes a full adder, four NOR gates, and 20 switching transistors M0~M1. 19 ; One input of each of the four NOR gates is connected to the input signal line IN_B; the other input of each of the four NOR gates is connected to one of the four storage nodes QB of the weight layer. 20 ~QB 23 Each of the four NOR gates is connected in a one-to-one correspondence to the four input terminals B0~B3 of the full adder; Switching transistor M 16 ~M 19 The drain of the transistor is connected one-to-one with the four input terminals A0~A3 of the full adder; the switching transistor M 16 ~M 19 The source and the four storage nodes Q of the first storage layer 10 ~Q 13 They are connected in a one-to-one correspondence and serve as the input terminals A0~A3 of the computing layer; the switching transistor M 16 ~M 19 The gate is connected to the control signal line WL_A; The output terminals C0 and M of the full adder 15 The source is connected to the output terminal. With M 14 The drains of the two electrodes are connected; the output terminal S3 of the full adder is connected to M. 13 The source is connected to the output terminal. With M 12 The drains of the two electrodes are connected; the output terminal S2 of the full adder is connected to M. 11 The source is connected to the output terminal. With M 10 The drains of the two electrodes are connected together; the output terminal S1 of the full adder is connected to the source of M9, and the output terminal... The output terminal S0 of the full adder is connected to the drain of M8; the output terminal S0 of the full adder is connected to the source of M1, M3, M5, and M7 respectively. Connected to the drains of M0, M2, M4, and M6 respectively; M8~M 15 The gates of M0 and M1 are connected to the control signal line WL_SH; the gates of M2 and M3 are connected to the control signal line WL_SL1; the gates of M4 and M5 are connected to the control signal line WL_SL2; and the gates of M6 and M7 are connected to the control signal line WL_SL3. 15 M 13 M 11 The drains of M9 and M9 serve as the original code output terminals S4~S1 of the computation layer, respectively; M 14 M 12 M 10 The sources of M8 serve as the inverse code outputs of the computation layer. ~ The drains of M7, M5, M3, and M1 serve as the original code output S0 of the computation layer; the sources of M6, M4, M2, and M0 serve as the inverse code output of the computation layer. .

3. The in-memory computing circuit according to claim 1, characterized in that, The weight layer, the first storage layer, and the second storage layer are each composed of four storage cells; the storage cells are 6T storage cells containing 6 transistors.

4. The in-memory computing circuit according to claim 3, characterized in that, The 6T memory cell includes two PMOS transistors P1~P2 and four NMOS transistors N1~N4. P1 and N1 form an inverter structure, P2 and N2 form another inverter structure, and N3 and N4 serve as transmission transistors. The sources of P1 and P2 are both connected to VDD, and the sources of N1 and N2 are both grounded. The drains of P1, N1, P2, and N2 are connected together as a memory node Q and connected to the drain of N3. The source of N3 is connected to the bit line BL. The drains of P2, N2, P1, and N1 are connected together as a memory node QB and connected to the drain of N4. The gates of N3 and N4 are connected to the word line WL, and the source of N4 is connected to the bit line BLB.

5. The in-memory computing circuit according to claim 2, characterized in that, When the in-memory computing circuit performs a write operation, it controls the signal line WL. <2> Four-bit binary weight Write to the weight layer and via the control signal line WL <1> and control signal line WL <0> Write "0" to both the first and second storage layers respectively.

6. The in-memory computing circuit according to claim 5, characterized in that, When the in-memory computing circuit performs a multiplication operation, it transmits the external four-bit binary weights through the input signal line IN_B. The input is given to the computation layer and combined with four-bit binary weights. Perform a four-cycle operation, the four-cycle operation method is as follows: First cycle; Input signal line IN_B input weights This weight is related to the four weights in the weight layer. Perform a NOR operation, and input the result to the input terminals B3~B0 of the full adder; set the control signal lines... The weights 0000 stored in the first storage layer are input to the full adder's input terminals A3~A0. The full adder produces a five-bit original code output and a five-bit inverse code output, which are respectively... , and , The calculation process is shown in the following formula: ， ； Then command the control signal line , The high four bits of the full adder output are stored in the first storage layer, and the low four bits are stored in the low four bits of the second storage layer. Second cycle; Input signal line IN_B input weights The operation process is the same as the first cycle, except that the first storage layer will store the high four bits of the first cycle's output result. The inputs are fed to the full adder input terminals A3~A0, and the calculation process is shown in the following formula: ； Immediately ordered , The high four bits of the full adder output are stored in the first storage layer, and the low four bits are stored in the low two storage layers. Third cycle; Input signal line IN_B input weights The operation process is the same as the second cycle, except that the first storage layer will store the high four bits of the second cycle's output result. The inputs are fed to the full adder input terminals A3~A0, and the calculation process is shown in the following formula: ； Immediately ordered , The high four bits of the full adder output are stored in the first storage layer, and the low four bits are stored in the high bits of the second storage layer. Fourth cycle; Input signal line IN_B input weights The operation process is the same as the third cycle, except that the first storage layer outputs the high four bits of the stored third cycle result. The inputs are fed to the full adder input terminals A3~A0, and the calculation process is shown in the following formula: ； Immediately ordered , The high four bits of the full adder output are stored in the first storage layer, and the low least bit is stored in the high most bit of the second storage layer. Furthermore, the four-bit binary weight and four-bit binary weight The result of the multiplication operation is stored in the first storage layer and the second storage layer. .

7. The in-memory computing circuit according to claim 2, characterized in that, The switching transistors M0~M 19 NOMS tubes are used.

8. A memory-writable multiplication calculation circuit, characterized in that, It includes: An in-memory computing unit array consists of NM in-memory computing units arranged in an N×M array; where N represents the number of rows of in-memory computing units and M represents the number of columns of the in-memory computing unit array. The word line WL is used to control the on and off of the transmission transistors in each memory computing unit in the memory computing unit array during reading and writing. Bit line pairs, which include 2M pairs of bit lines BL and BLB; each in-memory computing unit in each column is connected to the same set of bit lines BL and BLB; The input signal line IN_B is used to input four-bit binary weights into the computing layer in the in-memory computing unit array. The decoding circuit is used to decode the externally input row address selection signal and control the word line WL according to the decoding result; A switching circuit is used to select the four-bit binary weight of the input signal line IN_B to coordinate with the different cycles of the in-memory computing unit array. The mode control circuit is used to process the externally input mode selection signal to adjust the different operating modes of the circuit. A timing circuit is used to provide pulse signals required for read, write, and multiplication calculations to the in-memory computing unit array; The output circuit is connected to the bit lines BL and BLB of each column of the in-memory computing unit in the in-memory computing unit storage array through a sensitive amplifier SA, thereby outputting the data or calculation results stored in the in-memory computing unit in any column. The in-memory computing unit adopts the circuit structure of the in-memory computing circuit as described in any one of claims 1-7, and can realize the complete function of the in-memory computing circuit.

9. A memory-writable multiplication calculation chip, characterized in that, It is packaged from the in-memory rewritable multiplication calculation circuit described in claim 8.

10. The in-memory write-back multiplication calculation chip according to claim 9, characterized in that, The interface of the in-memory write-back multiplication chip includes at least: The power interface VDD is used to connect to the power supply. The grounding interface VSS is used for grounding. Row address selection interface A is used to input row strobe signals to the circuit, and the row strobe signals are used to adjust the access status of each in-memory computing unit on each word line; The enable signal interface CEN is used to input an enable signal to adjust the operating state of the circuit. The external clock signal interface CLKIN is used to input an external clock signal into the circuit. The clock signal is used to adjust the different operating modes of the circuit and the clock frequency required by each in-memory computing unit in the in-memory computing unit array. The row data interface DATA_IN is used to input a pre-stored data into each in-memory computing unit of the in-memory computing unit array. The read / write control interface WEN is used to input control signals that adjust the read / write operations of each memory computing unit. The mode selection interface MODE is used to input a mode selection signal to the circuit. The mode selection signal is used to adjust the switching between read / write operations and multiplication operations of each in-memory computing unit in the in-memory computing unit array, so as to adjust the different working modes of the circuit. The input signal interface MUL_IN is used to input the external weights to be calculated into each in-memory computing unit. The output signal interface OUT is used to output the data or calculation results stored in each memory computing unit.

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