A measurement method, system and terminal for improving wafer pattern overlay accuracy

Abstract

The present application discloses a measurement method, system and terminal for improving the overlay accuracy of wafer patterns. The method includes: defining a chip including multiple photoresists; performing atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain a reference line width; performing CD-SEM measurement on another wafer coated with photoresist, and adjusting the measurement parameters so that the actual line width of any photoresist is 1-3nm smaller than the reference line width; recording the measurement parameters that match any photoresist; summarizing the measurement parameters matched by each photoresist in the chip to construct a measurement parameter database; and performing photoresist pattern measurement based on the measurement parameter database. The system includes: a definition module, a reference line width acquisition module, a shrinkage size limitation module, a measurement parameter recording module, a measurement parameter database construction module and a photoresist pattern measurement module. Through the present application, the error caused by CD-SEM measurement between adjacent layers of photoresist can be eliminated, thereby greatly improving the overlay accuracy.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit manufacturing technology, and in particular to a measurement method, system, and terminal for improving wafer pattern overlay accuracy. Background Art

[0002] Wafer pattern overlay accuracy (OVL) refers to the accuracy of the overlapping position of the current layer pattern and the previous layer pattern in the photolithography manufacturing process. In the field of integrated circuit manufacturing technology, taking chip manufacturing as an example, in the initial stage of chip manufacturing, it is necessary to establish an accurate photolithography process model through OPC (Optical Proximity Correction). The establishment of the OPC model usually includes the following stages: design, experiment, data measurement, model calibration and verification. Data measurement, that is, data collection, is the basis for the establishment of the entire photolithography process model. Different types of photoresists are usually used in different structural layers in the chip. How to adjust the measurement method to ensure the accuracy of wafer pattern overlay is an important technical issue.

[0003] Existing measurement methods typically use a linewidth-scanning electron microscope to collect data from exposed photoresist patterns. However, due to the decomposition of internal protective groups in the photoresist under the irradiation of the photon beam, the photoresist inevitably shrinks, resulting in errors in the photoresist pattern measurement. Because different types of photoresists are typically used in different structural layers of a chip, they shrink to varying degrees under the bombardment of the high-energy electron beam. This increases overlay errors during stacking, affecting lithography accuracy and making it impossible to establish a correct OPC model. Consequently, existing measurement methods result in poor wafer pattern overlay accuracy, which in turn affects the establishment of the OPC model. Summary of the Invention

[0004] The present application provides a measurement method, system and terminal for improving wafer pattern overlay accuracy, so as to solve the problem that the measurement method in the prior art results in low wafer pattern overlay accuracy.

[0005] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0006] A measurement method for improving wafer pattern overlay accuracy, the method comprising:

[0007] The definition chip includes multiple photoresists;

[0008] Performing atomic layer deposition and CD-SEM (Critical Dimension-scanning electron microscope) measurement on a wafer coated with any photoresist to obtain a reference line width of any photoresist;

[0009] Performing CD-SEM measurement on another wafer coated with any of the photoresists, adjusting measurement parameters so that the actual line width of any of the photoresists shrinks by 1-3 nm compared to the reference line width, the measurement parameters including: acceleration voltage and electron beam density;

[0010] Recording measurement parameters matching any one of the photoresists;

[0011] Summarizing the measurement parameters matched by each photoresist in the chip and constructing a measurement parameter database;

[0012] Photoresist pattern measurement is performed according to the measurement parameter database.

[0013] Optionally, the shrinkage size is 2.5 nm.

[0014] Optionally, performing atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain a reference line width of any photoresist includes:

[0015] Pre-treating the wafer coated with any one of the photoresists;

[0016] Performing atomic layer deposition on the pre-treated wafer to obtain a wafer with a surface layer deposited, wherein the metal layer used for the atomic layer deposition includes: ZnO or Al2O3;

[0017] The distance between the inner walls of the metal layer in the wafer on which the surface layer is deposited is measured using CD-SEM to obtain a reference line width of any photoresist.

[0018] Optionally, a method for pre-treating a wafer coated with any of the photoresists comprises:

[0019] forming a SOC (Spin-On-Carbon) layer, a SOG (Spin On Glass) layer, and any photoresist layer on the wafer in order from bottom to top, wherein the any photoresist layer is spin-coated on the SOG layer;

[0020] The wafer coated with any of the photoresists is sequentially subjected to exposure, development and post-baking treatments to obtain a pre-treated wafer.

[0021] Optionally, a method of performing atomic layer deposition on a pre-treated wafer to obtain a wafer with a surface layer deposited thereon includes:

[0022] The pre-treated wafer was placed in an ALD (Atomic Layer Deposition) device for atomic layer deposition. The process conditions for atomic layer deposition were as follows: deposition temperature was 80°C, deposition rate was The deposition thickness is 5-10 nm, and the deposition time is 75 minutes to 150 minutes.

[0023] Optionally, a method of performing CD-SEM measurement on another wafer coated with any of the photoresists, and adjusting measurement parameters so that the actual line width of any of the photoresists shrinks by 1-3 nm compared to the reference line width, comprises:

[0024] Pre-treating another wafer coated with any one of the photoresists;

[0025] The other wafer after pretreatment is measured by CD-SEM, and measurement parameters are adjusted so that the actual line width of any photoresist is reduced by 1-3 nm compared with the reference line width.

[0026] A measurement system for improving wafer pattern overlay accuracy, the system comprising:

[0027] A definition module, used to define the chip including multiple photoresists;

[0028] A reference line width acquisition module is used to perform atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain a reference line width of the photoresist;

[0029] A shrinkage dimension limiting module is used to perform CD-SEM measurement on another wafer coated with any of the photoresists, and adjust measurement parameters so that the shrinkage dimension of the actual line width of any of the photoresists is 1-3 nm compared to the reference line width, wherein the measurement parameters include: acceleration voltage and electron beam density;

[0030] A measurement parameter recording module, configured to record measurement parameters matching any one of the photoresists;

[0031] A measurement parameter database construction module, used to summarize the measurement parameters matched by each photoresist in the chip and construct a measurement parameter database;

[0032] The photoresist pattern measurement module is used to measure the photoresist pattern according to the measurement parameter database.

[0033] Optionally, the reference line width acquisition module includes:

[0034] A first pre-processing unit, configured to pre-process the wafer coated with any one of the photoresists;

[0035] ALD equipment is used to perform atomic layer deposition on the pre-treated wafer to obtain a wafer with a surface layer deposited, wherein the metal layer used for atomic layer deposition includes: ZnO or Al2O3;

[0036] The reference line width measurement unit is used to measure the distance between the inner walls of the metal layer in the wafer on which the surface layer is deposited using a CD-SEM to obtain the reference line width of any photoresist.

[0037] Optionally, the shrinkage size limiting module includes:

[0038] a second pre-processing unit, configured to pre-process another wafer coated with any one of the photoresists;

[0039] The actual line width measurement unit is used to measure the other wafer after pretreatment by using CD-SEM, and adjust the measurement parameters so that the actual line width of any photoresist is shrunk by 1-3 nm compared with the reference line width.

[0040] A terminal comprises: a processor and a memory communicatively connected to the processor, wherein:

[0041] The memory stores instructions that can be executed by the processor, and the instructions are executed by the processor so that the processor can execute any one of the measurement methods for improving wafer pattern overlay accuracy as described above.

[0042] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0043] The present application provides a measurement method for improving wafer pattern overlay accuracy. The method defines that a chip includes multiple photoresists, and by recording and summarizing the measurement parameters matched by each photoresist in the chip, a measurement parameter database is constructed, and finally the photoresist pattern is measured based on the measurement parameter database. When recording the measurement parameters matched with any photoresist, the method adopted is: for any photoresist, its reference line width is obtained respectively, and when the size of the photoresist after shrinkage is measured using CD-SEM, the shrinkage size is controlled to 1-3nm by adjusting the measurement parameters, thereby recording the measurement parameters matched by the photoresist. When obtaining the measurement parameters, the shrinkage of all layers of photoresist in the chip is controlled to 1-3nm. This method can ensure that the errors caused by CD-SEM measurement of the upper and lower layers of photoresist are consistent and are controlled within 1-3nm, thereby eliminating the errors caused by CD-SEM measurement between adjacent layers of photoresist, thereby greatly improving overlay accuracy.

[0044] In this embodiment, when performing CD-SEM measurement on another wafer coated with any photoresist, the measurement parameters can be adjusted so that the actual line width of any photoresist is 2.5nm smaller than the reference line width. This preferred shrinkage size can further limit the shrinkage size of different photoresists, thereby further reducing the overlay error caused by the different shrinkage sizes due to the different actual sizes of the photoresists obtained by CD-SEM measurement, thereby improving the overlay accuracy.

[0045] This embodiment also provides a measurement system for improving wafer pattern overlay accuracy. The system mainly includes: a definition module, a reference linewidth acquisition module, a shrinkage dimension limitation module, a measurement parameter recording module, a measurement parameter database construction module, and a photoresist pattern measurement module. By setting the reference linewidth acquisition module and the shrinkage dimension limitation module, the reference linewidth of any photoresist can be obtained. When the actual linewidth of any photoresist is measured using a CD-SEM, the shrinkage dimension is controlled to be between 1 and 3 nm by adjusting the measurement parameters. The measurement parameters are recorded by the measurement parameter recording module. Then, the measurement parameters matched by all photoresists in the chip are summarized by the measurement parameter database construction module to construct a measurement parameter database. Finally, the photoresist pattern measurement module is used to perform photoresist pattern measurement. This system structure design ensures that the errors caused by CD-SEM measurement of the upper and lower photoresists are consistent by controlling the actual linewidth shrinkage dimensions of all photoresists in the current chip within the same error range. This can eliminate the errors caused by CD-SEM measurement between adjacent photoresists, thereby greatly improving overlay accuracy. In this embodiment, the actual linewidth shrinkage of the photoresist is controlled within a range of 1-3 nm. This range not only meets practical operational requirements but also ensures that this error range does not significantly impact CD-SEM measurement, facilitating the determination of more accurate measurement parameters and thus improving overlay accuracy. In this embodiment, the shrinkage is preferably 2.5 nm. This shrinkage defines the module size setting, further improving the accuracy of measurement parameters and thus overlay accuracy.

[0046] The present application also provides a terminal, which also has the above-mentioned measurement method and system for improving the wafer pattern overlay accuracy and corresponding technical effects, which will not be repeated here.

[0047] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0049] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 A schematic flow chart of a measurement method for improving wafer pattern overlay accuracy provided in an embodiment of the present application;

[0051] Figure 2 Schematic diagram of a method for measuring reference line width in an embodiment of the present application;

[0052] Figure 3 A comparative schematic diagram of controlling the shrinkage size of two adjacent photoresist layers by adjusting measurement parameters in an embodiment of the present application;

[0053] Figure 4 A schematic structural diagram of a measurement system for improving wafer pattern overlay accuracy provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0055] In order to better understand the present application, the implementation methods of the present application are explained in detail below with reference to the accompanying drawings.

[0056] Example 1

[0057] See also Figure 1 , Figure 1 The flow chart of a measurement method for improving wafer pattern overlay accuracy provided by an embodiment of the present application is as follows. Figure 1 It can be seen that the measurement method for improving wafer pattern overlay accuracy in this embodiment mainly includes the following processes:

[0058] S1: The definition chip includes multiple photoresists.

[0059] That is to define the various photoresists used in chip manufacturing.

[0060] S2: Perform atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain a reference line width of any photoresist.

[0061] Specifically, step S2 includes the following process:

[0062] S21: Pre-treating the wafer coated with any photoresist.

[0063] The method for pre-processing a wafer in this embodiment includes:

[0064] S211: forming an SOC layer, an SOG layer and any photoresist layer on the wafer in order from bottom to top, and spin-coating any photoresist layer on the SOG layer.

[0065] That is, firstly, an SOC layer is formed on the wafer, then an SOG layer is formed on the side of the SOC layer facing away from the wafer, and finally, a photoresist layer is spin-coated on the side of the SOG layer facing away from the wafer.

[0066] S212: performing exposure, development, and post-baking treatments on the wafer coated with any photoresist in sequence to obtain a pre-treated wafer.

[0067] The specific methods of exposure, development and post-baking treatment adopt the methods in the prior art and will not be described in detail here.

[0068] After the wafer is pre-processed, step S22 is executed: performing atomic layer deposition on the pre-processed wafer to obtain a wafer with a surface layer deposited. The metal layer used for the atomic layer deposition includes: ZnO or Al2O3.

[0069] The metal used in atomic layer deposition can be zinc oxide or aluminum oxide.

[0070] The method of performing atomic layer deposition on the pre-treated wafer in this embodiment is as follows: placing the pre-treated wafer into an ALD device for atomic layer deposition. The process conditions of the atomic layer deposition are: a deposition temperature of 80°C and a deposition rate of The deposition thickness is 5-10 nm, and the deposition time is 75 minutes to 150 minutes.

[0071] This atomic layer deposition process condition limits the temperature, deposition rate, deposition thickness and deposition time, which can effectively improve the effect of atomic layer deposition, thereby improving the accuracy of the reference line width, and ultimately reducing the overlay error and improving the overlay accuracy.

[0072] Furthermore, in this embodiment, atomic layer deposition is performed on the pre-treated wafer. After obtaining the wafer with the surface layer deposited, step S23 is also included: pickling the wafer with the surface layer deposited to remove the metal oxide on the top layer, thereby removing impurities, improving the atomic layer deposition effect, and obtaining a reference line width that is closer to the actual size, which is conducive to further improving the accuracy of the reference line width.

[0073] After obtaining the wafer with the surface layer deposited, step S24 is performed: using CD-SEM to measure the distance between the inner walls of the metal layer in the wafer with the surface layer deposited, and obtaining the reference line width of any photoresist.

[0074] The reference line width in this embodiment is the actual line width of the photoresist. The measurement method can be found in Figure 2 shown. Figure 2 The metal layer in the embodiment is aluminum oxide.

[0075] Continue to see Figure 1 It can be seen that after obtaining the reference line width of any photoresist, step S3 is executed: CD-SEM measurement is performed on another wafer coated with any photoresist, and the actual line width of any photoresist is reduced by 1-3nm compared with the reference line width by adjusting the measurement parameters.

[0076] The measurement parameters in this embodiment include acceleration voltage and electron beam density. When controlling the shrinkage of the actual photoresist line width relative to the reference line width, the acceleration voltage, the electron beam density, or both can be adjusted to ultimately control the shrinkage within a uniform error range.

[0077] Specifically, step S3 includes the following process:

[0078] S31: Pre-processing another wafer coated with any photoresist.

[0079] The pretreatment method for the other wafer used to measure the actual line width here is the same as the pretreatment method for the wafer used to obtain the reference line width in step S21. The SOC layer, SOG layer and any photoresist layer are formed on the other wafer in sequence from bottom to top, and any photoresist layer is spin-coated on the SOG layer; the other wafer coated with any photoresist is exposed, developed and post-baked in sequence to obtain the other wafer after pretreatment.

[0080] The difference is that atomic layer deposition is not performed on the other wafer, and step S32 is performed: the other wafer after pretreatment is measured using CD-SEM, and the measurement parameters are adjusted so that the actual line width of any photoresist is shrunk by 1-3 nm compared to the reference line width.

[0081] That is, by adjusting the CD-SEM measurement parameters, the shrinkage size of any photoresist is controlled to be 1-3nm.

[0082] In this embodiment, steps S2 and S3 are performed for each type of photoresist included in the chip, respectively obtaining the reference line width and actual line width matched to each type of photoresist, and controlling the shrinkage of the actual line width relative to the reference line width to be within the same error range of 1-3nm. By controlling the shrinkage of each layer of photoresist within the same range, the shrinkage of each layer of photoresist pattern is kept consistent, thereby ensuring that the actual line width errors caused by CD-SEM measurement of two adjacent layers of photoresist are consistent. This eliminates the errors caused by CD-SEM measurement between photoresist layers, thereby significantly improving the wafer pattern overlay accuracy.

[0083] Furthermore, in this embodiment, CD-SEM measurement is performed on another wafer coated with any photoresist. When the measurement parameters are adjusted, the actual line width of any photoresist can be controlled to have a shrinkage size of 2.5nm compared to the reference line width. The setting of this shrinkage size further refines the restriction on the shrinkage size of each layer of photoresist, and the size is easy to achieve, which can further improve the accuracy and reliability of the determined measurement parameters, thereby helping to improve the overlay accuracy.

[0084] Continue to see Figure 1 It can be seen that after adjusting the measurement parameters so that the actual line width of any photoresist is shrunk by 1-3 nm compared to the reference line width, step S4 is performed: recording the measurement parameters matching any photoresist.

[0085] S5: Summarize the measurement parameters matched by each photoresist in the chip and build a measurement parameter database.

[0086] Steps S2 to S4 are performed for each photoresist included in the chip to obtain measurement parameters matching each photoresist, and then a measurement parameter database is constructed through step S5.

[0087] By building a measurement parameter database, for the same type of photoresist, when adjusting the actual line width shrinkage, the measurement parameters in the measurement parameter database can be directly called, which can not only improve the overlay accuracy, but also greatly improve the efficiency of photoresist pattern measurement.

[0088] S6: Measure the photoresist pattern according to the measurement parameter database.

[0089] In this embodiment, the comparison diagram of the shrinkage size of two adjacent photoresist layers is controlled by adjusting the measurement parameters, which can be seen in Figure 3 As shown. Figure 3It can be seen that for the same wafer pattern with two reference line widths of 30nm in photoresist a and photoresist b, when the shrinkage amount is not determined by the reference line width to determine the CD-SEM adjustment parameter setting of either photoresist, the actual line widths obtained after CD-SEM measurement are 27nm and 28nm respectively. Based on this measurement result, the staff will determine that photoresist a and photoresist b have wafer patterns of different sizes. After adopting the measurement method in this embodiment, after obtaining the adjustment parameters of photoresist a and photoresist b, since after adjusting the accelerating voltage and electron beam density according to the adjustment parameters, the shrinkage of different photoresists when measured by CD-SEM is the same, so that the same wafer pattern with two reference line widths of 30nm for photoresist a and photoresist b can obtain a measurement result of 27.5nm after being measured. Based on this measurement result, the staff will determine that photoresist a and photoresist b have wafer patterns of the same size, and in actual conditions, photoresist a and photoresist b also have wafer patterns of the same size, so the determination result is more accurate. It can be seen that after adopting the method in steps S1-S6, although 27.5nm still has a measurement error compared to 30nm, the error between photoresist a and photoresist b is greatly reduced. That is, the method in this embodiment can eliminate the error caused by CD-SEM measurement between different photoresist layers, thereby effectively reducing the overlay error and improving the overlay accuracy.

[0090] Example 2

[0091] exist Figure 1-Figure 3 Based on the embodiment shown, see Figure 4 , Figure 4 This is a schematic diagram of the structure of a measurement system for improving wafer pattern overlay accuracy provided by an embodiment of the present application. Figure 4 It can be seen that the measurement system for improving wafer pattern overlay accuracy in this embodiment mainly includes: a definition module, a reference line width acquisition module, a shrinkage size limitation module, a measurement parameter recording module, a measurement parameter database construction module and a photoresist pattern measurement module.

[0092] Among them, the definition module is used to define multiple photoresists included in the chip; the reference line width acquisition module is used to perform atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain the reference line width of any photoresist; the shrinkage size limitation module is used to perform CD-SEM measurement on another wafer coated with any photoresist, and by adjusting the measurement parameters, the actual line width of any photoresist is 1-3nm compared to the reference line width. The measurement parameters include: acceleration voltage and electron beam density; the measurement parameter recording module is used to record the measurement parameters matching any photoresist; the measurement parameter database construction module is used to summarize the measurement parameters matching each photoresist in the chip and construct a measurement parameter database; the photoresist pattern measurement module is used to measure the photoresist pattern according to the measurement parameter database.

[0093] Furthermore, the reference linewidth acquisition module includes: a first preprocessing unit, an ALD device, and a reference linewidth measurement unit. The first preprocessing unit is used to preprocess a wafer coated with any photoresist; the ALD device is used to perform atomic layer deposition on the preprocessed wafer to obtain a wafer with a surface layer deposited thereon, where the metal layer used for atomic layer deposition includes ZnO or Al2O3; and the reference linewidth measurement unit is used to measure the distance between the inner walls of the metal layer in the wafer with the surface layer deposited thereon using a CD-SEM to obtain the reference linewidth of any photoresist.

[0094] When the first pretreatment unit performs pretreatment, the pretreated wafer is placed in the ALD equipment for atomic layer deposition. The process conditions of the atomic layer deposition are: deposition temperature is 80 ° C, deposition rate is The deposition thickness is 5-10 nm, and the deposition time is 75 minutes to 150 minutes.

[0095] The shrinkage dimension qualification module includes a second pre-processing unit and an actual linewidth measurement unit. The second pre-processing unit is used to pre-process another wafer coated with any photoresist. The actual linewidth measurement unit is used to measure the pre-processed wafer using a CD-SEM and adjust measurement parameters to reduce the actual linewidth of any photoresist to a shrinkage dimension of 1-3nm compared to the reference linewidth.

[0096] Furthermore, in this embodiment, when the shrinkage size limiting module performs CD-SEM measurement on another wafer coated with any photoresist, the actual line width of any photoresist can be adjusted by adjusting the measurement parameters so that the shrinkage size of the reference line width is 2.5nm, that is, the shrinkage size is preferably limited to 2.5nm. By adjusting the measurement parameters, when the size of the photoresist in the other wafer after shrinkage is measured using CD-SEM, the shrinkage size is controlled to 2.5nm. The shrinkage size of all photoresist layers is controlled to a uniform 2.5nm, and the current measurement parameters are recorded by the measurement parameter recording module. This size limitation can further unify the shrinkage size of photoresists of different layers, which is conducive to further reducing overlay error and improving overlay accuracy.

[0097] The working principle and working method of the measurement system for improving wafer pattern overlay accuracy in this embodiment are as follows: Figure 1-Figure 3 The embodiments shown have been described in detail, and the two embodiments can refer to each other, so they will not be described again here.

[0098] Example 3

[0099] The present application also provides a terminal, which includes: a processor and a memory communicatively connected to the processor, wherein the memory stores instructions that can be executed by the processor, and the instructions are executed by the processor so that the processor can execute the above-mentioned measurement method for improving the wafer pattern overlay accuracy.

[0100] The measurement method implemented by the processor to improve wafer pattern overlay accuracy is as follows:

[0101] 1) Define that a chip includes multiple photoresists.

[0102] 2) Performing atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain a reference line width of any photoresist.

[0103] First, a wafer coated with any photoresist is pretreated. Then, atomic layer deposition is performed on the pretreated wafer to obtain a wafer with a surface layer deposited thereon, wherein the metal layer used for atomic layer deposition includes: ZnO or Al2O3. Finally, a CD-SEM is used to measure the distance between the inner walls of the metal layer in the wafer with the surface layer deposited thereon, thereby obtaining a reference line width of any photoresist.

[0104] The specific pretreatment method is: forming an SOC layer, an SOG layer and any photoresist layer on the wafer in order from bottom to top, and any photoresist layer is spin-coated on the SOG layer; exposing, developing and post-baking the wafer coated with any photoresist in turn to obtain a pretreated wafer.

[0105] 3) Performing CD-SEM measurement on another wafer coated with either photoresist, adjusting measurement parameters such that the actual line width of either photoresist shrinks by 1-3 nm compared to the reference line width, wherein the measurement parameters include acceleration voltage and electron beam density.

[0106] First, another wafer coated with either photoresist is pre-processed. Then, the pre-processed wafer is measured using a CD-SEM. Measurement parameters are adjusted to reduce the actual line width of the photoresist by 1-3 nm compared to the reference line width. Note that the other wafer does not require atomic layer deposition.

[0107] To further improve overlay accuracy, when performing CD-SEM measurement on another wafer coated with any photoresist, the measurement parameters can be adjusted so that the actual line width of any photoresist shrinks by 2.5 nm compared to the reference line width.

[0108] 4) Record the measurement parameters that match any photoresist.

[0109] 5) Summarize the measurement parameters matched by each photoresist in the chip and build a measurement parameter database.

[0110] 6) Measure the photoresist pattern according to the measurement parameter database.

[0111] The specific execution steps and principles of the above methods can be found in Figure 1-Figure 3 The embodiment shown in FIG. Figure 4 The second embodiment shown will not be described in detail here.

[0112] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand and implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A measurement method for improving wafer pattern overlay accuracy, characterized in that: The method comprises: The definition chip includes multiple photoresists; Performing atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain a reference line width of the any photoresist; Performing CD-SEM measurement on another wafer coated with any of the photoresists, adjusting measurement parameters so that the actual line width of any of the photoresists shrinks by 1-3 nm compared to the reference line width, the measurement parameters including: acceleration voltage and electron beam density; Recording measurement parameters matching any one of the photoresists; Summarizing the measurement parameters matched by each photoresist in the chip and constructing a measurement parameter database; Photoresist pattern measurement is performed according to the measurement parameter database.

2. A measurement method for improving wafer pattern overlay accuracy according to claim 1, characterized in that: The shrinkage size is 2.5 nm.

3. The measurement method for improving wafer pattern overlay accuracy according to claim 1, wherein: The step of performing atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain a reference line width of the photoresist comprises: Pre-treating the wafer coated with any one of the photoresists; Performing atomic layer deposition on the pre-treated wafer to obtain a wafer with a surface layer deposited, wherein the metal layer used for the atomic layer deposition includes: ZnO or Al2O3; The distance between the inner walls of the metal layer in the wafer on which the surface layer is deposited is measured using CD-SEM to obtain a reference line width of any photoresist.

4. The measurement method for improving wafer pattern overlay accuracy according to claim 3, wherein: A method for pre-treating a wafer coated with any of the photoresists, comprising: forming a SOC layer, a SOG layer and any photoresist layer on the wafer in order from bottom to top, wherein the any photoresist layer is spin-coated on the SOG layer; The wafer coated with any of the photoresists is sequentially subjected to exposure, development and post-baking treatments to obtain a pre-treated wafer.

5. The measurement method for improving wafer pattern overlay accuracy according to claim 3, wherein: A method for performing atomic layer deposition on a pre-treated wafer to obtain a wafer with a surface layer deposited thereon comprises: The pre-treated wafer was placed in the ALD equipment for atomic layer deposition. The process conditions of atomic layer deposition were as follows: deposition temperature was 80°C, deposition rate was The deposition thickness is 5-10 nm, and the deposition time is 75 minutes to 150 minutes.

6. The measurement method for improving wafer pattern overlay accuracy according to claim 1, wherein: A method for performing CD-SEM measurement on another wafer coated with any of the photoresists, and adjusting measurement parameters so that the actual line width of any of the photoresists shrinks by 1-3 nm compared to the reference line width, comprising: Pre-treating another wafer coated with any one of the photoresists; The other wafer after pretreatment is measured by CD-SEM, and measurement parameters are adjusted so that the actual line width of any photoresist is reduced by 1-3 nm compared with the reference line width.

7. A measurement system for improving wafer pattern overlay accuracy, characterized in that: The system comprises: A definition module, used to define the chip including multiple photoresists; A reference line width acquisition module is used to perform atomic layer deposition and CD-SEM measurement on a wafer coated with any photoresist to obtain a reference line width of the photoresist; A shrinkage dimension limiting module is used to perform CD-SEM measurement on another wafer coated with any of the photoresists, and adjust measurement parameters so that the shrinkage dimension of the actual line width of any of the photoresists is 1-3 nm compared to the reference line width, wherein the measurement parameters include: acceleration voltage and electron beam density; A measurement parameter recording module, configured to record measurement parameters matching any one of the photoresists; A measurement parameter database construction module, used to summarize the measurement parameters matched by each photoresist in the chip and construct a measurement parameter database; The photoresist pattern measurement module is used to measure the photoresist pattern according to the measurement parameter database.

8. The measurement system for improving wafer pattern overlay accuracy according to claim 7, characterized in that: The reference line width acquisition module includes: A first pre-processing unit, configured to pre-process the wafer coated with any one of the photoresists; ALD equipment is used to perform atomic layer deposition on the pre-treated wafer to obtain a wafer with a surface layer deposited, wherein the metal layer used for atomic layer deposition includes: ZnO or Al2O3; The reference line width measurement unit is used to measure the distance between the inner walls of the metal layer in the wafer on which the surface layer is deposited using a CD-SEM to obtain the reference line width of any photoresist.

9. The measurement system for improving wafer pattern overlay accuracy according to claim 7, wherein: The shrinkage size limiting module includes: a second pre-processing unit, configured to pre-process another wafer coated with any one of the photoresists; The actual line width measurement unit is used to measure the other wafer after pretreatment by using CD-SEM, and adjust the measurement parameters so that the actual line width of any photoresist is shrunk by 1-3 nm compared with the reference line width.

10. A terminal, characterized in that: The terminal includes: a processor and a memory in communication with the processor, wherein: The memory stores instructions that can be executed by the processor, and the instructions are executed by the processor so that the processor can execute the measurement method for improving wafer pattern overlay accuracy as described in any one of claims 1 to 6.

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