Self-destructive device and chip

Abstract

The application discloses a self-destroying device and a chip, and relates to the technical field of electronics. The self-destroying device comprises a first self-destroying electrode and a second self-destroying electrode, a middle silicon layer, a first silicon layer doping and a second silicon layer doping, one side of the middle silicon layer is connected with the first self-destroying electrode through the first silicon layer doping, the other side of the middle silicon layer is connected with the second self-destroying electrode through the second silicon layer doping, a sealing layer, the middle silicon layer is closed by the sealing layer, the first silicon layer doping and the second silicon layer doping, a substrate, and the substrate is connected with the sealing layer. When the first self-destroying electrode receives a first preset threshold electrical signal, the second self-destroying electrode receives a second preset threshold electrical signal, the substrate receives a third preset threshold electrical signal, and the third preset threshold electrical signal lasts for a fourth preset threshold time length, the temperature of the middle silicon layer in the closed space is increased, so that the device is broken down or burned. The application has low cost and high integration, can guarantee normal work of the chip, and can quickly self-destroy.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic technology, and in particular to a self-destroying device and a chip. BACKGROUND

[0002] With the rapid development of semiconductor technology, chips have become the key carriers of information technology. When chips containing core intellectual property rights of enterprises and personal privacy are lost, they will pose a great threat to information security. Therefore, it is extremely urgent to use transient electronic technology to make the chip self-destroy (i.e., self-destroy) in function and even physical form when its information security is threatened. The implementation methods of transient electronic technology include stress destruction method and chemical corrosion method. In order to achieve high destruction precision and response speed, the microstructure design and process implementation process of the stress destruction method are relatively complex. The cavity process of the chemical corrosion method is relatively complex, and the high polymer material and chemical corrosion agent used are difficult to achieve long-term stable storage, which has safety hazards. SUMMARY

[0003] The purpose of the present application is to provide a self-destroying device and a chip, which is easy to integrate with a silicon-based functional circuit, has low cost, high integration, and isolation characteristics that ensure normal operation of the chip and fast self-destruction.

[0004] To solve the above technical problems, the present application adopts the following technical solutions:

[0005] The first aspect of the embodiment of the present application provides a self-destroying device, which comprises: a first self-destroying electrode and a second self-destroying electrode; an intermediate silicon layer, a first silicon layer doping and a second silicon layer doping, one side of the intermediate silicon layer is connected to the first self-destroying electrode through the first silicon layer doping, the other side of the intermediate silicon layer is connected to the second self-destroying electrode through the second silicon layer doping; a sealing layer, which cooperates with the first silicon layer doping and the second silicon layer doping to enclose the intermediate silicon layer; a substrate connected to the sealing layer; when the first self-destroying electrode receives a first preset threshold electrical signal, the second self-destroying electrode receives a second preset threshold electrical signal, and the substrate receives a third preset threshold electrical signal for a fourth preset threshold duration, the temperature of the intermediate silicon layer in the enclosed space rises, so that the device is broken down or burned out.

[0006] In some embodiments, the sealing layer is made of a material with low thermal conductivity.

[0007] In some embodiments, the sealing layer comprises a first buried oxygen layer and a second buried oxygen layer, the bottom of the first buried oxygen layer is connected to the top of the intermediate silicon layer, the two sides of the first buried oxygen layer are respectively connected to the inner sides of the first self-destroying electrode and the second self-destroying electrode, the top of the second buried oxygen layer is respectively connected to the bottom of the first silicon layer doping, the bottom of the intermediate silicon layer and the bottom of the second silicon layer doping, and the substrate is arranged at the bottom of the second buried oxygen layer.

[0008] In some embodiments, the self-destroying device further comprises a parasitic transistor, the parasitic transistor comprising a source doping, a drain doping, a gate electrode and a top silicon layer, two ends of a top of the top silicon layer being connected to the source doping and the drain doping respectively, a middle end of the top of the top silicon layer being connected to the gate electrode, and a top of the first buried oxide layer being connected to a bottom of the top silicon layer.

[0009] In some embodiments, the self-destroying device further comprises a first isolation layer and a second isolation layer, the first isolation layer and the second isolation layer being arranged on a top of the second buried oxide layer, the first isolation layer being arranged outside the first self-destroying electrode and the first silicon layer doping, and the second isolation layer being arranged outside the second self-destroying electrode and the second silicon layer doping.

[0010] In some embodiments, the self-destroying device further comprises a third isolation layer and a fourth isolation layer, the third isolation layer and the fourth isolation layer being arranged on a top of the first buried oxide layer, the third isolation layer being arranged outside the top silicon layer and the source doping, and the fourth isolation layer being arranged outside the top silicon layer and the drain doping, the parasitic transistor being separated from the first self-destroying electrode by the third isolation layer, and the parasitic transistor being separated from the second self-destroying electrode by the fourth isolation layer.

[0011] In some embodiments, the thickness of the top silicon layer is 40-70 nm, the thickness of the intermediate silicon layer is 130-160 nm, the thickness of the first buried oxide layer is 130-160 nm, and the thickness of the second buried oxide layer is 130-160 nm.

[0012] In some embodiments, the first preset threshold value is a positive value, the first preset threshold value is greater than the second preset threshold value, the absolute value of the voltage difference between the first preset threshold value electric signal and the second preset threshold value electric signal is greater than 100 V, and the voltage of the third preset threshold value electric signal is 8 V.

[0013] In some embodiments, the fourth preset threshold time is set to 10-20 s.

[0014] The second aspect of the embodiment of the present application provides a chip, the chip comprising the self-destroying device as described above.

[0015] According to the self-destroying device and chip, the following beneficial effects are achieved: a high voltage is applied between the first self-destroying electrode and the second self-destroying electrode, the substrate applies a starting voltage, collision ionization is caused, amplification effects of the intermediate silicon layer, the first silicon layer doping and the second silicon layer doping are triggered, current is amplified, and the temperature sharply increases due to the low thermal conductivity of the first buried oxide layer and the second buried oxide layer, so that the whole device is broken down or burned out. The design has high flexibility, is easy to integrate with a silicon-based functional circuit, has low cost and high integration, and has double-isolation characteristics, which ensures normal operation of the chip and fast self-destruction.

[0016] It should be understood that the foregoing general description and the following detailed description are only examples and do not limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 The self-destroying device structure according to the embodiment is shown in the figure.

[0019] The reference signs are explained as follows: 1, first self-destroying electrode; 2, second self-destroying electrode; 3, intermediate silicon layer; 4, first silicon layer doping; 5, second silicon layer doping; 6, substrate; 7, first buried oxide layer; 8, second buried oxide layer; 9, source doping; 10, drain doping; 11, gate electrode; 12, top silicon layer; 13, first isolation layer; 14, second isolation layer; 15, third isolation layer; 16, fourth isolation layer. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0021] In the description of the present application, it needs to be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0022] The terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0023] In the description of the present application, it needs to be explained that, unless otherwise explicitly specified and limited, the terms "communication", "installation", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0024] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these example implementations are provided so that this disclosure will be thorough and complete, and will fully convey the inventive aspects of the example implementations to those skilled in the art. The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, the descriptions and numerical ranges provided herein should also be understood as not being limited by the particular values provided. Identical reference numerals have been used in the drawings and the description to represent the same or similar components.

[0025] The technical solutions of the embodiments of the present application will be briefly described below:

[0026] According to some embodiments, as Figure 1 The present application provides a self-destruction device, which comprises:

[0027] A first self-destruction electrode 1 and a second self-destruction electrode 2;

[0028] An intermediate silicon layer 3, a first silicon layer doping 4 and a second silicon layer doping 5, one side of the intermediate silicon layer 3 is connected to the first self-destroying electrode 1 through the first silicon layer doping 4, the other side of the intermediate silicon layer 3 is connected to the second self-destroying electrode 2 through the second silicon layer doping 5;

[0029] A sealing layer, which seals the intermediate silicon layer 3 in cooperation with the first silicon layer doping 4 and the second silicon layer doping 5;

[0030] A substrate 6, which is connected to the sealing layer;

[0031] When the first self-destroying electrode 1 receives a first preset threshold electrical signal, the second self-destroying electrode 2 receives a second preset threshold electrical signal, the substrate 6 receives a third preset threshold electrical signal, and lasts for a fourth preset threshold time length, the temperature of the intermediate silicon layer 3 in the sealed space rises, so that the device is broken down or burned out.

[0032] Wherein, the electrical signal includes voltage signal and current signal.

[0033] Based on the above embodiment, the first preset threshold electrical signal, the second preset threshold electrical signal, the third preset threshold electrical signal and the fourth preset threshold time length can be set according to actual needs. Wherein, the voltage difference of the first preset threshold electrical signal and the second preset threshold electrical signal needs to reach or exceed the voltage difference value required for device self-destruction; the third preset threshold electrical signal is the electrical signal value required for opening the device self-destruction, and the fourth preset threshold time length is the time length required for device self-destruction after opening the device self-destruction.

[0034] When the device self-destroys, the electrical signal is applied to the substrate 6, the first self-destroying electrode 1 and the second self-destroying electrode 2, if the voltage of the first preset threshold electrical signal is greater than the voltage of the second preset threshold electrical signal, the current direction is from the first self-destroying electrode 1 to the first silicon layer doping 4, from the first silicon layer doping 4 to the intermediate silicon layer 3, from the intermediate silicon layer 3 to the second silicon layer doping 5, and finally from the second silicon layer doping 5 to the second self-destroying electrode 2. If the voltage of the first preset threshold electrical signal is less than the voltage of the second preset threshold electrical signal, the current direction is from the second self-destroying electrode 2 to the second silicon layer doping 5, from the second silicon layer doping 5 to the intermediate silicon layer 3, from the intermediate silicon layer 3 to the first silicon layer doping 4, and finally from the first silicon layer doping 4 to the first self-destroying electrode 1. In the process of current flow, Joule heat is generated, and the heat calculation method is Joule's law Q=I 2 ×R×t, the sealing layer makes it difficult for the heat of the intermediate silicon layer 3 to dissipate, the temperature of the intermediate silicon layer 3 rises rapidly, so that the device is broken down or burned out.

[0035] The specific embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings of the present disclosure. Figure 1 The preferred embodiments of the present disclosure are further described in detail.

[0036] According to some embodiments, the sealing layer is made of a material with low thermal conductivity.

[0037] Based on the above embodiments, the material with low thermal conductivity can make it difficult for the heat of the intermediate silicon layer 3 to be transferred out, and can make the temperature of the intermediate silicon layer 3 rapidly rise when the device is self-destroyed, and the device is rapidly self-destroyed due to high temperature.

[0038] According to some embodiments, as shown in Figure 1 The sealing layer includes a first buried oxygen layer 7 and a second buried oxygen layer 8, the bottom of the first buried oxygen layer 7 is connected to the top of the intermediate silicon layer 3, and the two sides of the first buried oxygen layer 7 are respectively connected to the inner sides of the first self-destroying electrode 1 and the second self-destroying electrode 2, the top of the second buried oxygen layer 8 is respectively connected to the bottom of the first silicon layer doping 4, the bottom of the intermediate silicon layer 3 and the bottom of the second silicon layer doping 5, and the substrate 6 is arranged at the bottom of the second buried oxygen layer 8.

[0039] As shown in Figure 1 The substrate 6 can be used as a support for the device, and the second buried oxygen layer 8 is used to isolate the intermediate silicon layer 3 and the substrate 6.

[0040] Further, the thickness of the first buried oxygen layer 7 and the second buried oxygen layer 8 is set to 145 nm, and the material with low thermal conductivity is used to make the intermediate silicon layer 3 rapidly heat up.

[0041] As shown in Figure 1 The two sides of the intermediate silicon layer 3 are respectively connected to the first silicon layer doping 4 and the second silicon layer doping 5, the upper side of the first silicon layer doping 4 is connected to the first self-destroying electrode 1, the upper side of the second silicon layer doping 5 is connected to the second self-destroying electrode 2, and the top of the second buried oxygen layer 8 is respectively connected to the bottom of the first silicon layer doping 4, the bottom of the intermediate silicon layer 3 and the bottom of the second silicon layer doping 5. The intermediate silicon layer 3 and the first silicon layer doping 4 and the second silicon layer doping 5 on both sides form an NPN device, and the substrate 6 is used to turn on the NPN device. According to Joule's law Q = I 2 × R × t, when the current flowing through the NPN device is too large, the NPN device generates high heat to self-destruct.

[0042] According to some embodiments, the self-destroying device further includes a parasitic transistor, the parasitic transistor includes a source doping 9, a drain doping 10, a gate electrode 11 and a top layer silicon 12, the top of the top layer silicon 12 is respectively connected to the source doping 9 and the drain doping 10, the top of the top layer silicon 12 is connected to the gate electrode 11, and the top of the first buried oxygen layer 7 is connected to the bottom of the top layer silicon 12.

[0043] As shown in Figure 1As shown, the first buried oxide layer 7 is used to isolate the intermediate silicon layer 3 and the top silicon layer 12. The source doping 9, drain doping 10, gate electrode 11 and top silicon layer 12 form another NPN device, which can be used normally as a parasitic transistor when it does not self-destruct.

[0044] According to some embodiments, such as Figure 1 As shown, the self-destruct device also includes a first isolation layer 13 and a second isolation layer 14. The first isolation layer 13 and the second isolation layer 14 are both disposed on the top of the second buried oxide layer 8. The first isolation layer 13 is disposed outside the first self-destruct electrode 1 and the first silicon layer doped 4, and the second isolation layer 14 is disposed outside the second self-destruct electrode 2 and the second silicon layer doped 5.

[0045] Among them, such as Figure 1 As shown, the first isolation layer 13 and the second isolation layer 14 are used to separate the devices on the left and right sides to prevent the devices on the left and right sides from coming into contact with the first self-destruct electrode 1 and the second self-destruct electrode 2, which would cause a short circuit.

[0046] According to some embodiments, such as Figure 1 As shown, the self-destruct device further includes a third isolation layer 15 and a fourth isolation layer 16. The third isolation layer 15 and the fourth isolation layer 16 are both disposed on top of the first buried oxide layer 7. The third isolation layer 15 is disposed outside the top silicon layer 12 and the source doped layer 9, and the fourth isolation layer 16 is disposed outside the top silicon layer 12 and the drain doped layer 10. The parasitic transistor is separated from the first self-destruct electrode 1 by the third isolation layer 15, and the parasitic transistor is separated from the second self-destruct electrode 2 by the fourth isolation layer 16.

[0047] Based on the above embodiments, such as Figure 1 As shown, the top of the first buried oxide layer 7 is sequentially connected to a third isolation layer 15, a parasitic transistor, and a fourth isolation layer 16. The left side of the first buried oxide layer 7 and the third isolation layer 15 is connected to a first self-destructing electrode 1, and the right side of the first buried oxide layer 7 and the fourth isolation layer 16 is connected to a second self-destructing electrode 2. The third isolation layer 15 is used to prevent short circuits or mutual interference between the first self-destructing electrode 1 and the source doped electrode 9 and the top silicon layer 12. The fourth isolation layer 16 is used to prevent short circuits or mutual interference between the second self-destructing electrode 2 and the drain doped electrode 10 and the top silicon layer 12.

[0048] In some preferred embodiments, the thickness of the top silicon layer 12 is set to be between 40 and 70 nm, the thickness of the intermediate silicon layer 3 is set to be between 130 and 160 nm, the thickness of the first buried oxide layer 7 is set to be between 130 and 160 nm, and the thickness of the second buried oxide layer 8 is set to be between 130 and 160 nm.

[0049] According to some embodiments, the first preset threshold is a positive value, the first preset threshold is greater than the second preset threshold, and an absolute value of a voltage difference between the first preset threshold and the second preset threshold is greater than 100 V, and the voltage of the third preset threshold is 8 V.

[0050] Based on the above embodiments, the first preset threshold and the second preset threshold can be set according to actual needs. In some embodiments, the substrate 6 of the self-destroying device has an opening voltage of 8 V, and an absolute value of a voltage difference between the first preset threshold and the second preset threshold is greater than 100 V. In other embodiments, the second preset threshold can also be set as a positive value, the second preset threshold is greater than the first preset threshold, and an absolute value of a voltage difference between the first preset threshold and the second preset threshold is greater than 100 V, that is, the voltage difference between the first self-destroying electrode 1 and the second self-destroying electrode 2 is greater than 100 V. When the first self-destroying electrode 1, the second self-destroying electrode 2 and the substrate 6 are powered on, the device can quickly heat up to achieve the purpose of self-destruction.

[0051] According to some embodiments, the fourth preset threshold time is set to 10 s to 20 s.

[0052] According to some embodiments, the application provides a chip, which comprises the self-destroying device as described above.

[0053] Based on the above embodiments, when the chip is lost and needs to remotely control the device to self-destroy, a self-destroying signal is sent to the chip, the chip controls the first self-destroying electrode 1, the second self-destroying electrode 2 and the substrate 6 to be powered on, controls the voltage difference between the first self-destroying electrode 1 and the second self-destroying electrode 2 to be greater than 100 V, and the substrate 6 is powered on with an 8 V electrical signal. When the time is about 10 s to 20 s, the middle silicon layer 3 in the self-destroying device is broken down or burned out due to insufficient heat dissipation and excessive heat, which further causes the chip to be broken down or burned out, so that the chip cannot operate, thereby preventing the information stored in the chip from being stolen. The self-destroying device can be arranged in a chip used in any field, which can ensure normal operation of the chip and quickly self-destroy.

[0054] In the description of the above-described embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0055] Although the present disclosure has been described with reference to several exemplary embodiments, it will be understood that the terms used are illustrative and not restrictive, and the present disclosure is not limited to any of the above-described details. Since the present disclosure can be embodied in various forms without departing from the spirit or essential characteristics thereof, it should be understood that the above-described embodiments are not limited to any of the above-described details, but are to be interpreted broadly and liberally in the spirit and scope of the appended claims, and all modifications, equivalents and substitutes falling within the scope of the claims or their equivalents are intended to be embraced by the appended claims.

Claims

1. A self-destruct device, characterized in that, The self-destruct device includes: First self-destructing electrode and second self-destructing electrode; An intermediate silicon layer, a first silicon layer doped, and a second silicon layer doped are provided. One side of the intermediate silicon layer is connected to the first self-destruct electrode through the first silicon layer doping, and the other side of the intermediate silicon layer is connected to the second self-destruct electrode through the second silicon layer doping. The intermediate silicon layer, together with the first and second silicon layer doping on both sides, forms an NPN device. A sealing layer, which, in conjunction with the doping of the first silicon layer and the doping of the second silicon layer, seals the intermediate silicon layer; Substrate, the substrate being connected to the sealing layer; When the first self-destructing electrode receives a first preset threshold electrical signal, the second self-destructing electrode receives a second preset threshold electrical signal, and the substrate receives a third preset threshold electrical signal to turn on the NPN device, it causes collisional ionization, triggering the amplification effect of the intermediate silicon layer, the first silicon layer doping and the second silicon layer doping, amplifying the current, and after a fourth preset threshold duration, the temperature of the intermediate silicon layer rises in the enclosed space, causing the device to break down or burn out. The sealing layer is made of a material with low thermal conductivity; The sealing layer includes a first buried oxide layer and a second buried oxide layer. The bottom of the first buried oxide layer is connected to the top of the intermediate silicon layer. The two sides of the first buried oxide layer are respectively connected to the inner sides of the first self-destructing electrode and the second self-destructing electrode. The top of the second buried oxide layer is respectively connected to the bottom of the first silicon layer doped, the bottom of the intermediate silicon layer, and the bottom of the second silicon layer doped. The substrate is disposed at the bottom of the second buried oxide layer.

2. The self-destruct device according to claim 1, characterized in that, The self-destruct device also includes a parasitic transistor, which includes a source dopant, a drain dopant, a gate electrode, and a top silicon layer. The top two ends of the top silicon layer are respectively connected to the source dopant and the drain dopant, and the top middle of the top silicon layer is connected to the gate electrode. The top of the first buried oxide layer is connected to the bottom of the top silicon layer.

3. The self-destruct device according to claim 2, characterized in that, The self-destruct device further includes a first isolation layer and a second isolation layer, both of which are disposed on top of the second buried oxide layer. The first isolation layer is disposed outside the first self-destruct electrode and the first silicon layer doping, and the second isolation layer is disposed outside the second self-destruct electrode and the second silicon layer doping.

4. The self-destruct device according to claim 2, characterized in that, The self-destruct device further includes a third isolation layer and a fourth isolation layer, both of which are disposed on top of the first buried oxide layer. The third isolation layer is disposed outside the top silicon and the source doped layer, and the fourth isolation layer is disposed outside the top silicon and the drain doped layer. The parasitic transistor is separated from the first self-destruct electrode by the third isolation layer, and the parasitic transistor is separated from the second self-destruct electrode by the fourth isolation layer.

5. The self-destruct device according to claim 2, characterized in that, The thickness of the top silicon layer is 40~70nm, the thickness of the intermediate silicon layer is 130~160nm, the thickness of the first buried oxide layer is 130~160nm, and the thickness of the second buried oxide layer is 130~160nm.

6. The self-destruct device according to claim 1, characterized in that, The first preset threshold is a positive value, the first preset threshold is greater than the second preset threshold, the absolute value of the voltage difference between the first preset threshold electrical signal and the second preset threshold electrical signal is greater than 100V, and the voltage of the third preset threshold electrical signal is 8V.

7. The self-destruct device according to claim 1, characterized in that, The duration of the fourth preset threshold is set to 10s~20s.

8. A chip, characterized in that, The chip includes a self-destruct device as described in any one of claims 1 to 7.

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