Chip package structure and manufacturing method thereof

Abstract

The application provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises at least a die, a plastic encapsulation layer and a first redistribution layer. The die comprises a plurality of pads and a protection layer. The plastic encapsulation layer covers the die. The front surface of the plastic encapsulation layer exposes the protection layer, and the front surface of the plastic encapsulation layer is lower than the upper surface of the protection layer. The first redistribution layer is located on the upper surface of the protection layer and is electrically connected with the pads. The first type metal pattern block of the first redistribution layer continuously covers the upper surface and the side surface of the protection layer in at least one cross section in the thickness direction. According to the embodiment of the application, the first type metal pattern block of the first redistribution layer continuously covers the upper surface and the side surface of the protection layer in at least one cross section in the thickness direction, forming a lock structure, which can improve the anti-deformation ability of the first type metal pattern block relative to the protection layer in the up-down direction, prevent the first type metal pattern block from being separated from the pads, and thus improve the yield of the chip packaging structure.

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