A semiconductor power device and a manufacturing method thereof

Abstract

The application provides a semiconductor power device and a manufacturing method thereof, the manufacturing method is simple in process, and the number of core masks is reduced from 5-7 to 4 by sharing masks, wherein, compared with a conventional semiconductor power device manufacturing process, two masks for P-type heavily doped regions and N-type heavily doped regions are saved, and a first trench and a second trench with different widths are defined by the same mask (a first mask), so that the second trench is formed without using an additional mask, thereby greatly reducing the process cost and helping to improve the yield. In the application, the second trench is easy to be filled with a doped layer due to the narrow width, the second conductive type dopant in the doped layer diffuses outward to form a second conductive type heavily doped region in a second conductive type well region around the second trench, which can provide an ohmic contact of an IGBT emitter region or a MOSFET source region, reduce the bulk resistance of the second conductive type well region, and help to prevent the triggering of the latch-up effect.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a semiconductor power device and its manufacturing method. Background Technology

[0002] Invented in 1979, the Insulated Gate Bipolar Transistor (IGBT) is a semiconductor power switching device primarily used for energy conversion, transmission, and control. Its applications include home appliances, electric vehicles, industrial control, high-speed rail, new energy, and smart grids. IGBT technology has undergone several generations of continuous improvement over the past few decades. Representative improvements in IGBT structure include: field-stop structure, trench gate, and micro-pattern trench gate structure. The field-stop structure alters the electric field distribution, reducing the thickness of the n-drift region at the same blocking voltage, thereby lowering the IGBT's turn-on voltage. The doping concentration of the field-stop layer can be used to optimize the IGBT's turn-off time and injection efficiency. The introduction of the trench gate increases the gate density and reduces the turn-on voltage. The trench gate also eliminates the parasitic junction field-effect transistor (JFET) found in planar gate structures. The micro-trench gate increases the emitter density and reduces the turn-on voltage. Different micro-trench gate designs provide multiple degrees of freedom for optimizing IGBT parameters.

[0003] The existing manufacturing processes for the aforementioned IGBTs with different structures typically require five to seven core photomasks. A typical core photomask includes: the active region, trench, gate, MOSFET source (n+), p+ (optional), contact window, and metal interconnects. The number of photomasks or the number of lithography steps required in IGBT manufacturing directly impacts device cost and yield. Reducing the number of photomasks has always been a desired goal in manufacturing processes. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor power device and a method for manufacturing the same, in order to solve the problem that the manufacturing of existing semiconductor power devices requires a large number of photomasks, which leads to increased device costs and low yield.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor power device, comprising the following steps:

[0006] A substrate of a first conductivity type is provided, and a well region of a second conductivity type is formed in the substrate;

[0007] Based on the first photomask, a first trench and a second trench are formed in the substrate at intervals. The first trench and the second trench open from the front side of the substrate and extend toward the back side of the substrate. The bottom surface of the first trench is lower than the bottom surface of the second conductivity type well region, the bottom surface of the second trench is higher than the bottom surface of the first trench, and the width of the first trench is greater than the width of the second trench.

[0008] A doped layer containing a second conductivity type dopant is formed in the second trench, and a heat treatment is performed to diffuse the second conductivity type dopant in the doped layer to form a heavily doped region of the second conductivity type around the second trench;

[0009] A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the substrate, and the gate dielectric layer and the gate conductive layer are sequentially filled into the first trench;

[0010] The portion of the gate conductive layer located on the substrate is patterned based on the second photomask;

[0011] A heavily doped region of the first conductivity type is formed on both sides of the first trench by ion implantation self-alignment.

[0012] An interlayer dielectric layer is formed above the substrate;

[0013] The interlayer dielectric layer is patterned based on a third photomask to form a contact hole, which is located above the second trench and exposes the first conductivity type heavily doped region and the second conductivity type heavily doped region.

[0014] A conductor layer is formed on the surface of the interlayer dielectric layer, and the conductor layer fills the contact hole;

[0015] The conductor layer is patterned based on the fourth photomask to obtain the lead structure.

[0016] Optionally, the semiconductor power device includes one of a silicon insulated gate bipolar transistor (SIGBT), a silicon carbide insulated gate bipolar transistor (SIGBT), a double-diffused metal-oxide-semiconductor field-effect transistor (MOSFET), and a silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET).

[0017] Optionally, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0018] Optionally, the first conductivity type is N-type, the second conductivity type is P-type, and the doped layer includes a borosilicate glass oxide layer.

[0019] Optionally, forming a first trench and a second trench spaced apart in the substrate based on the first photomask includes the following steps:

[0020] A hard mask layer is formed on the substrate;

[0021] The hard mask layer is patterned based on the first photomask to form a first opening and a second opening in the hard mask layer, wherein the width of the first opening is greater than the width of the second opening;

[0022] The substrate is etched through the first opening and the second opening to obtain the first trench and the second trench with different depths by utilizing the etching load effect.

[0023] Optionally, forming the doped layer in the second trench includes the following steps:

[0024] The doped layer is deposited on the surface of the substrate, the doped layer fills the first trench and the second trench, and the doped layer fills the second trench but does not fill the first trench;

[0025] When the doped layer is etched back, and the portion of the doped layer located in the first trench and on the substrate is removed, the portion of the doped layer located in the second trench is still completely or mostly retained.

[0026] Optionally, the gate dielectric layer is formed by thermal growth, wherein the heating process for diffusing a second conductivity type dopant in the doped layer to form a heavily doped region of the second conductivity type includes the heating process during the formation of the gate dielectric layer.

[0027] Optionally, the method further includes the following steps: forming a passivation layer on the surface of the conductor layer, and patterning the passivation layer based on a fifth photomask to obtain a contact opening.

[0028] Optionally, the method further includes the step of forming an electrode layer on the back side of the substrate.

[0029] The present invention also provides a semiconductor power device, which is manufactured by the semiconductor power device manufacturing method described in any one of the above claims.

[0030] As described above, the semiconductor power device fabrication method of the present invention has a simple process. By sharing a photomask, the number of core photomasks is reduced from the current mainstream 5-7 layers to 4 layers. Compared with conventional semiconductor power device manufacturing processes, the present invention eliminates the need for two photomasks for the P-type heavily doped region and the N-type heavily doped region. Furthermore, the present invention defines a first trench and a second trench with different widths using the same photomask (first photomask), eliminating the need for an additional photomask to form the second trench, thereby significantly reducing process costs and improving yield. In the present invention, the second trench, due to its narrower width, is easily filled by the doped layer. The second conductivity type dopant in the doped layer diffuses outward to form a second conductivity type heavily doped region in the second conductivity type well region surrounding the second trench. This provides ohmic contact for the IGBT emitter region or the MOSFET source region and reduces the bulk resistance of the second conductivity type well region, helping to prevent latch-up triggering. Attached Figure Description

[0031] Figure 1 The diagram shown is a process flow diagram of the method for fabricating the semiconductor power device of the present invention.

[0032] Figure 2 The diagram shows a method for fabricating a semiconductor power device according to the present invention, in which a second conductivity type well region is formed in a substrate.

[0033] Figure 3 The diagram shows a method for fabricating a semiconductor power device according to the present invention, based on a first photomask forming a first trench and a second trench spaced apart in a substrate.

[0034] Figure 4 The diagram shown illustrates the deposition of a doped layer in the method for fabricating the semiconductor power device of the present invention.

[0035] Figure 5 The diagram shows a method for fabricating a semiconductor power device according to the present invention, specifically a method for etching back the doped layer.

[0036] Figure 6 The diagram illustrates a method for fabricating a semiconductor power device according to the present invention, in which a second conductivity type dopant is diffused in a doped layer through heat treatment to form a heavily doped region of the second conductivity type in a well region of the second conductivity type around a second trench.

[0037] Figure 7 The diagram shown illustrates the deposition of a gate conductive layer in a method for fabricating a semiconductor power device according to the present invention.

[0038] Figure 8 The diagram shows a method for fabricating a semiconductor power device according to the present invention, in which a first conductivity type heavily doped region is formed on both sides of a first trench by ion implantation self-alignment.

[0039] Figure 9 The diagram shows a method for fabricating a semiconductor power device according to the present invention, comprising an interlayer dielectric layer, contact holes, a conductor layer, and a passivation layer.

[0040] Component designation explanation

[0041] Steps S1 to S10

[0042] 1 Substrate

[0043] 2. Second type of conductivity well region

[0044] 3 First trench

[0045] 4 Second trench

[0046] 5 Hard mask layer

[0047] 6 First opening

[0048] 7 Second opening

[0049] 8 Doped layer

[0050] 9. Heavy doped region of the second conductivity type

[0051] 10 Gate dielectric layer

[0052] 11 Gate conductive layer

[0053] 12 Heavy doped region of first conductivity type

[0054] 13 Interlayer dielectric layer

[0055] 14 Contact Holes

[0056] 15 Conductor Layer

[0057] 16 Passivation layer

[0058] 17. Contact opening Detailed Implementation

[0059] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] Please see Figures 1 to 9It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] This embodiment provides a method for fabricating a semiconductor power device. Please refer to [link to relevant documentation]. Figure 1 The diagram shows the process flow of this method, which includes the following steps:

[0062] S1: Provide a substrate of a first conductivity type, and form a well region of a second conductivity type in the substrate;

[0063] S2: Based on the first photomask, a first trench and a second trench are formed in the substrate at intervals. The first trench and the second trench open from the front side of the substrate and extend towards the back side of the substrate. The bottom surface of the first trench is lower than the bottom surface of the second conductivity type well region, the bottom surface of the second trench is higher than the bottom surface of the first trench, and the width of the first trench is greater than the width of the second trench.

[0064] S3: Form a doped layer containing a second type of conductivity dopant in the second trench, and heat-treat to diffuse the second type of conductivity dopant in the doped layer to form a heavily doped region of the second type of conductivity around the second trench;

[0065] S4: A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the substrate, and the gate dielectric layer and the gate conductive layer are sequentially filled into the first trench;

[0066] S5: Pattern the portion of the gate conductive layer located on the substrate based on the second photomask;

[0067] S6: A heavily doped region of the first conductivity type is formed on both sides of the first trench by ion implantation self-alignment;

[0068] S7: Form an interlayer dielectric layer above the substrate;

[0069] S8: Pattern the interlayer dielectric layer based on the third photomask to form a contact hole, the contact hole being located above the second trench and exposing the first conductivity type heavily doped region and the second conductivity type heavily doped region;

[0070] S9: A conductor layer is formed on the surface of the interlayer dielectric layer, and the conductor layer fills the contact hole;

[0071] S10: Pattern the conductor layer based on the fourth photomask to obtain the lead structure.

[0072] As an example, the first conductivity type can be N-type or P-type, and correspondingly, the second conductivity type can be P-type or N-type.

[0073] As an example, the method for fabricating the semiconductor power device can be used to fabricate one of the following: silicon insulated gate bipolar transistors (Si-IGBT), silicon carbide insulated gate bipolar transistors (SiC-IGBT), double-diffused metal-oxide-semiconductor field-effect transistors (D-MOSFET), and silicon carbide metal-oxide-semiconductor field-effect transistors (SiC-MOSFET). Among them, the IGBT is a three-terminal power electronic device with a gate, collector, and emitter. It has an additional P-type injection region (located between the drain and drain region of the MOSFET) compared to an N-channel MOSFET, thus forming a larger PN junction. This allows minority carriers to be emitted from the P-type injection region to the N-type drift region when the IGBT is turned on, thereby modulating the conductivity of the drift region and giving the IGBT a strong current-carrying capacity.

[0074] As an example, such as Figure 2 As shown, step S1 is performed: a first conductivity type substrate 1 is provided, and a second conductivity type well region 2 is formed in the substrate 1. Depending on the type of device to be fabricated, the substrate 1 can be a silicon substrate or a silicon carbide substrate, and the conductivity type of the substrate can be P-type or N-type. In this embodiment, the substrate 1 is an N-type lightly doped Si substrate, and a P-type well region is formed by boron ion implantation and high-temperature push-junction on the front side of the substrate 1.

[0075] It should be noted that the terms light doping, doping, and heavy doping in this invention are relative concepts, and the doping concentration satisfies the condition that light doping < heavy doping < heavy doping. The specific doping concentration can be adjusted as needed.

[0076] As an example, such as Figure 3 As shown, step S2 is performed: a first trench 3 and a second trench 4 are formed in the substrate 1 based on the first photomask. The first trench 3 and the second trench 4 open from the front side of the substrate 1 and extend towards the back side of the substrate 1. The bottom surface of the first trench 3 is lower than the bottom surface of the second conductive type well region 2, and the bottom surface of the second trench 4 is higher than the bottom surface of the first trench 3. The width of the first trench 3 is greater than the width of the second trench 4.

[0077] Specifically, in this embodiment, step S2 includes the following specific process flow:

[0078] Step S2-1: Form a hard mask layer 5 on the substrate 1. The hard mask layer 5 may be made of silicon oxide or other suitable materials.

[0079] Step S2-2: Based on the first photomask, the hard mask layer 5 is patterned using photolithography and etching processes to form a first opening 6 and a second opening 7 in the hard mask layer 5. The width of the first opening 6 is greater than the width of the second opening 7. For example, the width of the first opening 6 can be 1.3 micrometers and the width of the second opening can be 0.3 micrometers.

[0080] Step S2-3: The substrate 1 is etched through the first opening 6 and the second opening 7 to obtain the first trench 3 and the second trench 4 with different depths by utilizing the etching loading effect. The etching loading effect refers to the effect of the local consumption of etching gas being greater than the supply, which causes a decrease in etching rate or uneven distribution.

[0081] As an example, such as Figures 4-6 As shown, step S3 is performed: a doped layer 8 containing a second conductivity type dopant is formed in the second trench 4, and a heat treatment is performed to diffuse the second conductivity type dopant in the doped layer 8 to form a second conductivity type heavily doped region 9 around the second trench 4.

[0082] Specifically, such as Figure 4 As shown, the hard mask layer 5 is removed, and the doped layer 8 is deposited on the surface of the substrate 1. The doped layer 8 fills the first trench 3 and the second trench 4, and the doped layer 8 completely fills the second trench 4 but does not completely fill the first trench 3. In this embodiment, the doped layer 8 is a borosilicate glass oxide layer as an example.

[0083] Specifically, since the widths of the first trench 3 and the second trench 4 are different, the narrow second trench 4 is easily filled by the doped layer 8. In this embodiment, the thickness of the deposited doped layer 8 is taken as 0.15 micrometers to 0.25 micrometers. Finally, a thin doped layer 8 is deposited on the sidewall of the wide first trench 3, while the narrow second trench 4 is filled by the doped layer 8.

[0084] Specifically, such as Figure 5 As shown, wet etching is used to etch back the doped layer 8 to remove the doped layer 8 on the surface of the substrate 1. The etching solution used in the wet etching can be BOE (buffered oxide etchant) or DHF (dilute hydrofluoric acid). In this embodiment, when the portion of the doped layer 8 located in the first trench 3 and on the substrate 1 is completely removed, the portion of the doped layer 8 located in the second trench 4 is still completely or mostly retained.

[0085] Specifically, such as Figure 6As shown, a second conductivity type dopant in the doped layer 8 is diffused through heat treatment to form a second conductivity type heavily doped region 9 in the second conductivity type well region 2 surrounding the second trench 4. The presence of the second conductivity type heavily doped region 9 can reduce the bulk resistance of the second conductivity type well region 2. For IGBT devices, the presence of the second conductivity type heavily doped region 9 increases the emitter contact area, which helps to reduce the IGBT's turn-on voltage. Simultaneously, by controlling the outward diffusion of P-type impurities in the doped layer 8 within the second trench 4, the P-type heavily doped region can be made as close as possible to the first trench 3 (used to fabricate the trench gate structure) without affecting the threshold voltage of the N-channel MOSFET. Thus, the P-type heavily doped region in the P-type well region can effectively reduce the base resistance (R0) of the NPN parasitic bipolar transistor. B This increases the latch-up current of the device and expands the safe operating area of ​​the IGBT.

[0086] As an example, such as Figure 6 and Figure 7 As shown, step S4 is performed: a gate dielectric layer 10 and a gate conductive layer 11 are sequentially formed on the surface of the substrate 1, and the gate dielectric layer 10 and the gate conductive layer 11 are sequentially filled into the first trench 3.

[0087] Specifically, such as Figure 6 As shown, in this embodiment, the gate dielectric layer 10 is formed by thermal growth. The heating process in step S3, which diffuses the second conductivity type dopant in the doped layer 8 to form the second conductivity type heavily doped region 9, may include the heating process during the formation of the gate dielectric layer 10. That is, parts of step S3 and step S4 can be performed simultaneously. In this embodiment, a 2000 angstrom thick silicon oxide layer is used as the gate dielectric layer 10 through furnace tube thermal growth. During the thermal growth process of the gate dielectric layer 10, B ions in the doped layer 8 diffuse into Si, forming a P-type heavily doped region.

[0088] Specifically, such as Figure 7 As shown, a gate conductive layer 11 is deposited. In this embodiment, a polycrystalline silicon layer with a thickness of 1 micrometer to 2 micrometers is deposited as the gate conductive layer.

[0089] As an example, continue as follows Figure 7 As shown, step S5 is performed: patterning the portion of the gate conductive layer 11 located on the substrate 1 based on the second photomask.

[0090] Specifically, the gate conductive layer 11 is patterned using photolithography and etching processes based on the second photomask. In this embodiment, polysilicon interconnects and polysilicon field plates are formed during the patterning of the polysilicon gate conductive layer, and a heavily doped region of the first conductivity type is defined. The patterned gate conductive layer constitutes a self-aligned mask for subsequent ion implantation of the second conductivity type.

[0091] As an example, such as Figure 8 As shown, step S6 is performed: a heavily doped region 12 of the first conductivity type is formed on both sides of the first trench 3 by ion implantation self-alignment. In this embodiment, an N-type heavily doped region is formed by implanting As ions to serve as the emitter of the IGBT (the source of the N-channel MOSFET). Since the gate conductive layer 11 constitutes a self-aligned mask, no additional photomask is required to form the N-type heavily doped region by ion implantation.

[0092] As an example, before forming the first conductivity type heavily doped region 12 by ion implantation self-alignment, the front side of the substrate 1 can be implanted with a second conductivity type again as needed to adjust the concentration of the second conductivity type well region 2, and this ion implantation does not require an additional photomask.

[0093] As an example, such as Figure 9 As shown, steps S7-S10 are performed as follows: an interlayer dielectric layer 13 is formed above the substrate 1; the interlayer dielectric layer 13 is patterned using photolithography and etching processes based on a third photomask to form a contact hole 14; the contact hole 14 is located above the second trench 4 and exposes the first conductivity type heavily doped region 12 and the second conductivity type heavily doped region 9; a conductor layer 15 is formed on the surface of the interlayer dielectric layer 13; the conductor layer 15 fills the contact hole 14; and the conductor layer 15 is patterned using photolithography and etching processes based on a fourth photomask to obtain a lead structure.

[0094] Specifically, in this embodiment, the contact hole 14 is located directly above the second trench 4, and the opening area of ​​the contact hole 14 is larger than the opening area of ​​the second trench 4 to expose the emitter of the IGBT (the source of the N-channel MOSFET and the collector of the PNP bipolar transistor), so that the subsequently deposited conductor layer 15 covers the heavily doped P-type and heavily doped N-type regions around the second trench 4, forming a good ohmic contact. The conductor layer 15 can be made of a 4-micrometer-thick aluminum-copper alloy or other conductive materials of suitable thickness and material.

[0095] As an example, such as Figure 9As shown, in this embodiment, a passivation layer 16 is further formed on the surface of the conductor layer 15, and the passivation layer 15 is patterned using photolithography and etching processes based on a fifth photomask to obtain a contact opening 17. The passivation layer 15 may be a silicon oxide / silicon nitride stack structure or other suitable materials, and the contact opening 17 exposes the conductor layer 15 to serve as an interface for a gate pad or an emitter bonding pad.

[0096] As an example, an electrode layer (not shown) can be further formed on the back side of the substrate 1 using conventional processes to serve as the collector electrode of the IGBT or the drain electrode of the MOSFET.

[0097] Thus, a semiconductor power device is fabricated. The fabrication method of the semiconductor power device in this embodiment only requires four photomasks (excluding passivation layers): trench, gate conductive layer, contact hole, and conductive interconnect. It is applicable to silicon insulated gate bipolar transistor (Si-IGBT), silicon carbide insulated gate bipolar transistor (SiC-IGBT), double diffused metal oxide semiconductor field-effect transistor (D-MOSFET), and silicon carbide MOSFET (SiC-MOSFET).

[0098] In summary, the semiconductor power device fabrication method of this invention has a simple process. By sharing a photomask, it reduces the number of core photomasks from the current mainstream 5-7 layers to 4 layers. Compared with conventional semiconductor power device manufacturing processes, this invention eliminates the need for two photomasks for the P-type heavily doped region and the N-type heavily doped region. Furthermore, this invention defines a first trench and a second trench with different widths using the same photomask (the first photomask), eliminating the need for an additional photomask to form the second trench, thereby significantly reducing process costs and improving yield. In this invention, the narrower width of the second trench makes it easier to be filled by the doped layer. The second conductivity type dopant in the doped layer diffuses outward to form a second conductivity type heavily doped region in the second conductivity type well region surrounding the second trench. This provides ohmic contact for the IGBT emitter region or the MOSFET source region and reduces the bulk resistance of the second conductivity type well region, helping to prevent latch-up triggering. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of fabricating a semiconductor power device, characterized by, The method comprises the following steps: providing a substrate of a first conductivity type, and forming a well region of a second conductivity type in the substrate; forming first and second trenches in the substrate based on a first mask, the first and second trenches being spaced apart, and the first and second trenches being open at a front surface of the substrate and extending toward a back surface of the substrate, a bottom surface of the first trench being lower than a bottom surface of the well region of the second conductivity type, and a bottom surface of the second trench being higher than the bottom surface of the first trench, and a width of the first trench being greater than a width of the second trench; forming a doped layer containing dopants of the second conductivity type in the second trench, and performing a heat treatment to diffuse the dopants of the second conductivity type in the doped layer to form a heavily doped region of the second conductivity type around the second trench; sequentially forming a gate dielectric layer and a gate conductive layer on a surface of the substrate, the gate dielectric layer and the gate conductive layer being sequentially filled into the first trench; patterning a portion of the gate conductive layer on the substrate based on a second mask; forming a heavily doped region of a first conductivity type on both sides of the first trench by ion implantation self-alignment; forming an interlayer dielectric layer above the substrate; patterning the interlayer dielectric layer based on a third mask to form a contact hole, the contact hole being above the second trench and exposing the heavily doped region of the first conductivity type and the heavily doped region of the second conductivity type; forming a conductor layer on a surface of the interlayer dielectric layer, the conductor layer being filled into the contact hole; patterning the conductor layer based on a fourth mask to obtain a lead structure.

2. The method of fabricating a semiconductor power device of claim 1, wherein: The semiconductor power device comprises one of a silicon insulated gate bipolar transistor, a silicon carbide insulated gate bipolar transistor, a double-diffused metal oxide semiconductor field effect transistor, and a silicon carbide metal oxide semiconductor field effect transistor.

3. The method of fabricating a semiconductor power device of claim 1, wherein: The first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.

4. The method of fabricating a semiconductor power device of claim 3, wherein: The first conductivity type is N-type, the second conductivity type is P-type, and the doped layer comprises a borosilicate glass oxide layer.

5. The method of claim 1, wherein: The method of forming the first and second trenches in the substrate based on the first mask comprises the following steps: forming a hard mask layer on the substrate; patterning the hard mask layer based on the first mask to form a first opening and a second opening in the hard mask layer, a width of the first opening being greater than a width of the second opening; etching the substrate through the first and second openings to obtain the first and second trenches with different depths by using etching loading effects.

6. The method of fabricating a semiconductor power device of claim 1, wherein: The method of forming the doped layer in the second trench comprises the following steps: depositing the doped layer on a surface of the substrate, the doped layer being filled into the first and second trenches, and the doped layer being filled into the second trench but not being filled into the first trench; performing a back etching on the doped layer, when portions of the doped layer on the first trench and on the substrate are removed, portions of the doped layer in the second trench are still completely retained or mostly retained.

7. The method of fabricating a semiconductor power device of claim 1, wherein: The heating process for forming the gate dielectric layer includes a heating process for forming the gate dielectric layer.

8. The method of fabricating a semiconductor power device according to claim 1, wherein Further comprising the following steps: forming a passivation layer on the surface of the conductor layer, and patterning the passivation layer based on a fifth mask to obtain a contact opening.

9. The method of fabricating a semiconductor power device according to claim 1, wherein Further comprising the following steps: forming an electrode layer on the back surface of the substrate.

10. A semiconductor power device, characterized by: The semiconductor power device is manufactured by the method for manufacturing a semiconductor power device according to any one of claims 1-9.

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