Sampling circuit and DC-DC converter

Abstract

The present application is applicable to the technical field of DC-DC converters, and provides a sampling circuit and a DC-DC converter, wherein the sampling circuit comprises n first switching tubes connected in series and n-1 discharge units. A common node exists between any two adjacent first switching tubes, and the input end of the discharge unit is electrically connected to the common node. When the first switching tube is in the off state, the voltage at the common node is still the voltage when the first switching tube is in the on state. The discharge unit in the embodiment of the present application can lower the voltage at the common node between two adjacent first switching tubes, so that the difference between the voltage value at the common node and the gate voltage of the switching tube is less than the withstand voltage value between the source and gate of the first switching tube, preventing the difference between the voltage value at the common node and the gate voltage of the switching tube from being greater than the withstand voltage value between the source and gate of the first switching tube, causing damage to the first switching tube, thereby improving the reliability of the sampling circuit.

Description

Technical Field

[0001] The present application belongs to the technical field of DC-DC converters, and in particular relates to a sampling circuit and a DC-DC converter. Background Art

[0002] A DC-DC converter is a device that converts a fixed DC voltage into a variable DC voltage. The sampling circuit in a traditional DC-DC converter includes multiple switching transistors connected in series. Due to the high input power voltage, when all the switching transistors are off, the difference between the node voltage at the common node of two adjacent switching transistors and the gate voltage of the switching transistors exceeds the withstand voltage between the source and gate of the sampling circuit. This can damage the switching transistors and lead to poor reliability of the sampling circuit. Summary of the Invention

[0003] Embodiments of the present application provide a sampling circuit and a DC-DC converter, which can solve the problem in existing sampling circuits where, when a switch tube in the sampling circuit is in the off state, the difference between the node voltage at the common node of two adjacent switch tubes and the switch tube gate voltage is greater than the withstand voltage between the source and gate of the switch tube in the sampling circuit, thereby damaging the switch tube in the sampling circuit and causing poor reliability of the sampling circuit.

[0004] In a first aspect, an embodiment of the present application provides a sampling circuit, comprising n first switching tubes connected in series and n-1 discharge units, wherein the common node of any two adjacent first switching tubes is connected to one discharge unit, and the discharge unit is used to lower the voltage of the common node when the first switching tube is in the disconnected state; wherein n is an integer greater than 1.

[0005] In a possible implementation of the first aspect, the discharge unit includes a second switching tube, wherein the drain and gate of the second switching tube are electrically connected to corresponding common nodes, and the source of the second switching tube is electrically connected to a voltage node; when the first switching tube is in an off state, the voltage value of the voltage node is a first voltage, and the voltage drop of the second switching tube when it is turned on is less than the withstand voltage value between the source and gate of the first switching tube.

[0006] In a possible implementation manner of the first aspect, the voltage node is electrically connected to the gate of the first switching tube.

[0007] In a possible implementation of the first aspect, the second switch tube is an N-type MOS tube.

[0008] In a possible implementation of the first aspect, the source of the ath first switching transistor is electrically connected to the drain of the a+1th first switching transistor, where a is a positive integer and 1≤a<n.

[0009] In a second aspect, an embodiment of the present application provides a DC-DC converter, comprising a comparison module, a conversion module, and the sampling circuit according to any one of the first aspects, wherein the conversion module is used to convert the error amplified voltage signal output by the DC-DC converter into a sampling current signal, the comparison module is used to compare the first sampling voltage signal with the switch node voltage signal and output a modulation signal, the DC-DC converter is used to adjust the switch node voltage signal according to the modulation signal and the input voltage signal output by the input power supply, the sampling circuit comprises n first switching tubes connected in series and n-1 discharge units, the drain of the first first switching tube is electrically connected to the input power supply, the source of the nth first switching tube is electrically connected to the conversion module, and the common node of any two adjacent first switching tubes is connected to one discharge unit, the discharge unit being used to lower the voltage of the common node when the first switching tube is in the off state; wherein n is an integer greater than 1.

[0010] In a possible implementation of the second aspect, the DC-DC converter further includes an isolation unit and a pull-up unit;

[0011] The isolation unit is connected in series between the sampling circuit and the conversion module, and is further configured to output a second sampling voltage signal to the conversion module according to the first sampling voltage signal and the modulation signal;

[0012] The pull-up unit is connected in series between the input power supply and the conversion module, and is further used to output a preset voltage to the conversion module according to the input voltage signal when the sampling circuit does not output the first sampling voltage signal.

[0013] In a possible implementation of the second aspect, the isolation unit includes b third switching tubes connected in series, the source of the first third switching tube is electrically connected to the source of the nth first switching tube, the drain of the bth third switching tube is electrically connected to the conversion module, and the gates of all the third switching tubes receive the modulation signal, where b is a positive integer.

[0014] In a possible implementation of the second aspect, the discharge unit includes c fourth switching tubes connected in series, the source of the first fourth switching tube is electrically connected to the input power supply, the drain of the cth fourth switching tube is electrically connected to the conversion module, and the gate of each fourth switching tube is electrically connected to its respective drain, where c is a positive integer.

[0015] In a possible implementation manner of the second aspect, all the third switching transistors are N-type MOS transistors, and all the fourth switching transistors are P-type MOS transistors.

[0016] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0017] The sampling circuit provided in an embodiment of the present application includes n first switching tubes connected in series and n-1 discharge units. A common node exists between any two adjacent first switching tubes, and the input end of the discharge unit is electrically connected to the common node. When the first switching tube is in the off state, the voltage at the common node remains the voltage when the first switching tube is in the on state. The discharge unit in the embodiment of the present application can lower the voltage at the common node between two adjacent first switching tubes so that the difference between the voltage at the common node and the gate voltage of the first switching tube is less than the withstand voltage between the source and gate of the first switching tube, thereby preventing the difference between the voltage at the common node and the gate voltage of the first switching tube from exceeding the withstand voltage between the source and gate of the first switching tube, thereby preventing damage to the first switching tube. This improves the reliability of the sampling circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 is a circuit schematic diagram of a sampling circuit provided in one embodiment of the present application;

[0020] Figure 2 This is a principle block diagram of a DC-DC converter provided by an embodiment of the present application;

[0021] Figure 3 is a principle block diagram of a DC-DC converter provided by another embodiment of the present application;

[0022] Figure 4 This is a circuit diagram of a DC-DC converter provided in one embodiment of the present application.

[0023] In the figure: 10, discharge unit; 20, isolation unit; 30, pull-up unit; 40, comparison module; 50, conversion module; 60, input power supply; 01, sampling circuit. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0025] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0026] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0027] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0028] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0030] The sampling circuit in a traditional DC-DC converter includes multiple switching tubes connected in series. Due to the high voltage of the input power supply, when all the switching tubes are in the off state, the difference between the node voltage at the common node of two adjacent switching tubes and the gate voltage of the switching tubes is greater than the withstand voltage value between the source and gate of the switching tubes in the sampling circuit. This will damage the switching tubes in the sampling circuit and lead to poor reliability of the sampling circuit.

[0031] Based on the above problems, the sampling circuit provided in an embodiment of the present application includes n first switching tubes connected in series and n-1 discharge units. A common node exists between any two adjacent first switching tubes, and the input end of the discharge unit is electrically connected to the common node. When the first switching tube is in the off state, the voltage at the common node remains the voltage when the first switching tube is in the on state. The discharge unit in the embodiment of the present application can lower the voltage at the common node between two adjacent first switching tubes when the first switching tube is in the off state, so that the difference between the voltage at the common node and the gate voltage of the first switching tube is less than the withstand voltage between the source and gate of the first switching tube, thereby preventing the difference between the voltage at the common node and the gate voltage of the first switching tube from exceeding the withstand voltage between the source and gate of the first switching tube, which may cause damage to the first switching tube, thereby improving the reliability of the sampling circuit.

[0032] In order to illustrate the technical solution described in this application, specific embodiments are provided below.

[0033] Figure 1 FIG1 shows a circuit schematic diagram of a sampling circuit 01 provided in an embodiment of the present application. Figure 1 As shown, it includes n first switching tubes connected in series and n-1 discharge units 10. The common node of any two adjacent first switching tubes is connected to a discharge unit 10. The discharge unit 10 is used to lower the voltage of the common node when the first switching tube is in the off state; wherein n is an integer greater than 1.

[0034] Specifically, the sampling circuit 01 includes n first switching tubes connected in series and n-1 discharge units 10. A common node exists between any two adjacent first switching tubes, and the input end of the discharge unit 10 is electrically connected to the common node. When the first switching tube is in the off state, the voltage at the common node remains the input voltage when the first switching tube is in the on state. The discharge unit 10 in the embodiment of the present application can lower the voltage at the common node between two adjacent first switching tubes when the first switching tube is in the off state, so that the difference between the voltage at the common node and the gate voltage of the first switching tube is less than the withstand voltage between the source and gate of the first switching tube. This prevents the difference between the voltage at the common node and the gate voltage of the first switching tube from exceeding the withstand voltage between the source and gate of the first switching tube, which could damage the first switching tube, thereby improving the reliability of the sampling circuit 01.

[0035] For example, the withstand voltage between the source and gate of the first switch is set to 5V. When the first switch is in the on state, the voltage at the common node between any two adjacent first switches is equal to or approximately equal to the voltage of the input voltage signal Vin. When the voltage of the input voltage signal Vin is 50V, the voltage at the common node between any two adjacent first switches is approximately 50V. When the first switch is in the off state, the voltage at the common node between any two adjacent first switches remains at the original potential (approximately 50V). At this time, the voltage at the common node is much higher than the withstand voltage between the source and gate of the first switch, which may cause damage to the first switch. The input end of the discharge unit 10 in the embodiment of the present application is electrically connected to the common node, and is used to lower the voltage of the common node when the first switch is in the off state, that is, to lower the voltage of the common node from 50V, so that the voltage at the common node is lower than the withstand voltage between the source and gate of the first switch (5V), thereby protecting the first switch from damage and improving the reliability of the sampling circuit 01.

[0036] For example, when the value of n is 3, Figure 1As shown, sampling circuit 01 includes three first switching transistors connected in series and two discharge units 10. M11, M12, and M13 are all first switching transistors. The common node between M11 and M12 is connected to one discharge unit 10, and the common node between M12 and M13 is connected to one discharge unit 10. When M11, M12, and M13 are all in the on state, the voltage value at the common node between M11 and M12 is equal to or approximately equal to the voltage value of the input voltage signal Vin, and the voltage value at the common node between M12 and M13 is equal to or approximately equal to the voltage value of the input voltage signal Vin. When the voltage value of the input voltage signal Vin is 50V, the voltage value at the common node between M11 and M12 and the voltage value at the common node between M12 and M13 are approximately 50V. When M11, M12, and M13 are all disconnected, the voltage at the common node between M11 and M12 and the voltage at the common node between M12 and M13 remain at their original potential (approximately 50V). At this point, the voltage at the common node between M11 and M12 is much greater than the withstand voltage between the source and gate of M11 (5V), which can damage M11. Simultaneously, the voltage at the common node between M12 and M13 is much greater than the withstand voltage between the source and gate of M12 (5V), which can damage M12. However, the connection of a discharge unit 10 to the common node between M11 and M12 pulls down the voltage of the common node between M11 and M12 by 50V, thereby reducing the voltage at the common node to less than the withstand voltage between the source and gate of M11 (5V), protecting M11 from damage. At the same time, the common node between M12 and M13 is connected to a discharge unit 10, which will lower the voltage of the common node between M12 and M13 by 50V, so that the voltage value at the common node is lower than the withstand voltage value (5V) between the source and gate of M12, protecting M12 from damage, thereby improving the reliability of the sampling circuit 01.

[0037] In one embodiment of the present application, the discharge unit 10 includes a second switch tube, the drain and gate of the second switch tube are both connected to the corresponding common node, and the source of the second switch tube is electrically connected to the voltage node A; when the first switch tube is in the off state, the voltage value of the voltage node A is the first voltage, and the voltage drop when the second switch tube is turned on is less than the withstand voltage value between the source and gate of the first switch tube.

[0038] Specifically, the gate and drain of the second switching transistor are electrically connected. In this case, each of the second switching transistors functions as a diode, with the anode of the diode electrically connected to the common node and the cathode of the diode electrically connected to voltage node A. When the first switching transistor is off, the voltage at the common node remains the voltage input when the first switching transistor is on. At this time, the voltage at the common node is much greater than the voltage at voltage node A, i.e., the voltage at the common node is much greater than the first voltage. The difference between the voltage at the common node and the first voltage is greater than the turn-on voltage of the second switching transistor. When the second switching transistor is turned on, the voltage at the common node is pulled down to the gate voltage of the first switching transistor. When the voltage drop when the second switching transistor is on is less than the withstand voltage between the source and gate of the first switching transistor, damage to the first switching transistor is prevented, thereby improving the reliability of sampling circuit 01.

[0039] For example, Figure 1 As shown, M21 and M22 are both second switching transistors. When the voltage value of the input voltage signal Vin is 10V, when M11 and M12 are in the disconnected state, the voltage value at the common node between M11 and M12 is equal to or approximately equal to the voltage value of the input voltage signal Vin, that is, the voltage value at the common node is approximately 10V. Assuming that the withstand voltage value between the source and gate of M11 is 5V, only by ensuring that the voltage drop when M21 is turned on is less than the withstand voltage value (5V) between the source and gate of the first switching transistor can M11 be protected from damage. For example, the first voltage can be 4V, and the voltage drop when the second switching transistor is turned on is 0.7V. This ensures that the voltage drop when the second switching transistor is turned on is less than the withstand voltage value (5V) between the source and gate of the first switching transistor, thereby preventing damage to the first switching transistor and improving the reliability of the sampling circuit 01.

[0040] It should be noted that the second switching transistors are all N-type MOS transistors. Selecting N-type MOS transistors ensures that the drains of M21 and M22 are electrically connected to the common node. The drains of M21 and M22 have high-voltage resistance, which prevents damage to M21 and M22 when the first switching transistor outputs a preset high voltage, thereby improving the reliability of sampling circuit 01. Furthermore, the gate and drain of the N-type MOS transistors are electrically connected, equivalent to a diode conducting from left to right, with the anode of the diode electrically connected to the common node and the cathode of the diode electrically connected to voltage node A. A diode is not used directly because the input voltage signal Vin output by the input power supply 60 received by the first switching transistor is a high-voltage signal and outputs this high-voltage signal to the discharge unit 10. Since diodes do not have strong high-voltage resistance, they may be damaged. High-voltage N-type MOS transistors have strong high-voltage resistance and can receive the high-voltage signal output by the first switching transistor, thereby improving the reliability of sampling circuit 01.

[0041] In one embodiment of the present application, the voltage node A is electrically connected to the gate of the first switching tube.

[0042] In addition to including a single second switching transistor, the discharge unit 10 may also include multiple second switching transistors connected in series. The number of second switching transistors in the discharge unit 10 can be set based on actual needs and is not limited here. Furthermore, in addition to being constructed using second switching transistors, the discharge unit 10 may also be constructed using other circuits with unidirectional conduction capability, which is not limited here.

[0043] Specifically, the voltage node A is electrically connected to the gate of the first switching tube, wherein the voltage value of the voltage node A is a first voltage, that is, the input voltage signal of the gate of the first switching tube changes according to the change of the first voltage, that is, the first voltage can be used as the input voltage signal of the gate of the first switching tube, wherein the first voltage and the input voltage signal of the gate of the first switching tube can be equal or unequal.

[0044] In one embodiment of the present application, the source of the ath first switching transistor is electrically connected to the drain of the a+1th first switching transistor, where a is a positive integer and 1≤a<n.

[0045] Specifically, such as Figure 1 As shown, the source of the ath first switching transistor is electrically connected to the drain of the a+1th first switching transistor, and all first switching transistors are connected in series. If a=1, the drain of the ath first switching transistor is electrically connected to the input power supply 60, for receiving the input voltage signal Vin output by the input power supply 60. If a>1, the drain of the ath first switching transistor is electrically connected to the source of the a-1th first switching transistor, for receiving the voltage signal output by the source of the a-1th first switching transistor, and the drain of the a+1th first switching transistor is electrically connected to the source of the ath first switching transistor, for receiving the voltage signal output by the source of the ath first switching transistor.

[0046] Exemplarily, when the value of a is 2, the drain of the second first switch tube M12 is electrically connected to the source of the first first switch tube M11, for receiving the voltage signal output by the source of the first first switch tube M11, and the drain of the third first switch tube M13 is electrically connected to the source of the second first switch tube M12, for receiving the voltage signal output by the source of the second first switch tube M12.

[0047] It should be noted that if Figure 3 As shown, the value of n is 3, and the value of a is 2. At this time, the source and drain of M12 can be interchanged, that is, the source of M12 is electrically connected to the source of M11 to receive the voltage signal output by the source of M11, and the drain of M13 is electrically connected to the drain of M12 to receive the voltage signal output by the drain of M12.

[0048] Figure 2 The schematic diagram of the DC-DC converter provided by one embodiment of the present application is shown. Figure 2 As shown, the DC-DC converter includes a comparison module 40, a conversion module 50 and a sampling circuit 01. The conversion module 50 is used to convert the error amplified voltage signal output by the DC-DC converter into a sampling current signal. The comparison module 40 is used to compare the first sampling voltage signal with the switch node voltage signal and output a modulation signal. The DC-DC converter is used to adjust the switch node voltage signal according to the modulation signal and the input voltage signal output by the input power supply 60. The sampling circuit 01 includes n first switching tubes connected in series and n-1 discharge units 10. The drain of the first first switching tube is electrically connected to the input power supply 60, and the source of the nth first switching tube is electrically connected to the conversion module 50. The common node of any two adjacent first switching tubes is connected to a discharge unit 10. The discharge unit 10 is used to lower the voltage of the common node when the first switching tube is in the off state; wherein n is an integer greater than 1.

[0049] Specifically, the modulation signal can be a PWM signal. The sampling circuit 01 outputs a first sampled voltage signal Vsen1 to the comparison module 40 based on the input PWM signal and the input voltage signal Vin. The comparison module 40 outputs a PWM signal based on the input first sampled voltage signal Vsen1 and the switch node voltage signal Vsw. Simultaneously, the sampling circuit 01 also outputs a second sampled voltage signal Vsen2 to the conversion module 50. The conversion module 50 converts the input error amplified voltage signal Verr into a sampled current signal. The DC-DC converter adjusts the switch node voltage signal Vsw based on the PWM signal and the input voltage signal Vin.

[0050] For example, to facilitate illustration of the entire process of regulating the switching node voltage signal Vsw by the DC-DC converter, the current regulation cycle can be set, with the switching node voltage signal Vsw being defined as the first switching node voltage signal Vsw1. After the DC-DC converter regulates the first switching node voltage signal Vsw1 based on the PWM signal and the input voltage signal Vin, the signal output by the switching node is defined as the second switching node voltage signal Vsw2. It will be appreciated that after outputting the second switching node voltage signal Vsw2, in the next regulation cycle, the second switching node voltage signal Vsw2 is used as the first switching node voltage signal Vsw1, and the aforementioned process is repeated.

[0051] In one embodiment of the present application, Figure 3 As shown, the DC-DC converter further includes an isolation unit 20 and a pull-up unit 30;

[0052] The isolation unit 20 is connected in series between the sampling circuit 01 and the conversion module 50, and is further used to output a second sampling voltage signal to the conversion module 50 according to the first sampling voltage signal and the modulation signal;

[0053] The pull-up unit 30 is connected in series between the input power supply 60 and the conversion module 50 , and is further configured to output a preset voltage to the conversion module 50 according to the input voltage signal when the sampling circuit 01 does not output the first sampling voltage signal.

[0054] Specifically, the sampling circuit 01 is connected in series between the input power supply 60 and the comparison module 40. It is configured to output a first sampled voltage signal Vsen1 to the comparison module 40 and the isolation unit 20 based on the modulation signal and the input voltage signal Vin. The isolation unit 20 is configured to output a second sampled voltage signal Vsen2 to the conversion module 50 based on the first sampled voltage signal Vsen1 and the modulation signal. The comparison module 40 is configured to compare the first sampled signal with the switch node voltage signal Vsw and output the modulation signal. When the modulation signal output by the comparison module 40 is low, the sampling circuit 01 is unable to output the first sampled voltage signal Vsen1 to the isolation unit 20 based on the modulation signal and the input voltage signal Vin. Simultaneously, the isolation unit 20 is unable to output the second sampled voltage signal Vsen2 to the conversion module 50 based on the first sampled voltage signal Vsen1 and the modulation signal. At this time, the pull-up unit 30 connected in series between the input power supply 60 and the conversion module 50 is triggered. When the sampling circuit 01 does not output the first sampling voltage signal Vsen1, the pull-up unit 30 outputs a preset voltage to the conversion module 50, so that the current mirror in the conversion module 50 is always in the saturation region. When the modulation signal output by the comparison module 40 is a high level, the sampling circuit 01 can output the first sampling voltage signal Vsen1 to the isolation unit 20 based on the modulation signal and the input voltage signal Vin. At the same time, the isolation unit 20 can also output the second sampling voltage signal Vsen2 to the conversion module 50 based on the first sampling voltage signal Vsen1 and the modulation signal. At this time, the input voltage of the conversion module 50 increases from the preset voltage to the second sampling voltage signal Vsen2, thereby improving the establishment speed and accuracy of the second sampling voltage.

[0055] In one embodiment of the present application, the isolation unit 20 includes b third switching tubes connected in series in sequence, the source of the first third switching tube is electrically connected to the source of the nth first switching tube, the drain of the bth third switching tube is electrically connected to the conversion module 50, and the gates of all third switching tubes receive the modulation signal, where b is a positive integer.

[0056] Specifically, the switches in the isolation unit 20 are all defined as third switches, and each third switch is connected in series. The source of the first third switch is electrically connected to the source of the nth first switch and serves as the input of the isolation unit 20, receiving the first sampled voltage signal Vsen1 output by the sampling circuit 01. The drain of the bth third switch serves as the output of the isolation unit 20, outputting the second sampled voltage signal Vsen2 to the conversion module 50. Simultaneously, the gates of all third switches receive a modulation signal, ensuring that all third switches are turned on or off simultaneously. When all first switches and all third switches are turned on simultaneously, the voltage value of the first sampled voltage signal Vsen1 output by the sampling circuit 01 and the voltage value of the second sampled voltage signal Vsen2 output by the isolation unit 20 to the conversion module 50 are equal or approximately equal. This means that the total voltage drop across all third switches in the isolation unit 20 is very small or even zero, and can be ignored. When all first switching transistors and all third switching transistors are simultaneously turned off, the sampling circuit 01 cannot output the first sampled voltage signal Vsen1 to the isolation unit 20, and the isolation unit 20 cannot output the second sampled voltage signal Vsen2 to the conversion module 50. At this time, the voltage value of the input voltage signal Vin of the sampling circuit 01 is significantly greater than the voltage value of the second sampled voltage signal Vsen2 output by the isolation unit 20 to the conversion module 50. This triggers the pull-up unit 30 to turn on and output a preset voltage to the conversion module 50, ensuring that the conversion module 50 has a continuous input voltage, thereby improving the speed and accuracy of establishing the second sampled voltage.

[0057] It should be noted that designers can select an appropriate number of third switching transistors based on actual conditions, and can select an appropriate number of MOS transistors as the third switching transistors to meet the actual requirements of the isolation unit 20. At the same time, designers can also select the model of the third switching transistor based on actual requirements. For example, N-type MOS transistors can be selected to meet the high-voltage isolation requirement of the isolation unit 20.

[0058] For example, Figure 4As shown, the isolation unit 20 includes three third switching transistors connected in series, M31, M32, and M33. M31 serves as the first third switching transistor, with its source electrically connected to the source of M13 and serving as the input of the isolation unit 20 for receiving the first sampled voltage signal Vsen1 output by the sampling circuit 01. M33 serves as the third third switching transistor, with its drain serving as the output of the isolation unit 20, outputting the second sampled voltage signal Vsen2 to the conversion module 50. Simultaneously, the gates of M31, M32, and M33 all receive a modulation signal, ensuring that M31, M32, and M33 are simultaneously turned on or off. When M11, M12, M13, M31, M32, and M33 are simultaneously turned on, the voltage value of the first sampled voltage signal Vsen1 output by the sampling circuit 01 and the voltage value of the second sampled voltage signal Vsen2 output by the isolation unit 20 to the conversion module 50 are equal or approximately equal. That is, the total voltage drop across M31, M32, and M33 in the isolation unit 20 is very small or even zero and can be ignored. When M11, M12, M13, M31, M32, and M33 are simultaneously turned off, the sampling circuit 01 cannot output the first sampled voltage signal Vsen1 to the isolation unit 20, and the isolation unit 20 cannot output the second sampled voltage signal Vsen2 to the conversion module 50. At this time, the voltage value of the input voltage signal Vin of the sampling circuit 01 is much greater than the voltage value of the second sampling voltage signal Vsen2 output by the isolation unit 20 to the conversion module 50, which can trigger the pull-up unit 30 to turn on and output the preset voltage to the conversion module 50, ensuring that the conversion module 50 has a continuous input voltage, thereby improving the establishment speed and accuracy of the second sampling voltage.

[0059] It should be noted that M31, M32, and M33 are all N-type MOS transistors. Selecting an N-type MOS transistor allows the drain of M33 to be electrically connected to the pull-up unit 30. When the pull-up unit 30 is triggered, the drain of M33 receives the preset voltage output by the pull-up unit 30. When the preset voltage output by the pull-up unit 30 is a high-voltage signal, the drain of M33 has high-voltage resistance, which can prevent M33 from being damaged when the pull-up unit 30 outputs the preset high voltage, thereby improving the reliability of the sampling circuit 01.

[0060] It should be noted that the first voltage output by the discharge unit 10 in the sampling circuit 01 is a PWM voltage signal, wherein the voltage node A is electrically connected to the gate of the first switching tube and the output terminal of the comparison module 40. The gate of the first switching tube outputs the first sampled voltage signal Vsen1 to the isolation unit 20 based on the PWM signal and the input voltage signal Vin output by the input power supply 60.

[0061] In one embodiment of the present application, the pull-up unit 30 includes c fourth switching tubes connected in series in sequence, the source of the first fourth switching tube is electrically connected to the input power supply 60, the drain of the cth fourth switching tube is electrically connected to the conversion module 50, and the gate of each fourth switching tube is electrically connected to its respective drain, where c is a positive integer.

[0062] Specifically, the switch tubes in the pull-up unit 30 are all defined as fourth switch tubes, and each fourth switch tube is connected in series in sequence. Among them, the source of the first fourth switch tube is electrically connected to the input power supply 60 and serves as the input end of the pull-up unit 30, for receiving the input voltage signal Vin output by the input power supply 60. The drain of the cth fourth switch tube serves as the output end of the pull-up unit 30, outputting a preset voltage to the conversion module 50. At the same time, the gate of each fourth switch tube is electrically connected to its respective drain, and each fourth switch tube is equivalent to a diode. The series connection of all fourth switch tubes is equivalent to the series connection of all diodes. When all first switch tubes and all second switch tubes are turned off at the same time, the sampling circuit 01 cannot output the first sampling voltage signal Vsen1 to the isolation unit 20, and the isolation unit 20 cannot output the second sampling voltage signal Vsen2 to the conversion module 50. At this time, the voltage value of the input voltage signal Vin of the sampling circuit 01 is much greater than the voltage value of the second sampling voltage signal Vsen2 output by the isolation unit 20 to the conversion module 50, which can trigger the pull-up unit 30 to turn on. That is, the difference between the voltage value of the input voltage signal Vin of the sampling circuit 01 and the voltage value of the second sampling voltage signal Vsen2 is greater than the turn-on voltage of all fourth switching tubes in the pull-up unit 30. At this time, all fourth switching tubes are turned on, and the drain of the cth fourth switching tube outputs a preset voltage to the conversion module 50, ensuring that the conversion module 50 has a continuous input voltage, thereby improving the establishment speed and accuracy of the second sampling voltage.

[0063] It should be noted that designers can select an appropriate number of fourth switching transistors based on actual conditions, and can select an appropriate number of MOS transistors as the fourth switching transistors to meet the actual requirements of the pull-up unit 30. Furthermore, designers can also select the model of the fourth switching transistor based on actual requirements. For example, P-type MOS transistors can be selected to meet the requirement that the pull-up unit 30 output a preset voltage to the conversion module 50.

[0064] For example, Figure 4As shown, the pull-up unit 30 includes two fourth switching transistors connected in series, M41 and M42. M41 serves as the first fourth switching transistor, with its source electrically connected to the input power supply 60 and serving as the input terminal of the pull-up unit 30, for receiving the input voltage signal Vin output by the input power supply 60. M42 serves as the second fourth switching transistor, with its drain serving as the output terminal of the pull-up unit 30, outputting a preset voltage to the conversion module 50. Simultaneously, the gate of M41 is electrically connected to the drain of M41, and the gate of M42 is electrically connected to the drain of M42. M41 and M42 act as diodes, and the series connection of M41 and M42 is equivalent to two diodes in series. When M11, M12, M13, M31, M32, and M33 are simultaneously turned off, the sampling circuit 01 cannot output the first sampled voltage signal Vsen1 to the isolation unit 20, and the isolation unit 20 cannot output the second sampled voltage signal Vsen2 to the conversion module 50. At this time, the voltage value of the input voltage signal Vin of the sampling circuit 01 is much greater than the voltage value of the second sampling voltage signal Vsen2 output by the isolation unit 20 to the conversion module 50, which can trigger the pull-up unit 30 to turn on. That is, the difference between the voltage value of the input voltage signal Vin of the sampling circuit 01 and the voltage value of the second sampling voltage signal Vsen2 is greater than the sum of the turn-on voltages of M41 and M42 in the pull-up unit 30. At this time, M41 and M42 are turned on, and the drain of M42 outputs a preset voltage to the conversion module 50, ensuring that the conversion module 50 has a continuous input voltage, thereby improving the establishment speed and accuracy of the second sampling voltage.

[0065] It should be noted that M41 and M42 are both P-type MOS transistors, the gate and drain of which are electrically connected, which is equivalent to a diode that conducts from top to bottom. The anode of the diode is electrically connected to the input power supply 60 and serves as the input end of the pull-up unit 30, for receiving the input voltage signal Vin output by the input power supply 60. The cathode of the diode serves as the output end of the pull-up unit 30, and outputs a preset voltage to the conversion module 50. The reason why the diode is not directly used in series is that when the input voltage signal Vin output by the input power supply 60 received by the pull-up unit 30 is a high-voltage signal, the diode may be damaged because it does not have a strong high-voltage resistance characteristic. The P-type MOS transistor has a strong high-voltage resistance characteristic and can receive the high-voltage signal output by the input power supply 60, thereby improving the reliability of the sampling circuit 01.

[0066] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A sampling circuit, characterized in that: The device comprises n first switching transistors connected in series and n-1 discharge units, wherein a common node of any two adjacent first switching transistors is connected to one discharge unit, and the discharge unit is configured to lower the voltage of the common node when the first switching transistors are in an off state; wherein n is an integer greater than 1; The discharge unit includes a second switch tube, wherein the drain and gate of the second switch tube are both connected to corresponding common nodes, and the source of the second switch tube is electrically connected to a voltage node; when the first switch tube is in an off state, the voltage value of the voltage node is a first voltage, and when the second switch tube is in an on state, the voltage drop is less than the withstand voltage value between the source and gate of the first switch tube; The voltage node is electrically connected to the gate of the first switching tube.

2. The sampling circuit according to claim 1, wherein: The second switch tube is an N-type MOS tube.

3. The sampling circuit according to claim 1, wherein: The source of the ath first switching transistor is electrically connected to the drain of the a+1th first switching transistor, where a is a positive integer and 1≤a<n.

4. A DC-DC converter, characterized in that: The sampling circuit comprises a comparison module, a conversion module, and the sampling circuit according to any one of claims 1 to 3, wherein the conversion module is configured to convert the error amplified voltage signal output by the DC-DC converter into a sampling current signal, the comparison module is configured to compare the first sampling voltage signal with the switch node voltage signal and output a modulation signal, the DC-DC converter is configured to adjust the switch node voltage signal according to the modulation signal and the input voltage signal output by the input power supply, the sampling circuit comprises n first switching tubes connected in series and n-1 discharge units, the drain of the first first switching tube is electrically connected to the input power supply, the source of the nth first switching tube is electrically connected to the conversion module, and the common node of any two adjacent first switching tubes is connected to one discharge unit, the discharge unit being configured to lower the voltage of the common node when the first switching tube is in the off state; wherein n is an integer greater than 1.

5. The DC-DC converter according to claim 4, characterized in that: The DC-DC converter further includes an isolation unit and a pull-up unit; The isolation unit is connected in series between the sampling circuit and the conversion module, and is further configured to output a second sampling voltage signal to the conversion module according to the first sampling voltage signal and the modulation signal; The pull-up unit is connected in series between the input power supply and the conversion module, and is further used to output a preset voltage to the conversion module according to the input voltage signal when the sampling circuit does not output the first sampling voltage signal.

6. The DC-DC converter according to claim 5, characterized in that: The isolation unit includes b third switching tubes connected in series in sequence, the source of the first third switching tube is electrically connected to the source of the nth first switching tube, the drain of the bth third switching tube is electrically connected to the conversion module, and the gates of all the third switching tubes receive the modulation signal, where b is a positive integer.

7. The DC-DC converter according to claim 6, characterized in that: The pull-up unit includes c fourth switching tubes connected in series, the source of the first fourth switching tube is electrically connected to the input power supply, the drain of the cth fourth switching tube is electrically connected to the conversion module, and the gate of each fourth switching tube is electrically connected to its own drain, where c is a positive integer.

8. The DC-DC converter according to claim 7, wherein: All the third switch tubes are N-type MOS tubes, and all the fourth switch tubes are P-type MOS tubes.

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