Surge-suppressing power supply

Abstract

A surge-suppressing power supply includes: a bridge rectifier, a first surge absorption circuit, a second surge absorption circuit, a third surge absorption circuit, and a boost converter. The bridge rectifier can generate a rectified potential according to a first input potential and a second input potential. The first surge absorption circuit can receive the rectified potential, wherein the first surge absorption circuit is coupled to the ground. The second surge absorption circuit is coupled to the first surge absorption circuit. The third surge absorption circuit is coupled to the second surge absorption circuit, wherein the third surge absorption circuit includes a transformer. The boost converter is coupled to the third surge absorption circuit and can generate an output potential.

Description

Technical Field

[0001] The present invention relates to a power supply, and more particularly to a power supply capable of suppressing surges. Background Art

[0002] Among the reasons for the generation of surges in a power supply, the most serious one is the surge caused by lightning strikes. Lightning surges are generated by natural phenomena. If the power supply is used in an area prone to thunderstorms, it is necessary to add appropriate lightning surge protection. The commonly used surge protection component in traditional power supplies is a varistor, which is a component whose resistance value changes with different voltage values. When the voltage exceeds the critical voltage, the varistor will become in an approximately short-circuit state, guiding the surge into the varistor and dissipating it in the form of heat energy. However, if the energy of the lightning surge is too large and exceeds the range that the varistor itself can withstand, it will still cause damage to the varistor and the power supply. In view of this, it is necessary to propose a completely new solution to overcome the defects faced by the prior art. Summary of the Invention

[0003] In a preferred embodiment, the present invention provides a power supply for suppressing surges, comprising: a bridge rectifier for generating a rectified potential according to a first input potential and a second input potential; a first surge absorption circuit for receiving the rectified potential, wherein the first surge absorption circuit is coupled to the ground; a second surge absorption circuit coupled to the first surge absorption circuit; a third surge absorption circuit coupled to the second surge absorption circuit, wherein the third surge absorption circuit includes a transformer; and a boost converter coupled to the third surge absorption circuit and generating an output potential; wherein the first surge absorption circuit provides a relatively high impedance value, the second surge absorption circuit provides a medium impedance value, and the third surge absorption circuit provides a relatively low impedance value.

[0004] In some embodiments, the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to a ground potential, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node.

[0005] In some embodiments, the first surge absorption circuit includes: a Zener diode having an anode and a cathode, wherein the anode of the Zener diode is coupled to a second node, and the cathode of the Zener diode is coupled to the first node to receive the rectified potential; and a first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the second node, and the second end of the first inductor is coupled to the ground.

[0006] In some embodiments, the first surge absorption circuit further includes: a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the first node, and the second end of the first resistor is coupled to a third node; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the third node, and the second end of the second resistor is coupled to the ground; a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to a fourth node; and a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the fourth node, and the second end of the second capacitor is coupled to the ground.

[0007] In some embodiments, the second surge absorption circuit includes: a first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is coupled to a fifth node, the first end of the first transistor is coupled to a sixth node, and the second end of the first transistor is coupled to the first node; a second transistor having a control end, a first end, and a second end, wherein the control end of the second transistor is coupled to a seventh node, the first end of the second transistor is coupled to an eighth node, and the second end of the second transistor is coupled to the sixth node; and a third transistor having a control end, a first end, and a second end, wherein the control end of the third transistor is coupled to a ninth node, the first end of the third transistor is coupled to a tenth node, and the second end of the third transistor is coupled to the eighth node.

[0008] In some embodiments, the second surge absorption circuit further includes: a third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the first node, and the second end of the third resistor is coupled to the tenth node; a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the fifth node, and the second end of the fourth resistor is coupled to the third node; a fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is coupled to the seventh node, and the second end of the fifth resistor is coupled to the third node; and a sixth resistor having a first end and a second end, wherein the first end of the sixth resistor is coupled to the ninth node, and the second end of the sixth resistor is coupled to the third node.

[0009] In some embodiments, the transformer of the third surge absorption circuit includes: a first main coil having a first end and a second end, wherein the first end of the first main coil is coupled to the tenth node, and the second end of the first main coil is coupled to an eleventh node; a second main coil having a first end and a second end, wherein the first end of the second main coil is coupled to the eleventh node, and the second end of the second main coil is coupled to a twelfth node; and a third main coil having a first end and a second end, wherein the first end of the third main coil is coupled to the twelfth node, and the second end of the third main coil is coupled to a thirteenth node.

[0010] In some embodiments, the transformer of the third surge absorption circuit further includes: a first secondary coil having a first end and a second end, wherein the first end of the first secondary coil is coupled to a fourteenth node, and the second end of the first secondary coil is coupled to a fifteenth node; a second secondary coil having a first end and a second end, wherein the first end of the second secondary coil is coupled to the fifteenth node, and the second end of the second secondary coil is coupled to a sixteenth node; and a third secondary coil having a first end and a second end, wherein the first end of the third secondary coil is coupled to a seventeenth node, and the second end of the third secondary coil is coupled to the second node.

[0011] In some embodiments, the third surge absorption circuit further includes: a third capacitor having a first end and a second end, wherein the first end of the third capacitor is coupled to the eleventh node, and the second end of the third capacitor is coupled to the thirteenth node; a fourth capacitor having a first end and a second end, wherein the first end of the fourth capacitor is coupled to the fifteenth node, and the second end of the fourth capacitor is coupled to the sixteenth node; a seventh resistor having a first end and a second end, wherein the first end of the seventh resistor is coupled to the sixteenth node, and the second end of the seventh resistor is coupled to the ground; an eighth resistor having a first end and a second end, wherein the first end of the eighth resistor is coupled to the seventeenth node, and the second end of the eighth resistor is coupled to the ground; and a ninth resistor having a first end and a second end, wherein the first end of the ninth resistor is coupled to the seventeenth node, and the second end of the ninth resistor is coupled to the second node.

[0012] In some embodiments, the boost converter includes: a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the fourteenth node, and the second end of the second inductor is coupled to the fifteenth node; a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the fifteenth node, and the cathode of the fifth diode is coupled to an output node to output the output potential; a fourth transistor having a control end, a first end, and a second end, wherein the control end of the fourth transistor is for receiving a clock potential, the first end of the fourth transistor is coupled to the ground potential, and the second end of the fourth transistor is coupled to the fifteenth node; and a fifth capacitor having a first end and a second end, wherein the first end of the fifth capacitor is coupled to the output node, and the second end of the fifth capacitor is coupled to the ground potential. Description of the Drawings

[0013] Figure 1 is a schematic diagram showing a power supply according to an embodiment of the present invention.

[0014] Figure 2 is a schematic diagram showing a power supply according to an embodiment of the present invention.

[0015] Figure 3 is a graph showing the relationship between the rectified potential and the input current of a power supply according to an embodiment of the present invention.

[0016] Figure 4 is a surge test diagram of a conventional power supply.

[0017] Figure 5It is a surge test diagram of a power supply according to an embodiment of the present invention.

[0018] Among them, the reference numerals are explained as follows:

[0019] 100, 200: Power supply

[0020] 110, 210: Bridge rectifier

[0021] 120, 220: First surge absorption circuit

[0022] 130, 230: Second surge absorption circuit

[0023] 140, 240: Third surge absorption circuit

[0024] 150, 250: Transformer

[0025] 160, 260: Boost converter

[0026] 190, 290: Ground

[0027] 251: First main coil

[0028] 252: Second main coil

[0029] 253: Third main coil

[0030] 254: First secondary coil

[0031] 255: Second secondary coil

[0032] 256: Third secondary coil

[0033] 401: First dashed box

[0034] 402: Second dashed box

[0035] 501: Third dashed box

[0036] 502: Fourth dashed box

[0037] C1: First capacitor

[0038] C2: Second capacitor

[0039] C3: Third capacitor

[0040] C4: Fourth capacitor

[0041] C5: Fifth capacitor

[0042] D1: First diode

[0043] D2: Second diode

[0044] D3: The third diode

[0045] D4: The fourth diode

[0046] D5: The fifth diode

[0047] DZ: Zener diode

[0048] G1: The first interval

[0049] G2: The second interval

[0050] G3: The third interval

[0051] L1: The first inductor

[0052] L2: The second inductor

[0053] IIN: Input current

[0054] M1: The first transistor

[0055] M2: The second transistor

[0056] M3: The third transistor

[0057] M4: The fourth transistor

[0058] N1: The first node

[0059] N2: The second node

[0060] N3: The third node

[0061] N4: The fourth node

[0062] N5: The fifth node

[0063] N6: The sixth node

[0064] N7: The seventh node

[0065] N8: The eighth node

[0066] N9: The ninth node

[0067] N10: The tenth node

[0068] N11: The eleventh node

[0069] N12: The twelfth node

[0070] N13: The thirteenth node

[0071] N14: The fourteenth node

[0072] N15: The fifteenth node

[0073] N16: The sixteenth node

[0074] N17: The seventeenth node

[0075] NIN1: The first input node

[0076] NIN2: The second input node

[0077] NOUT: The output node

[0078] R1: The first resistor

[0079] R2: The second resistor

[0080] R3: The third resistor

[0081] R4: The fourth resistor

[0082] R5: The fifth resistor

[0083] R6: The sixth resistor

[0084] R7: The seventh resistor

[0085] R8: The eighth resistor

[0086] R9: The ninth resistor

[0087] V3: Potential

[0088] VA: Clock potential

[0089] VIN1: The first input potential

[0090] VIN2: The second input potential

[0091] VOUT: Output potential

[0092] VR: Rectified potential

[0093] VSS: Ground potential

[0094] Z1: Higher impedance value

[0095] Z2: Moderate impedance value

[0096] Z3: Lower impedance value Detailed implementation manners

[0097] To make the objectives, features, and advantages of the present invention more obvious and understandable, specific embodiments of the present invention are hereinafter specifically exemplified and described in detail in conjunction with the accompanying drawings as follows.

[0098] Certain terms are used in the description and claims to refer to particular components. Those skilled in the art will appreciate that hardware manufacturers may use different names to refer to the same component. This specification and the claims do not distinguish components by the difference in name, but by the difference in function. The terms "comprising" and "including" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". The term "substantially" means within an acceptable error range, and those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device in the text, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

[0099] Figure 1 is a schematic diagram showing a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer. As Figure 1 shown, the power supply 100 includes: a bridge rectifier 110, a first surge absorption circuit 120, a second surge absorption circuit 130, a third surge absorption circuit 140, and a boost converter 160. It should be noted that although not shown in Figure 1 , the power supply 100 may further include other components, such as: a voltage regulator and / or a negative feedback circuit.

[0100] The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2. Both the first input potential VIN1 and the second input potential VIN2 can be from an external input power supply, and an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be approximately 50 Hz or 60 Hz, and the root mean square value of the AC voltage can range from 90 V to 264 V, but it is not limited thereto. The first surge absorption circuit 120 can receive the rectified potential VR, wherein the first surge absorption circuit 120 is coupled to the ground 190. The ground 190 can refer to the earth or any grounding path coupled to the earth, which is not an internal component of the power supply 100. The second surge absorption circuit 130 is coupled to the first surge absorption circuit 120. The third surge absorption circuit 140 is coupled to the second surge absorption circuit 130, wherein the third surge absorption circuit 140 includes a transformer 150. The boost converter 160 is coupled to the third surge absorption circuit 140 and can generate an output potential VOUT. For example, the output potential VOUT can be a DC potential, and its potential level can be between 300 V and 500 V, but it is not limited thereto. It should be noted that the first surge absorption circuit 120 can provide a relatively high impedance value Z1, the second surge absorption circuit 130 can provide a medium impedance value Z2, and the third surge absorption circuit 140 can provide a relatively low impedance value Z3 (i.e., Z1 > Z2 > Z3). During normal operation, neither the first surge absorption circuit 120, the second surge absorption circuit 130, nor the third surge absorption circuit 140 will have any action. When a high-voltage surge enters the power supply 100, its energy can be released to the ground 190 through the first surge absorption circuit 120, the second surge absorption circuit 130, and the third surge absorption circuit 140, so that damage to the power supply 100 can be avoided. According to the actual measurement results, the power supply 100 of the present invention can fully comply with the surge protection specifications of the International Electrotechnical Commission (IEC), especially the lightning strike test part of IEC 61000-4-5.

[0101] The following embodiments will introduce the detailed structure and operation mode of the power supply 100. It must be understood that these diagrams and descriptions are only for illustration and not for limiting the scope of the present invention.

[0102] Figure 2 is a schematic diagram showing a power supply 200 according to an embodiment of the present invention. In Figure 2In an embodiment, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first surge absorption circuit 220, a second surge absorption circuit 230, a third surge absorption circuit 240, and a boost converter 260, wherein the third surge absorption circuit 240 includes a transformer 250. The first input node NIN1 and the second input node NIN2 of the power supply 200 can respectively receive a first input potential VIN1 and a second input potential VIN2 from an external input power supply, and the output node NOUT of the power supply 200 can output an output potential VOUT to an electronic device (not shown). It must be understood that a high-voltage surge caused by lightning strike or other reasons may enter either the first input node NIN1 or the second input node NIN2 of the power supply 200.

[0103] The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS (e.g., 0V), and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

[0104] The first surge absorption circuit 220 includes a Zener Diode DZ, a first inductor L1, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The Zener Diode DZ has an anode and a cathode, wherein the anode of the Zener Diode DZ is coupled to a second node N2, and the cathode of the Zener Diode DZ is coupled to the first node N1 to receive the rectified potential VR. In some embodiments, the Zener Diode DZ can also be replaced by a plurality of serially-coupled Zener diodes to provide a larger breakdown voltage. The first inductor L1 has a first end and a second end, wherein the first end of the first inductor L1 is coupled to the second node N2, and the second end of the first inductor L1 is coupled to the ground 290. The ground 290 can refer to the earth, or any grounding path coupled to the earth, which is not an internal component of the power supply 200.

[0105] The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is coupled to the first node N1, and the second end of the first resistor R1 is coupled to a third node N3. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the third node N3, and the second end of the second resistor R2 is coupled to the ground 290. In some embodiments, the first resistor R1 or (and) the second resistor R2 can also be replaced by a plurality of serially-coupled resistors to provide a larger resistance value. The first capacitor C1 has a first end and a second end, wherein the first end of the first capacitor C1 is coupled to the first node N1, and the second end of the first capacitor C1 is coupled to a fourth node N4. The second capacitor C2 has a first end and a second end, wherein the first end of the second capacitor C2 is coupled to the fourth node N4, and the second end of the second capacitor C2 is coupled to the ground 290.

[0106] The second surge absorption circuit 230 includes a first transistor M1, a second transistor M2, a third transistor M3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first transistor M1, the second transistor M2, and the third transistor M3 can each be an N-type metal oxide semiconductor field effect transistor. The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the first transistor M1 is coupled to a fifth node N5, the first terminal of the first transistor M1 is coupled to a sixth node N6, and the second terminal of the first transistor M1 is coupled to the first node N1. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the second transistor M2 is coupled to a seventh node N7, the first terminal of the second transistor M2 is coupled to an eighth node N8, and the second terminal of the second transistor M2 is coupled to the sixth node N6. The third transistor M3 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the third transistor M3 is coupled to a ninth node N9, the first terminal of the third transistor M3 is coupled to a tenth node N10, and the second terminal of the third transistor M3 is coupled to the eighth node N8.

[0107] The third resistor R3 has a first end and a second end, wherein the first end of the third resistor R3 is coupled to the first node N1, and the second end of the third resistor R3 is coupled to the tenth node N10. In some embodiments, the third resistor R3 can also be replaced by a plurality of resistors connected in series to provide a larger resistance value. The fourth resistor R4 has a first end and a second end, wherein the first end of the fourth resistor R4 is coupled to the fifth node N5, and the second end of the fourth resistor R4 is coupled to the third node N3. The fifth resistor R5 has a first end and a second end, wherein the first end of the fifth resistor is coupled to the seventh node N7, and the second end of the fifth resistor R5 is coupled to the third node N3. The sixth resistor R6 has a first end and a second end, wherein the first end of the sixth resistor R6 is coupled to the ninth node N9, and the second end of the sixth resistor R6 is coupled to the third node N3.

[0108] The third surge absorption circuit 240 includes a transformer 250, a third capacitor C3, a fourth capacitor C4, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The transformer 250 includes a first main coil 251, a second main coil 252, a third main coil 253, a first secondary coil 254, a second secondary coil 255, and a third secondary coil 256. The first main coil 251, the second main coil 252, and the third main coil 253 can all be located on the same side (e.g., the primary side) of the transformer 250 and can be serially coupled to each other. The first secondary coil 254, the second secondary coil 255, and the third secondary coil 256 are all located on the opposite side (e.g., the secondary side, which can be isolated from the aforementioned primary side) of the transformer 250 and can be serially coupled to each other.

[0109] The first main coil 251 has a first end and a second end, wherein the first end of the first main coil 251 is coupled to the tenth node N10, and the second end of the first main coil 251 is coupled to an eleventh node N11. The second main coil 252 has a first end and a second end, wherein the first end of the second main coil 252 is coupled to the eleventh node N11, and the second end of the second main coil 252 is coupled to a twelfth node N12. The third main coil 253 has a first end and a second end, wherein the first end of the third main coil 253 is coupled to the twelfth node N12, and the second end of the third main coil 253 is coupled to a thirteenth node N13. The first secondary coil 254 has a first end and a second end, wherein the first end of the first secondary coil 254 is coupled to a fourteenth node N14, and the second end of the first secondary coil 254 is coupled to a fifteenth node N15. The second secondary coil 255 has a first end and a second end, wherein the first end of the second secondary coil 255 is coupled to the fifteenth node N15, and the second end of the second secondary coil 255 is coupled to a sixteenth node N16. The third secondary coil 256 has a first end and a second end, wherein the first end of the third secondary coil 256 is coupled to a seventeenth node N17, and the second end of the third secondary coil 256 is coupled to the second node N2.

[0110] The third capacitor C3 has a first end and a second end, wherein the first end of the third capacitor C3 is coupled to the eleventh node N11, and the second end of the third capacitor C3 is coupled to the thirteenth node N13. The fourth capacitor C4 has a first end and a second end, wherein the first end of the fourth capacitor C4 is coupled to the fifteenth node N15, and the second end of the fourth capacitor C4 is coupled to the sixteenth node N16. The seventh resistor R7 has a first end and a second end, wherein the first end of the seventh resistor R7 is coupled to the sixteenth node N16, and the second end of the seventh resistor R7 is coupled to ground 290. The eighth resistor R8 has a first end and a second end, wherein the first end of the eighth resistor R8 is coupled to the seventeenth node N17, and the second end of the eighth resistor R8 is coupled to ground 290. The ninth resistor R9 has a first end and a second end, wherein the first end of the ninth resistor R9 is coupled to the seventeenth node N17, and the second end of the ninth resistor R9 is coupled to the second node N2. In some embodiments, the ninth resistor R9 can also be replaced by a plurality of resistors connected in series to provide a larger resistance value.

[0111] The boost converter 260 includes a second inductor L2, a fifth diode D5, a fourth transistor M4, and a fifth capacitor C5. The second inductor L2 has a first end and a second end, wherein the first end of the second inductor L2 is coupled to the fourteenth node N14, and the second end of the second inductor L2 is coupled to the fifteenth node N15. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the fifteenth node N15, and the cathode of the fifth diode D5 is coupled to the output node NOUT. The fourth transistor M4 can be an N-type metal oxide semiconductor field effect transistor. The fourth transistor M4 has a control end (e.g., a gate), a first end (e.g., a source), and a second end (e.g., a drain), wherein the control end of the fourth transistor M4 is used to receive a clock potential VA, the first end of the fourth transistor M4 is coupled to the ground potential VSS, and the second end of the fourth transistor M4 is coupled to the fifteenth node N15. For example, the clock potential VA can be maintained at a fixed potential when the power supply 200 is initialized, and a periodic clock waveform can be provided after the power supply 200 enters the normal operation stage. The fifth capacitor C5 has a first end and a second end, wherein the first end of the fifth capacitor C5 is coupled to the output node NOUT, and the second end of the fifth capacitor C5 is coupled to the ground potential VSS.

[0112] In some embodiments, the surge suppression mechanism of the power supply 200 may be as described below. When a high-voltage surge enters the first input node NIN1 or the second input node NIN2, its energy will first be transferred to the first surge absorption circuit 220. If the energy of this high-voltage surge is large enough, the potential V3 at the third node N3 will exceed a critical potential, so that the three transistors in the second surge absorption circuit 230 can be turned on. Then, the energy of the high-voltage surge can be further transferred to the third surge absorption circuit 240 and released to the ground 290 through its transformer 250. Conversely, if there is no high-voltage surge, the first surge absorption circuit 220, the second surge absorption circuit 230, and the third surge absorption circuit 240 will not operate, and the rectified potential VR can be converted into the output potential VOUT through the boost converter 260.

[0113] Figure 3 FIG. is a graph showing the relationship between the rectified potential VR and the input current IIN of the power supply 200 according to an embodiment of the present invention, which can be measured at the first node N1. The horizontal axis represents the current value of the input current IIN, and the vertical axis represents the potential level of the rectified potential VR. According to Figure 3 the measurement results, the impedance characteristics of the power supply 200 (i.e., Figure 3 the slope in FIG.) can be divided into a first interval G1, a second interval G2, and a third interval G3. The first interval G1 can correspond to the first surge absorption circuit 220, which can provide a relatively high impedance value Z1. The second interval G2 can correspond to the second surge absorption circuit 230, which can provide a moderate impedance value Z2. The third interval G3 can correspond to the third surge absorption circuit 240, which can provide a relatively low impedance value Z3.

[0114] Figure 4 FIG. is a surge test diagram of a conventional power supply, where the horizontal axis represents the input voltage and the vertical axis represents the time. According to Figure 4 the measurement results, when a high-voltage surge enters a conventional power supply using a rheostat, its input voltage will increase significantly (as shown by a first dashed box 401). In addition, after multiple surge tests, the rheostat may be damaged, causing the input voltage to decay rapidly and unable to return to its original level (as shown by a second dashed box 402).

[0115] Figure 5 FIG. is a surge test diagram of the power supply 200 according to an embodiment of the present invention, where the horizontal axis represents the input voltage (i.e., a potential difference between the first input potential VIN1 and the second input potential VIN2), and the vertical axis represents the time. According to Figure 5Measurement results show that when a high-voltage surge enters the power supply 200 using the first surge absorption circuit 220, the second surge absorption circuit 230, and the third surge absorption circuit 240, its input voltage can maintain only a small oscillation (as shown by a third dashed box 501). Additionally, after multiple surge tests, since there will be no problem of varistor damage, the input voltage can generally maintain its original level (as shown by a fourth dashed box 502).

[0116] In some embodiments, the component parameters of the power supply 200 may be as described below. The inductance value of the first inductor L1 may be between 0.9 mH and 1.1 mH, preferably about 1 mH. The inductance value of the second inductor L2 may be between 324 μH and 396 μH, preferably about 360 μH. The capacitance value of the first capacitor C1 may be between 85 μF and 115 μF, preferably about 100 μF. The capacitance value of the second capacitor C2 may be between 85 μF and 115 μF, preferably about 100 μF. The capacitance value of the third capacitor C3 may be between 0.8 μF and 1.2 μF, preferably about 1 μF. The capacitance value of the fourth capacitor C4 may be between 0.8 μF and 1.2 μF, preferably about 1 μF. The capacitance value of the fifth capacitor C5 may be between 544 μF and 816 μF, preferably about 680 μF. The resistance value of the first resistor R1 may be between 43.2 MΩ and 52.8 MΩ, preferably about 48 MΩ. The resistance value of the second resistor R2 may be between 0.9 MΩ and 1.1 MΩ, preferably about 1 MΩ. The resistance value of the third resistor R3 may be between 510 KΩ and 690 KΩ, preferably about 600 KΩ. The resistance value of the fourth resistor R4 may be between 95 Ω and 105 Ω, preferably about 100 Ω. The resistance value of the fifth resistor R5 may be between 95 Ω and 105 Ω, preferably about 100 Ω. The resistance value of the sixth resistor R6 may be between 95 Ω and 105 Ω, preferably about 100 Ω. The resistance value of the seventh resistor R7 may be between 0.9 KΩ and 1.1 KΩ, preferably about 1 KΩ. The resistance value of the eighth resistor R8 may be between 0.9 KΩ and 1.1 KΩ, preferably about 1 KΩ. The resistance value of the ninth resistor R9 may be between 18 KΩ and 22 KΩ, preferably about 20 KΩ. The turn ratio of the first main coil 251 to the second main coil 252 may be between 0.1 and 10, preferably about 2. The turn ratio of the first main coil 251 to the third main coil 253 may be between 0.1 and 10, preferably about 2. The turn ratio of the first main coil 251 to the first secondary coil 254 may be between 0.1 and 10, preferably about 1. The turn ratio of the first main coil 251 to the second secondary coil 255 may be between 0.1 and 10, preferably about 2. The turn ratio of the first main coil 251 to the third secondary coil 256 may be between 0.1 and 10, preferably about 6. The above parameter ranges are obtained based on the results of multiple experiments, which help to optimize the surge protection mechanism of the power supply 200.

[0117] The present invention proposes a novel power supply, which includes three surge absorption circuits. According to the actual measurement results, using the power supply designed as described above can effectively avoid circuit damage caused by high-voltage surges, so it is very suitable for various types of devices.

[0118] It should be noted that the above-mentioned potential, current, resistance value, inductance value, capacitance value, and other component parameters are not limiting conditions of the present invention. The designer can adjust these set values according to different needs. The power supply of the present invention is not limited to Figures 1 - 5 the state shown. The present invention may only include Figures 1 - 5 any one or more features of any one or more embodiments. In other words, not all of the illustrated features need to be implemented simultaneously in the power supply of the present invention. Although the embodiments of the present invention use metal-oxide-semiconductor field-effect transistors as examples, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field-effect transistors or fin field-effect transistors, etc., without affecting the effects of the present invention.

[0119] In the present specification and claims, ordinal numbers such as "first", "second", "third", etc. do not have a sequential relationship with each other. They are only used to label and distinguish two different components with the same name.

[0120] Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the appended claims.

Claims

1. A power supply for suppressing surges, comprising: A bridge rectifier that generates a rectified potential based on a first input potential and a second input potential; A first surge absorption circuit that receives the rectified potential, wherein the first surge absorption circuit is coupled to the ground; A second surge absorption circuit coupled to the first surge absorption circuit; A third surge absorption circuit coupled to the second surge absorption circuit, wherein the third surge absorption circuit includes a transformer; and A boost converter coupled to the third surge absorption circuit and generating an output potential; Wherein the first surge absorption circuit provides a first impedance value, the second surge absorption circuit provides a second impedance value, and the third surge absorption circuit provides a third impedance value, wherein the first impedance value is greater than the second impedance value, and the second impedance value is greater than the third impedance value.

2. The power supply according to claim 1, wherein the bridge rectifier includes: A first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; A second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; A third diode having an anode and a cathode, wherein the anode of the third diode is coupled to a ground potential, and the cathode of the third diode is coupled to the first input node; And A fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node.

3. The power supply according to claim 2, wherein the first surge absorption circuit includes: A Zener diode having an anode and a cathode, wherein the anode of the Zener diode is coupled to a second node, and the cathode of the Zener diode is coupled to the first node to receive the rectified potential; And A first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the second node, and the second end of the first inductor is coupled to the ground.

4. The power supply according to claim 3, wherein the first surge absorption circuit further includes: A first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the first node, and the second end of the first resistor is coupled to a third node; A second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the third node, and the second end of the second resistor is coupled to the ground; A first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to a fourth node; And A second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the fourth node and the second end of the second capacitor is coupled to the ground.

5. The power supply according to claim 4, wherein the second surge absorption circuit includes: A first transistor having a control end, a first end, and a second end, wherein the control end of the first transistor is coupled to a fifth node, the first end of the first transistor is coupled to a sixth node, and the second end of the first transistor is coupled to the first node; A second transistor having a control end, a first end, and a second end, wherein the control end of the second transistor is coupled to a seventh node, the first end of the second transistor is coupled to an eighth node, and the second end of the second transistor is coupled to the sixth node; And A third transistor having a control end, a first end, and a second end, wherein the control end of the third transistor is coupled to a ninth node, the first end of the third transistor is coupled to a tenth node, and the second end of the third transistor is coupled to the eighth node.

6. The power supply according to claim 5, wherein the second surge absorption circuit further includes: A third resistor having a first end and a second end, wherein the first end of the third resistor is coupled to the first node and the second end of the third resistor is coupled to the tenth node; A fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is coupled to the fifth node and the second end of the fourth resistor is coupled to the third node; A fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is coupled to the seventh node and the second end of the fifth resistor is coupled to the third node; And A sixth resistor having a first end and a second end, wherein the first end of the sixth resistor is coupled to the ninth node and the second end of the sixth resistor is coupled to the third node.

7. The power supply according to claim 6, wherein the transformer of the third surge absorption circuit includes: A first main coil having a first end and a second end, wherein the first end of the first main coil is coupled to the tenth node and the second end of the first main coil is coupled to an eleventh node; A second main coil having a first end and a second end, wherein the first end of the second main coil is coupled to the eleventh node and the second end of the second main coil is coupled to a twelfth node; And A third main coil having a first end and a second end, wherein the first end of the third main coil is coupled to the twelfth node and the second end of the third main coil is coupled to a thirteenth node.

8. The power supply according to claim 7, wherein the transformer of the third surge absorption circuit further includes: A first secondary coil having a first end and a second end, wherein the first end of the first secondary coil is coupled to a fourteenth node and the second end of the first secondary coil is coupled to a fifteenth node; A second secondary coil having a first end and a second end, wherein the first end of the second secondary coil is coupled to the fifteenth node and the second end of the second secondary coil is coupled to a sixteenth node; and A third secondary coil having a first end and a second end, wherein the first end of the third secondary coil is coupled to a seventeenth node and the second end of the third secondary coil is coupled to the second node.

9. The power supply according to claim 8, wherein the third surge absorption circuit further comprises: A third capacitor having a first end and a second end, wherein the first end of the third capacitor is coupled to the eleventh node and the second end of the third capacitor is coupled to the thirteenth node; A fourth capacitor having a first end and a second end, wherein the first end of the fourth capacitor is coupled to the fifteenth node and the second end of the fourth capacitor is coupled to the sixteenth node; A seventh resistor having a first end and a second end, wherein the first end of the seventh resistor is coupled to the sixteenth node and the second end of the seventh resistor is coupled to ground; An eighth resistor having a first end and a second end, wherein the first end of the eighth resistor is coupled to the seventeenth node and the second end of the eighth resistor is coupled to ground; and A ninth resistor having a first end and a second end, wherein the first end of the ninth resistor is coupled to the seventeenth node and the second end of the ninth resistor is coupled to the second node.

10. The power supply according to claim 9, wherein the boost converter comprises: A second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the fourteenth node and the second end of the second inductor is coupled to the fifteenth node; A fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the fifteenth node and the cathode of the fifth diode is coupled to an output node to output the output potential; A fourth transistor having a control end, a first end, and a second end, wherein the control end of the fourth transistor is for receiving a clock potential, the first end of the fourth transistor is coupled to the ground potential, and the second end of the fourth transistor is coupled to the fifteenth node; and A fifth capacitor having a first end and a second end, wherein the first end of the fifth capacitor is coupled to the output node and the second end of the fifth capacitor is coupled to the ground potential.

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