Switching power supply secondary side synchronous rectification controller and switching power supply

Abstract

The embodiment of the application discloses a kind of secondary side synchronous rectification controllers of switching power supply and switching power supply, the synchronous rectification controller includes: demagnetization detection circuit, standby judging circuit, and gate circuit and drive circuit;Wherein, the input end of the demagnetization detection circuit is connected with one end of the synchronous rectification MOS Q2 of the switching power supply, one output end of the demagnetization detection circuit is connected with one input end of the gate circuit, another output end of the demagnetization detection circuit is connected with the input end of the standby judging circuit, the output end of the standby judging circuit is connected with another input end of the gate circuit, the output end of the gate circuit is connected with the input end of the drive circuit, the output end of the drive circuit is connected with the gate of the MOS Q2.The technical scheme of the application has the advantages of improving system efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switching power supply, in particular to a switching power supply secondary side synchronous rectification controller and a switching power supply. BACKGROUND

[0002] With the continuous growth of charging power of mobile terminals, energy efficiency is increasingly valued by people, and countries and regions are constantly improving energy efficiency standards. The application of synchronous rectification controller replaces the traditional Schottky diode rectifier, greatly improving the charging efficiency of adapters and chargers, and therefore is more and more widely used. However, the prior art of synchronous rectification controller indeed improves the charging efficiency of the power supply system under heavy load, but ignores the fact that the power consumption of the synchronous rectification controller itself under no load or light load of the power supply system reduces the system efficiency, and increases the standby power consumption of the system, wasting a lot of energy and increasing energy consumption. SUMMARY

[0003] Therefore, in order to solve the problem of high energy consumption in the prior art, the present application provides a switching power supply secondary side synchronous rectification controller.

[0004] The present application solves the above problems by the following technical means:

[0005] The present application provides a switching power supply secondary side synchronous rectification controller, which comprises a demagnetization detection circuit, a standby judgment circuit, an AND gate circuit and a driving circuit. One end of a synchronous rectification MOS Q2 of the switching power supply is connected to the input end of the demagnetization detection circuit. One output end of the demagnetization detection circuit is connected to one input end of the AND gate circuit. The other output end of the demagnetization detection circuit is connected to the input end of the standby judgment circuit. The output end of the standby judgment circuit is connected to the other input end of the AND gate circuit. The output end of the AND gate circuit is connected to the input end of the driving circuit. The output end of the driving circuit is connected to the gate of the MOS Q2.

[0006] The demagnetization detection circuit is used for detecting the voltage difference VDET between the drain and the source of the MOS Q2. When the VDET is lower than a set threshold, the DEMAG signal is output through two output ends.

[0007] The standby judgment circuit is used for integrating the DEMAG signal and comparing it with a set threshold to obtain a comparison result. The output signal V G-EN is determined according to the comparison result.

[0008] The AND gate circuit is used for outputting the V G-EN signal according to the DEMAG signal and the V gate signal.

[0009] The driving circuit is used for outputting a driving signal according to the Vgate The signal judges whether to output the VG signal to the gate of the MOS Q2 to drive the MOS Q2.

[0010] Optionally, the demagnetization detection circuit comprises a first comparator, an inverter INV, a resistor and a reference voltage V DET-ref ; wherein,

[0011] The non-inverting input terminal of the first comparator is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to VDET, and the inverting input terminal of the first comparator is connected to the reference voltage V DET-ref The two ends of the second resistor R2 are respectively connected to the non-inverting input terminal and the output terminal of the first comparator, and the output terminal of the first comparator outputs the DEMAG signal through the inverter INV.

[0012] Optionally, the standby judgment circuit comprises a current source, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop and an inverter; wherein

[0013] The drain of the first MOS tube is connected to the current source I charge , the gate of the first MOS tube is connected to the DEMAG signal, the source of the first MOS tube is connected to the drain of the second MOS tube and one end of the capacitor C1, the gate of the second MOS tube is connected to the clock signal CLK, and the source of the second MOS tube and the other end of the capacitor C1 are both connected to the ground.

[0014] The non-inverting input terminals of the second comparator and the third comparator are both connected to the source of the first MOS tube, the inverting input terminal of the second comparator is connected to the voltage V TH , and the enable terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL , and the enable terminal of the third comparator is connected to V G-EN ;

[0015] The two input terminals of the OR gate circuit are respectively connected to the output terminals of the second comparator and the third comparator, the output terminal of the OR gate circuit is connected to the input terminal of the buffer circuit BUF, the output terminal of the buffer circuit BUF is connected to the signal input terminal of the D flip-flop, the clock terminal of the D flip-flop is connected to the clock signal CLK, and the output terminal of the D flip-flop outputs V G-EN , V G-EN The signal is outputted through the inverter.

[0016] Optionally, the standby judgment circuit judges whether the switching power supply is in the heavy load state or the light load state in the current period according to the size relationship among V C1 , V TH and V TL . ​

[0017] Optionally, the standby judging circuit comprises: a resistor, an operational amplifier, a MOS transistor, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein,

[0018] The fifth resistor R5 has one end connected to the DEMAG signal and the other end connected to the non-inverting input terminal of the operational amplifier; the source of the first MOS transistor is connected to the inverting input terminal of the operational amplifier; the drain of the first MOS transistor is connected to the output terminal of the operational amplifier; the positive power supply terminal of the operational amplifier is connected to the voltage source VCC; the negative power supply terminal is connected to the ground; the sixth resistor R6 has two ends connected to the inverting input terminal of the operational amplifier and the reference ground, respectively; and the first capacitor C1 has two ends connected to the output terminal and the inverting input terminal of the operational amplifier, respectively.

[0019] The second capacitor C2 has one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to the ground; the drain of the second MOS transistor is connected to the non-inverting input terminal of the operational amplifier; the source of the second MOS transistor is connected to the ground; and the gate of the second MOS transistor and the gate of the first MOS transistor are both connected to the clock signal CLK.

[0020] The non-inverting input terminals of the second comparator and the third comparator are both connected to the output terminal V C1 of the operational amplifier; the inverting input terminal of the second comparator is connected to the voltage V TH ; the enable terminal of the second comparator is connected to The inverting input terminal of the third comparator is connected to the voltage V TL ; and the enable terminal of the third comparator is connected to V G-EN .

[0021] The two input terminals of the OR gate circuit are connected to the output terminals of the second comparator and the third comparator, respectively; the output terminal of the OR gate circuit is connected to the input terminal of the buffer circuit BUF; the output terminal of the buffer circuit BUF is connected to the signal input terminal of the D flip-flop; the clock terminal of the D flip-flop is connected to the clock signal CLK; and the output terminal of the D flip-flop outputs the V G-EN signal, which is inverted by the inverter to obtain the V G-EN signal.

[0022] Optionally, the standby judging circuit determines whether the switching power supply is in a heavy load state or a light load state in the current period according to the size relationship between V C1 , V TH , and V TL .

[0023] Optionally, the standby judging circuit comprises: a resistor, an operational amplifier, a MOS transistor, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein,

[0024] ​One end of the fifth resistor R5 is connected with the DEMAG signal, and the other end is connected with the inverting input terminal of the operational amplifier, the non-inverting input terminal of the operational amplifier is connected with the ground, the positive power supply terminal is connected with the voltage source VCC, the negative power supply terminal is connected with the voltage source -VCC, and the first capacitor C1 is connected with the output terminal and the inverting input terminal of the operational amplifier respectively;

[0025] The drain of the first MOS is connected with the inverting input terminal of the operational amplifier, the source of the first MOS is connected with the output terminal of the operational amplifier, and the gate of the first MOS is connected with the clock signal CLK;

[0026] The inverting input terminals of the second comparator and the third comparator are both connected with the output terminal V C1 of the operational amplifier, the non-inverting input terminal of the second comparator is connected with the voltage -V TH , and the enable terminal of the second comparator is connected with The non-inverting input terminal of the third comparator is connected with the voltage -V TL , and the enable terminal of the third comparator is connected with V G-EN ;

[0027] The two input terminals of the OR gate circuit are connected with the output terminals of the second comparator and the third comparator respectively, the output terminal of the OR gate circuit is connected with the input terminal of the buffer circuit BUF, the output terminal of the buffer circuit BUF is connected with the signal input terminal of the D flip-flop, the clock terminal of the D flip-flop is connected with the clock signal CLK, and the output terminal of the D flip-flop outputs V G-EN , V G-EN signal through the inverter to obtain signal.

[0028] Optionally, the standby judgment circuit determines whether the switching power supply is in the heavy load or light load state in the current period through the size relationship of V C1 , -V TH and -V TL .

[0029] The application further provides a switching power supply, which comprises the above-mentioned switching power supply secondary side synchronous rectification controller.

[0030] Optionally, the switching power supply is a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit or a push-pull converter topology circuit.

[0031] The synchronous rectification controller and the standby mode control circuit thereof provided in the application utilize the demagnetization signal DEMAG generated by detecting the voltage drop of the synchronous rectification MOS, and output V CLK through detecting the length of the DEMAG effective time t on in the fixed time T G_EN .The application judges whether to switch the normal working mode and the standby mode. When the synchronous rectification controller of the application enters light load or no load from heavy load, the synchronous rectification controller is switched from the normal working mode to the standby mode, so that the power consumption of the synchronous rectification controller is reduced, and the system efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 is a schematic block diagram of the secondary side synchronous rectification controller of the switching power supply provided by the application;

[0034] Figure 2 is a schematic diagram of the synchronous rectification controller and the standby mode control principle provided by the application;

[0035] Figure 3 is a key waveform schematic diagram of the normal working mode switching to the standby mode of the synchronous rectification controller of the application when the synchronous rectification controller enters light load or no load from heavy load;

[0036] Figure 4 is a key waveform schematic diagram of the standby mode switching to the normal working mode of the synchronous rectification controller of the application when the synchronous rectification controller enters heavy load from light load or no load;

[0037] Figure 5 is a control flow chart of the synchronous rectification controller provided by the application;

[0038] Figure 6 is another control principle diagram of the synchronous rectification controller and the standby mode provided by the application;

[0039] Figure 7 is still another control principle diagram of the synchronous rectification controller and the standby mode provided by the application. DETAILED DESCRIPTION

[0040] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the technical solutions of the application will be described in detail below with reference to the drawings and specific embodiments. It should be pointed out that the described embodiments are only some embodiments of the application, not all embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0041] Reference Figure 1 , Figure 1is a schematic block diagram of a secondary side synchronous rectification controller of a switching power supply of the application, wherein the switching power supply can be any one of a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit, a push-pull converter topology circuit, and the like, refer to Figure 1 The synchronous rectification controller comprises a demagnetization detection circuit, a standby judgment circuit, an AND gate, and a driving circuit. The input end of the demagnetization detection circuit is connected to one end of a synchronous rectification MOS Q2 of the switching power supply. One output end of the demagnetization detection circuit is connected to one input end of the AND gate circuit. The other output end of the demagnetization detection circuit is connected to the input end of the standby judgment circuit. The output end of the standby judgment circuit is connected to the other input end of the AND gate circuit. The output end of the AND gate circuit is connected to the input end of the driving circuit. The output end of the driving circuit is connected to the gate of the MOS Q2.

[0042] The demagnetization detection circuit is configured to detect a voltage difference VDET between the drain and the source of the MOS Q2. When the VDET is lower than a set threshold value, the demagnetization detection circuit outputs a DEMAG signal through two output ends.

[0043] The standby judgment circuit is configured to integrate the DEMAG signal and compare the integrated signal with a set threshold value to obtain a comparison result. The standby judgment circuit determines whether an output channel Vgate is valid according to the comparison result. G-EN

[0044] The AND gate circuit is configured to output a Vgate signal according to the DEMAG signal and the V G-EN . gate

[0045] The driving circuit is configured to determine whether to output a VG signal to the gate of the MOS Q2 to drive the MOS Q2 according to the V gate .

[0046] The synchronous rectification controller of the application has two working modes: a normal working mode and a standby mode. The demagnetization detection circuit samples a Vds between the two ends of a synchronous rectification MOS Q2 through a VDET pin. When the Vds is lower than a set threshold value, the demagnetization detection circuit outputs a DEMAG signal. The standby judgment circuit integrates the DEMAG signal and compares the integrated signal with a set threshold value to determine whether the current power supply system is in a light load or an empty load, so as to determine whether the synchronous rectification controller enters the standby mode and whether to enable an output signal V G_EN gate. G_EN The Vgate and the DEMAG pass through the AND gate to output the Vgate. The driving circuit strengthens the driving capability on the basis of the Vgate signal to output a VG signal to drive the synchronous rectification MOS Q2.

[0047] Figure 2 ​​The first synchronous rectification controller and standby mode control principle diagram proposed in the application are a further detailed description of the synchronous rectification controller. Figure 1 The synchronous rectification controller. Figure 2 The detailed demagnetization detection circuit principle and standby judgment circuit principle are given. Specifically, the demagnetization detection circuit includes a first comparator, an inverter INV, a resistor, and a reference voltage V DET-ref ; wherein the positive input end of the first comparator is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to VDET, the negative input end of the first comparator is connected to the reference voltage V DET-ref , the two ends of the second resistor R2 are respectively connected to the positive input end and the output end of the first comparator, and the output end of the first comparator outputs the DEMAG signal through the inverter INV.

[0048] The standby judgment circuit includes a current source, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein the drain of the first MOS tube is connected to the current source I charge , the gate of the first MOS tube is connected to the DEMAG signal, the source of the first MOS tube is connected to the drain of the second MOS tube and one end of the capacitor C1, the gate of the second MOS tube is connected to the clock signal CLK, the source of the second MOS tube and the other end of the capacitor C1 are both grounded; the positive input ends of the second comparator and the third comparator are both connected to the source of the first MOS tube, the negative input end of the second comparator is connected to the voltage V TH , the enable end of the second comparator is connected to the negative input end of the third comparator is connected to the voltage V TL , and the enable end of the third comparator is connected to V G-EN ;

[0049] The two input ends of the OR gate circuit are respectively connected to the output ends of the second comparator and the third comparator, the output end of the OR gate circuit is connected to the input end of the buffer circuit BUF, the output end of the buffer circuit BUF is connected to the signal input end of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output end of the D flip-flop outputs V G-EN , the V G-EN signal is output as signal through the inverter.

[0050] As shown in Figure 2 , the demagnetization detection circuit includes R1, R2, comparator 1, and reference voltage V DET_ref . When the sampled VDET voltage rapidly decreases and is lower than (for example, about -85mV), the comparator 1 outputs a low level, and the DEMAG high level is output after the inverter INV, indicating that the demagnetization start is detected. When the sampled VDET voltage gradually rises and is higher than When the voltage is set to about -5mV, the comparator 1 outputs a high level, and after passing through the inverter INV, it outputs a DEMAG low level, indicating that the demagnetization is detected to be completed.

[0051] Figure 2 The principle of the standby judgment circuit is also given. During the demagnetization process, that is, when DEMAG is high, the DEMAG signal drives MOS Q1 to turn on, and the current source I charge Charge capacitor C1, V C1 The rising level is: where t ON is the time duration of DEMAG being high. When DEMAG is low, that is, not in the demagnetization time, MOS Q1 is turned off, and V C1 Each VDET pulse will repeat the above process to achieve V C1 The voltage rises and accumulates during each DEMAG high period. CLK V inside C1 Voltage and set threshold V TL / V TH The relationship between the size of T can be used to determine the heavy load or light load state of the switching power supply in the current cycle, and then control the synchronous rectifier to enter the normal working mode or standby mode. CLK and V TL / V TH Both can be set, which makes it convenient to set different standby mode trigger thresholds in different applications.

[0052] There are four situations in the standby judgment circuit: 1. Entering the standby mode from the normal working mode, that is, V G_EN From the high level of the current cycle to the low level of the next CLK cycle; 2. Maintain normal working mode, that is, maintain the current V G_EN 3. Restore from standby mode to normal working mode, that is, V G_EN From the current cycle low level to the next CLK cycle high level; 4. Keep in standby mode, that is, keep the current V G_EN is low level.

[0053] The first and second cases mentioned above both occur when the current V G_EN When it is high, the synchronous rectifier controller is in normal working mode, and the comparator 3 enables the signal V G_EN High, output valid level, comparator 2 enable signal is low, the output is always low. When the next rising edge of CLK comes, if V C1 >V TL, the comparator 3 output is high, after the or gate and the BUF delay, the VD signal is high, the D flip-flop output V G_EN is high, that is, the second case of the standby judgment circuit: the synchronous rectification controller keeps the normal working mode. When the next CLK rising edge comes, if V C1 ≤ V TL , the comparator 3 output is low, the comparator 2 output is low because the enable signal V is low, the output is always low, after the or gate and the BUF delay, the VD signal is low, the D flip-flop output V G_EN is high to low, that is, the first case of the standby judgment circuit: the synchronous rectification controller enters the standby mode from the normal working mode.

[0054] The third case and the fourth case above both occur when the current V G_EN is low, that is, the current synchronous rectification controller is in the standby mode, the comparator 3 enable signal V G_EN is low, the output is always low, the comparator 2 enable signal V is high, the output is effective. When the next CLK rising edge comes, if V C1 >V TH , the comparator 2 output is high, after the or gate and the BUF delay, the VD signal is high, the D flip-flop output V G_EN is low to high, that is, the third case of the standby judgment circuit: the synchronous rectification controller recovers to the normal working mode from the standby mode. If the next CLK rising edge comes, V C1 ≤ V TH , the comparator 2 output is low, the comparator 3 output is always low because the enable signal V G_EN is low, after the or gate and the BUF delay, the VD signal is low, the D flip-flop output V G_EN is low, that is, the fourth case of the standby judgment circuit: the synchronous rectification controller keeps the standby mode.

[0055] The standby judgment circuit output signal V G_EN and the demagnetization signal DEMAG are input to the AND gate together, the AND gate output V gate is given to the drive circuit. The drive circuit strengthens the driving ability, and outputs a signal VG synchronized with V gate to the synchronous rectification MOS Q2 gate, to control the synchronous rectification MOS switch. The above is the basic principle of the synchronous rectification controller and the standby mode control thereof.

[0056] Figure 3is the key waveform diagram of the synchronous rectifier controller in this application from heavy load to light load or no load, switching from normal mode to standby mode. Time starts at t = 0, CLK sends a pulse signal, which is high when MOS Q2 is opened, discharging C1 capacitor, V C1 is quickly discharged to zero, as shown in the V Figure 3 waveform in the figure. When the CLK pulse is over, every time VDET quickly drops and meets "VDET < V C1 ", the demagnetization signal DEMAG becomes high, and V DET_ref_L is high. At the same time, the demagnetization signal DEMAG high level drives MOS Q1 to open, charging C1 capacitor, V G_EN rises to: , where t gate is the length of time when DEMAG is high. When DEMAG is low, i.e. not in demagnetization time, MOS Q1 is closed, and V C1 remains unchanged. Every VDET pulse will repeat the above process, so that V ON is realized. C1 The voltage rises during each DEMAG high period. Until the next CLK rising edge comes, V C1 accumulates rise, which does not exceed V TL , and D flip-flop output V G_EN changes from high to low, and remains low before the next CLK arrives, realizing the synchronous rectifier controller switching from normal mode to standby mode.

[0057] Figure 4 is the key waveform diagram of the synchronous rectifier controller in this application from light load or no load to heavy load, switching from standby mode to normal mode. Time starts at t = 0, CLK sends a pulse signal, which is high when MOS Q2 is opened, discharging C1 capacitor, V C1 is quickly discharged to zero, as shown in the V C1 waveform in the figure. When the CLK pulse is over, every time VDET quickly drops and meets "VDET < V DET_ref_L ", the demagnetization signal DEMAG becomes high, driving MOS Q1 to open, charging C1 capacitor, V C1 rises to: , where t ON is the length of time when DEMAG is high. When DEMAG is low, i.e. not in demagnetization time, MOS Q1 is closed, and V C1 remains unchanged. Every VDET pulse will repeat the above process, so that V C1The voltage rises up during each DEMAG high level. Until the next CLK rising edge comes, V C1 The rising edge is accumulated and V C1 >V TH The D flip-flop output V G_EN is changed from low to high and keeps high until the next CLK comes, realizing the synchronous rectification controller switching from standby mode to normal working mode.

[0058] Figure 5 is the control flow chart of the synchronous rectification controller proposed in the present application. The specific implementation circuit and principle of the flow chart follow Figure 1 the synchronous rectification controller block diagram and Figure 2 the proposed synchronous rectification controller and its standby mode control principle. The detailed control flow steps are as follows:

[0059] Step 1: start;

[0060] Step 2: power-on reset, initialize the sampling module, initialize each part of the logic circuit, and default VG as low level;

[0061] Step 3: enter normal working mode, CLK outputs a pulse, V C1 is cleared, V G_EN is enabled, and VG normally outputs;

[0062] Step 4: VDET detects the demagnetization time, and charges C1 in the demagnetization time;

[0063] Step 5: T CLK timing ends, at the next CLK pulse rising edge, judges whether V C1 is less than V TL . If yes, execute step 6; if not, execute step 3;

[0064] Step 6: enter standby mode, CLK outputs a pulse, V C1 is cleared, V G_EN is not enabled, and VG has no output;

[0065] Step 7: VDET detects the demagnetization time, and charges C1 in the demagnetization time;

[0066] Step 8: T CLK timing ends, at the next CLK pulse rising edge, judges whether V C1 is greater than V TH . If yes, execute step 3; if not, execute step 6.

[0067] Figure 6 is another control principle diagram of the synchronous rectification controller proposed in the present application and its standby mode, the demagnetization detection circuit and Figure 2The first synchronous rectifier controller and standby mode control principle thereof are proposed Figure 1 The difference lies in Figure 2 The standby judgment circuit in the middle adopts DEMAG control I charge Charging the capacitor C1, realizing That is, V C1 And t on Proportional to the first function relationship. As Figure 6 The standby judgment circuit shown in the figure comprises a resistance, an operational amplifier, a MOS tube, a clock signal CLK, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein one end of a fifth resistance R5 is connected with a DEMAG signal, the other end is connected with a positive input end of the operational amplifier, a source of a first MOS tube is connected with a negative input end of the operational amplifier, a drain of the first MOS tube is connected with an output end of the operational amplifier, a positive power supply end of the operational amplifier is connected with a voltage source VCC, and a negative power supply end is grounded, two ends of a sixth resistance R6 are respectively connected with the negative input end of the operational amplifier and a reference ground, two ends of a first capacitor C1 are respectively connected with the output end and the negative input end of the operational amplifier; one end of a second capacitor C2 is connected with the positive input end of the operational amplifier, the other end of the second capacitor C2 is grounded, a drain of a second MOS tube is connected with the positive input end of the operational amplifier, a source of the second MOS tube is grounded, a gate of the second MOS tube and a gate of the first MOS tube are both connected with the clock signal CLK; positive input ends of a second comparator and a third comparator are both connected with the output end V C1 Of the operational amplifier, a negative input end of the second comparator is connected with a voltage V TH , an enable end of the second comparator is connected with A negative input end of the third comparator is connected with a voltage V TL , an enable end of the third comparator is connected with V G-EN ; two input ends of the OR gate circuit are respectively connected with an output end of the second comparator and an output end of the third comparator, an output end of the OR gate circuit is connected with an input end of the buffer circuit BUF, an output end of the buffer circuit BUF is connected with a signal input end of the D flip-flop, a clock port of the D flip-flop is connected with the clock signal CLK, an output end of the D flip-flop outputs V G-EN , the V G-EN signal obtains a signal through the inverter.

[0068] As Figure 6 shown, Figure 6 The standby judgment circuit in the middle is replaced by a positive phase integral circuit composed of an operational amplifier, R5, C2, Q2, R6, C1, and Q1, and R5*C2=R6*C1 is taken, so that V C1 and t on are proportional to the first function relationship, wherein V DEMAGDEMAG high level time voltage value. When the value is , the second synchronous rectification controller and standby mode control principle proposed in the application can realize the same function as the first synchronous rectification controller and standby mode control principle Figure 1 , the key waveform reference Figure 3 and Figure 4 .

[0069] Figure 7 is another control principle diagram of the synchronous rectification controller and standby mode proposed in the application. The demagnetization detection circuit is the same as Figure 2 , Figure 6 the synchronous rectification controller and standby mode control principle proposed in the application Figure 1 , as shown in the standby judgment circuit Figure 7 , including: resistors, operational amplifiers, MOS transistors, comparators, capacitors, OR gate circuits, buffer circuits BUF, D flip-flops, inverters; wherein one end of the fifth resistor R5 is connected to the DEMAG signal, the other end is connected to the inverting input terminal of the operational amplifier, the non-inverting input terminal of the operational amplifier is connected to ground, the positive power supply terminal is connected to the voltage source VCC, the negative power supply terminal is connected to the voltage source -VCC, and the two ends of the first capacitor C1 are respectively connected to the output terminal and the inverting input terminal of the operational amplifier; the drain of the first MOS transistor is connected to the inverting input terminal of the operational amplifier, the source of the first MOS transistor is connected to the output terminal of the operational amplifier, and the gate of the first MOS transistor is connected to the clock signal CLK; the inverting input terminals of the second comparator and the third comparator are both connected to the output terminal V C1 of the operational amplifier, the non-inverting input terminal of the second comparator is connected to the voltage -V TH , the enable terminal of the second comparator is connected to the non-inverting input terminal of the third comparator is connected to the voltage -V TL , the enable terminal of the third comparator is connected to V G-EN ; the two input terminals of the OR gate circuit are respectively connected to the output terminals of the second comparator and the third comparator, the output terminal of the OR gate circuit is connected to the input terminal of the buffer circuit BUF, the output terminal of the buffer circuit BUF is connected to the signal input terminal of the D flip-flop, the clock port of the D flip-flop is connected to the clock signal CLK, and the output terminal of the D flip-flop outputs V G-EN , V G-EN signal through the inverter to obtain signal.

[0070] Referring to Figure 7 , the difference is that the standby judgment circuit in Figure 2 uses DEMAG control I charge to charge the capacitor C1, so as to realize that V C1 is proportional to t on ; Figure 7The positive phase integration circuit is composed of an operational amplifier, R5, C2, Q2, R6, C1 and Q1, and R5*C2=R6*C1, so that V C1 is proportional to t on , where V DEMAG is the voltage value of DEMAG high level. Figure 7 The negative phase integration circuit is composed of an operational amplifier, R5, C1 and Q1, so that V C1 is inversely proportional to t on , where V DEMAG is the voltage value of DEMAG high level. Since the output VC1 of the negative phase integration circuit is negative, the input conditions of the comparator 2 and the comparator 3 need to be adjusted accordingly: the input reference value is changed from V TL / V TH to (-V TL ) / (-V TH ), and the input reference value is set to the positive input of the comparator, and V C1 is the negative input. The standby judgment circuit other parts are consistent with Figure 2 , Figure 6 and realize the same function.

[0071] In summary, the synchronous rectification controller and the standby mode control circuit thereof utilize the demagnetization signal DEMAG generated by detecting the voltage drop across the synchronous rectification MOS, and output V CLK according to the length of the effective time t on of DEMAG in the fixed time T G_EN , to determine whether to switch to the normal working mode or the standby mode. When the synchronous rectification controller of the application switches from heavy load to light load or no load, it switches from the normal working mode to the standby mode, which can reduce the power consumption of the synchronous rectification controller and improve the system efficiency.

[0072] The application provides three representative synchronous rectification controllers and standby mode control circuits thereof, which are only preferred embodiments and are not used to limit the application. Any modification, replacement, improvement, etc. within the design principles and spirit of the application is within the protection scope of the application.

Claims

1. A secondary side synchronous rectification controller for a switching power supply, characterized by, The synchronous rectification controller comprises a demagnetization detection circuit, a standby judgment circuit, an AND gate circuit and a driving circuit; wherein one end of the synchronous rectification MOS Q2 of the switching power supply is connected to the input end of the demagnetization detection circuit, one output end of the demagnetization detection circuit is connected to one input end of the AND gate circuit, the other output end of the demagnetization detection circuit is connected to the input end of the standby judgment circuit, the output end of the standby judgment circuit is connected to the other input end of the AND gate circuit, the output end of the AND gate circuit is connected to the input end of the driving circuit, and the output end of the driving circuit is connected to the gate of the MOS Q2; The demagnetization detection circuit is used for detecting the voltage difference VDET between the drain and the source of the MOS Q2, and outputs a DEMAG signal through two output ends when the VDET is lower than a set threshold value; The standby judging circuit is used to integrate the DEMAG signal and compare the result with a set threshold to obtain a comparison result, and determine an output signal V G-EN whether it is valid or not; The AND gate circuit is used for outputting V G-EN output V gate signal; The driving circuit is used for judging whether to output the VG signal to the gate of the MOS Q2 to drive the MOS Q2 according to the V gate The signal judges whether to output the VG signal to the gate of the MOS Q2 to drive the MOS Q2. The standby judgment circuit comprises a resistor, an operational amplifier, a MOS tube, a comparator, a capacitor, an OR gate circuit, a buffer circuit BUF, a D flip-flop, and an inverter; wherein One end of the fifth resistor R5 is connected to the DEMAG signal, the other end is connected to the inverting input end of the operational amplifier, the non-inverting input end of the operational amplifier is connected to the ground, the positive power supply end is connected to the voltage source VCC, the negative power supply end is connected to the voltage source -VCC, and the two ends of the first capacitor C1 are respectively connected to the output end and the inverting input end of the operational amplifier; The drain of the first MOS tube is connected to the inverting input end of the operational amplifier, the source of the first MOS tube is connected to the output end of the operational amplifier, and the gate of the first MOS tube is connected to the clock signal CLK; The inverting input terminals of the second comparator and the third comparator are both connected to the output terminal V C1 of the operational amplifier. The non-inverting input terminal of the second comparator is connected to voltage -V TH . The enable terminal of the second comparator is connected to V . The non-inverting input terminal of the third comparator is connected to voltage -V TL . The enable terminal of the third comparator is connected to V G-EN . Two input terminals of the or gate circuit are connected with the output terminals of the second comparator and the third comparator respectively, an output terminal of the or gate circuit is connected with an input terminal of a buffer circuit BUF, an output terminal of the buffer circuit BUF is connected with a signal input terminal of a D flip-flop, a clock port of the D flip-flop is connected with the clock signal CLK, and an output terminal of the D flip-flop outputs V G-EN , V G-EN . The signal passes through an inverter to obtain a signal.

2. The switching power supply secondary side synchronous rectification controller according to claim 1, characterized in that, The demagnetization detection circuit comprises a first comparator, an inverter INV, a resistor and a reference voltage V DET-ref ; wherein, The positive input terminal of the first comparator is connected to one end of a first resistor R1, the other end of the first resistor R1 is connected to the VDET, the inverting input terminal of the first comparator is connected to a reference voltage V DET-ref , two ends of a second resistor R2 are respectively connected to the positive input terminal and the output terminal of the first comparator, and the output terminal of the first comparator outputs a DEMAG signal through an inverter INV.

3. The secondary side synchronous rectification controller of the switching power supply according to claim 1, characterized in that The standby judging circuit judges the heavy or light load state of the switching power supply in the current period by the size relation of V C1 and -V TH , -V TL .

4. A switching power supply, characterized by comprising: The switching power supply comprises the secondary side synchronous rectification controller of the switching power supply according to any one of claims 1-3.

5. The switching power supply of claim 4, wherein The switching power supply is a flyback converter topology circuit, a forward converter topology circuit, an LLC converter topology circuit, a half-bridge converter topology circuit, a full-bridge converter topology circuit or a push-pull converter topology circuit.

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