A multi-functional configurable encoder and encoding method

Abstract

The present application discloses a multifunctional configurable encoder and an encoding method, relating to the fields of transmission and IP. It includes: a bus interface connected to a register and an encoding module. The encoding module includes a plurality of encoding modules connected in a preset order, and a logic control module for controlling the switching logic of the encoding modules. The plurality of encoding modules connected in a preset order respectively adopt different encoding methods; the register is used to store the control parameters received through the bus interface and send them to the encoding module; the encoding module is used to receive the data to be encoded. The logic control module selects at least one encoding module according to the logic control parameters in the control parameters, and the selected encoding module encodes according to the preset encoding order based on the corresponding encoding parameters in the control parameters. The present application can meet the usage requirements in different scenarios only by configuring relevant parameters, and has a wider application scenario.

Description

Technical Field

[0001] This application relates to the fields of transmission and IP, and particularly to a multi-functional configurable encoder and an encoding method. Technical Background

[0002] Existing encoding technologies are relatively mature. However, common encoders usually only have one encoding function. Encoders with single functions are greatly restricted by the usage environment and protocol system in practical applications and are not suitable for the requirements of flexible configuration and multi-encoding function combination. Moreover, no solution has been proposed for the serial-to-parallel combination in CRC encoding, and the design of encoders with multiple encoding methods and suitable for satellite communication is still relatively rare. Summary of the Invention

[0003] The purpose of this application is to provide a multi-functional configurable encoder and an encoding method. To solve the problem that the encoder can only perform single-function encoding, this application has multiple encoding methods, and only by configuring relevant parameters can it meet the usage requirements in different scenarios, with a wider range of application scenarios.

[0004] In a first aspect, this application provides a multi-functional configurable encoder, including:

[0005] A bus interface, connected to a register and an encoding module. The encoding module includes a plurality of encoding modules connected in a preset order, and a logic control module for controlling the switching logic of the encoding modules. The plurality of encoding modules connected in a preset order respectively adopt different encoding methods;

[0006] A register, used to store the control parameters received through the bus interface and send them to the encoding module. The control parameters include the logic control parameters sent to the logic control module and the encoding parameters sent to the encoding modules;

[0007] An encoding module, used to receive the data to be encoded. The logic control module selects at least one encoding module according to the logic control parameters, and the selected encoding module encodes according to the corresponding encoding parameters in a preset encoding order.

[0008] In one or more possible embodiments, the logic control module includes a plurality of multiplexers;

[0009] One of the multiplexers serves as the first-level multiplexer. The input is connected to the bus interface and the first-level encoding module, and the output is connected to the next-level multiplexer and the next-level encoding module. The first-level multiplexer selects to output the data to be encoded received from the bus interface or the data encoded by the first-level encoding module to the next-level multiplexer and the next-level encoding module according to the logic control parameters;

[0010] One of the multiplexers serves as the last-stage multiplexer, with its input connected to the output of the previous-stage multiplexer and the last-stage encoding module. The last-stage multiplexer selects and outputs the data from the output of the previous-stage multiplexer or the data from the output of the last-stage encoding module according to the logical control parameter.

[0011] When at least one intermediate multiplexer is further connected between the input multiplexer and the output multiplexer, the input of the intermediate multiplexer is connected to the output of the previous-stage multiplexer and the output of the encoding module at the same level as the intermediate multiplexer, and the output is connected to the next-stage multiplexer and the next-stage encoding module. The intermediate input multiplexer outputs the data received from the previous-stage multiplexer or the data encoded by the encoding module at the same level as the intermediate multiplexer to the next-stage multiplexer and the next-stage encoding module according to the logical control parameter.

[0012] In one or more possible embodiments, the bus interface includes an APB bus and an AXI bus;

[0013] The APB bus is connected to the register and is used to transmit control parameters to the register;

[0014] The AXI bus is connected to the encoding module and is used to transmit data to be encoded to the encoding module.

[0015] In one or more possible embodiments, the data to be encoded includes multiple frames to be encoded, and the encoding parameters in the control parameters include at least one of the following parameters:

[0016] The total length of the frames to be encoded, the first data of the encoded frame, the last data of the encoded frame, the actual input frame length of each encoding module, and the actual output frame length.

[0017] In one or more possible embodiments, the multiple encoding modules connected in a preset order include any combination of the following encoding modules:

[0018] CRC and masking encoding module using cyclic redundancy check encoding method, rate matching Turbo encoding module, interleaving encoding module, scrambling encoding module.

[0019] In one or more possible embodiments, the encoding module includes a CRC and masking encoding module, where:

[0020] The CRC and masking encoding module encodes the data to be encoded in byte-integer multiples using a parallel CRC encoding method and encodes the data to be encoded in non-byte-integer multiples using a serial CRC encoding method according to the corresponding encoding parameters.

[0021] In one or more possible embodiments, the register includes a START register for storing the START signal. Before storing the START signal, the START register sends the logic control parameters to the logic control module and sends the encoding parameters to the encoding module.

[0022] In one or more possible embodiments, the encoding module includes a rate-matched Turbo encoding module, and the rate-matched Turbo encoding module selects a single-component convolutional encoder.

[0023] In one or more possible embodiments, the rate-matched Turbo encoding module further includes an interleaver, a rate-matching module, and a data merging module. The interleaver is used to interleave the data to be encoded. The data to be encoded and the interleaved data obtained after the interleaving process by the interleaver are respectively input into the single-component convolutional encoder for encoding according to the time sequence. The rate-matching module performs operations of generating tail bits and rate matching on the encoded data, and merges the data after rate matching with the data to be encoded and then outputs.

[0024] In a second aspect, the present application further provides a multifunctional configurable encoding method, and the method includes:

[0025] Writing the corresponding control parameters to the register through the bus interface and sending them to the encoding module connected to the register. The control parameters include the logic control parameters sent to the logic control module of the encoding module and the encoding parameters during encoding of the encoding module of the encoding module;

[0026] Receiving the data to be encoded through the encoding module;

[0027] The logic control module selects at least one encoding module according to the logic control parameters;

[0028] The selected encoding module encodes according to the preset encoding sequence based on the corresponding encoding parameters.

[0029] In one or more possible embodiments, the logic control module includes a first-stage multiplexer, an intermediate multiplexer, and a last-stage multiplexer. The logic control module selects at least one encoding module according to the logic control parameters, including:

[0030] According to the logic control parameters, the first-stage multiplexer selects to output the data to be encoded received from the bus interface or the data encoded by the first-stage encoding module to the next-stage multiplexer and the next-stage encoding module;

[0031] According to the logic control parameters, the intermediate multiplexer outputs the data received from the previous-stage multiplexer or the data encoded by the encoding module at the same level as the intermediate multiplexer to the next-stage multiplexer and the next-stage encoding module;

[0032] According to the logic control parameter, the last - stage multiplexer selects to output the data output by the previous - stage multiplexer or the data output by the last - stage encoding module.

[0033] In one or more possible embodiments, the selected encoding modules include any combination of the following encoding modules:

[0034] CRC and masking encoding module using cyclic redundancy check encoding method, rate - matching Turbo encoding module, interleaving encoding module, scrambling encoding module.

[0035] In one or more possible embodiments, the selected encoding module includes a CRC and masking encoding module, and the CRC and masking encoding module encodes in the following manner:

[0036] Encode the data to be encoded input according to the corresponding encoding parameters. For the data to be encoded that is an integer multiple of bytes, parallel CRC encoding is used for encoding, and for the data to be encoded that is not an integer multiple of bytes, serial CRC encoding is used for encoding.

[0037] This application provides a multi - functional configurable encoder and an encoding method, which has multiple encoding methods. Only by configuring relevant control parameters can it meet the usage requirements of multiple scenarios, and the application scenarios are more extensive. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application, and do not constitute an improper limitation of this application.

[0039] Figure 1 It is a schematic diagram of the application environment provided according to an embodiment of this application;

[0040] Figure 2 It is a schematic diagram of the module provided according to an embodiment of this application;

[0041] Figure 3 It is a schematic diagram of the micro - architecture of the multi - functional configurable encoder provided according to an embodiment of this application;

[0042] Figure 4 It is a schematic diagram of the micro - architecture of one of the encoding modules of the multi - functional configurable encoder provided according to an embodiment of this application;

[0043] Figure 5 It is a schematic diagram of the service process of the multi - functional configurable encoder provided according to an embodiment of this application;

[0044] Figure 6Flowchart of a multi-functional configurable encoding method provided according to an embodiment of the present application. Detailed implementation manners

[0045] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] Traditional encoders only have a single encoding function and are greatly restricted by the usage environment and protocol system in practical applications. They are not applicable in the case of flexible configuration and multi-encoding function combination requirements. To enable an encoder to have multiple encoding functions, the present application provides a multi-functional configurable encoder and encoding method. This solution can be applied to terminal devices in a network communication system or network-side devices. A possible application scenario is a satellite communication system. Of course, it can also be applied in more scenarios.

[0047] See Figure 1 , which is a schematic diagram of an application environment according to an embodiment of the present application. The application environment includes multiple satellites located on the orbital plane in a satellite communication system and terminals communicating with the satellites. Exemplarily, it includes satellites 102_1, 102_2, ……, 102_N in the figure, where N is a positive integer, and the size of N is determined according to specific requirements and scenarios in practice. The terminal 101 communicates with other target terminals 103 through the satellites.

[0048] See Figure 2 , which is a schematic diagram of a multi-functional configurable encoder according to an embodiment provided by the present application, including: a bus interface 201, a register 202, and an encoding module 203, where:

[0049] The bus interface 201 is connected to an external terminal CPU, receives signals transmitted by the external CPU, and feeds back signals to the CPU to realize interaction with the CPU. At the same time, it is connected to the register 202 and the encoding module 203. The encoding module 203 includes multiple encoding modules 203a connected in a preset order and a logic control module 203b for controlling the switching logic of the encoding modules 203a. The multiple encoding modules 203a connected in a preset order respectively adopt different encoding methods, which can meet the data encoding work under different protocol systems;

[0050] The number of the above-mentioned encoding modules 203a can be designed according to requirements, and the order of the encoding modules 203a can also be designed according to actual applications. The above-mentioned logic control module 203b and the encoding module 203a are in a one-to-one correspondence relationship. In a multi-functional configurable encoder, it includes multiple levels of logic control modules 203b and encoding modules 203a. The above-mentioned logic control module 203b can independently control whether each encoding module 203a encodes the received data. When encoding the received data, it encodes the received data and then sends it. If the received data does not need to be encoded, the above-mentioned data skips the encoding of this encoding module 203a and is sent to the next-level encoding module.

[0051] The register 202 is used to store the control parameters received through the bus interface 201 and send them to the encoding module 203. The control parameters include the logic control parameters sent to the logic control module 203b and the encoding parameters sent to the encoding module 203a.

[0052] The above-mentioned logic control parameters are sent to the logic control module 203b, which can decide whether to execute the encoding function of the encoding module 203a. The data to be encoded includes multiple frames to be encoded. The above-mentioned encoding parameters include at least one of the following parameters: the total length of the frames to be encoded, the first data of the encoded frame, the last data of the encoded frame, the actual input frame length of each encoding module, and the actual output frame length. And the above-mentioned control parameters can all be directly configured through the bus.

[0053] The encoding module 203 is used to receive the data to be encoded. The logic control module 203b selects at least one encoding module 203a according to the logic control parameters, and the selected encoding module 203a encodes according to the preset encoding order and the corresponding encoding parameters.

[0054] According to a multi-functional configurable encoder provided by the present application, different encoding methods can be performed in one encoder, and flexible configuration can also be performed. Select the required encoding function according to your own needs, control according to the control parameters, and select the required encoding method in the actual situation for encoding.

[0055] In one or more possible embodiments, the logic control module includes multiple multiplexers.

[0056] One of the multiplexers serves as the first-stage multiplexer. The input of the first-stage multiplexer is connected to the bus interface and the first-stage encoding module. When the data to be encoded enters the encoding module, it is simultaneously sent to the first-stage multiplexer and the first-stage encoding module. After the data to be encoded is encoded by the first encoding module, the output data is also sent to the first-stage multiplexer. The output of the first-stage multiplexer is connected to the next-stage multiplexer and the next-stage encoding module. According to the logical control parameters, it is selected to send the data to be encoded or the data that has been encoded by the first-stage encoding module to the next-stage multiplexer and the next-stage encoding module. Therefore, through the first-stage multiplexer, it can be determined whether the first-stage encoding module participates in data encoding;

[0057] One of the multiplexers serves as the last-stage multiplexer. The input is connected to the output of the previous-stage multiplexer and the last-stage encoding module. The last-stage multiplexer selects to output the data output by the previous-stage multiplexer or the data output by the last-stage encoding module according to the logical control parameters. Therefore, through the last-stage multiplexer, it can be determined whether the last encoding module participates in data encoding;

[0058] In the embodiments of the present application, the number of encoding modules may be two or more, and the number of encoding modules is the same as the number of multiplexers. If at least one intermediate multiplexer is also connected between the first-stage multiplexer and the last-stage multiplexer, the input of the intermediate multiplexer is connected to the output of the previous-stage multiplexer and the output of the encoding module at the same level as the intermediate multiplexer, and the output is connected to the next-stage multiplexer and the next-stage encoding module. The intermediate multiplexer outputs the data received from the previous-stage multiplexer or the data encoded by the encoding module at the same level as the multiplexer to the next-stage multiplexer and the next-stage encoding module according to the logical control parameters. Therefore, the intermediate multiplexer can determine whether the data selected and output by the previous-stage multiplexer and the encoding module at the same level as the intermediate multiplexer participate in data encoding.

[0059] The multiplexer in the present application can perform switch control on the data path, and can select different encoding functions. After the control parameters are configured, the data to be encoded will only flow according to the path controlled by the control parameters, greatly improving the flexibility of the encoding method. Multiple different encoding methods can be configured to adapt to different working environments.

[0060] In one or more possible embodiments, a plurality of encoding modules connected in a preset order include any combination of the following encoding modules: a CRC and masking encoding module using cyclic redundancy check encoding, a rate-matching Turbo encoding module, an interleaving encoding module, and a scrambling encoding module. In addition to these four encoding modules, there may also be encoding modules with other encoding methods. Among them, the CRC and masking encoding module encodes the data to be encoded in the byte-integer multiple part using parallel CRC encoding according to the corresponding encoding parameters, and encodes the data to be encoded in the non-byte-integer multiple part using serial CRC encoding. This can support the encoding of data of any length. At the same time, compared with traditional encoding methods, the CRC encoding method greatly improves the processing speed of the data to be encoded and can be applied in more environments to meet the requirements of more scenarios, greatly improving flexibility and adaptability.

[0061] In summary, the present application provides a multifunctional configurable encoder. In one or more possible embodiments, as Figure 3 shown, there are a total of four multiplexers and four encoding modules, including: a bus interface 301, a register array 302, four encoding modules, and four logic control modules;

[0062] The above-mentioned bus interface 301 includes an APB bus and an AXI bus. The APB bus is connected to the register and is used to transmit control parameters to the register; the AXI bus is connected to the encoding module and is used to transmit the data to be encoded to the encoding module; selecting two different buses enables it to be directly used on the above AMBA bus, meeting the encoding requirements under different protocol systems and having a wider usage environment.

[0063] The above four encoding modules include: a CRC and masking encoding module, a rate-matching Turbo encoding module, an interleaving encoding module, and a scrambling encoding module; the above CRC and masking encoding module is the first-level encoding module 3031, the rate-matching Turbo encoding module is the second-level encoding module 3032, the interleaving encoding module is the third-level encoding module 3033, and the scrambling encoding module is the fourth-level encoding module 3034;

[0064] The above four multiplexers include: a first-level multiplexer 3041, a second-level multiplexer 3042, a third-level multiplexer 3043, and a fourth-level multiplexer 3044. The above second-level and third-level multiplexers are intermediate multiplexers, and the fourth-level multiplexer is the last-level multiplexer; the above multiplexers and the above encoding modules are in one-to-one correspondence.

[0065] In one or more possible embodiments, as Figure 4As shown, when data is input into the rate matching Turbo coding module from the upper-level multiplexer, the above rate matching Turbo coding module selects a single-component convolutional encoder, which saves resources while ensuring the coding efficiency. The above rate matching Turbo coding module further includes an interleaver, a rate matching module and a data merging module. First, the data to be encoded X1 is input into the above component convolutional encoder for encoding. The above interleaver is used to interleave the data to be encoded X1. The interleaved data X2 is obtained after the data to be encoded X1 is interleaved by the above interleaver. The data to be encoded X1 and the interleaved data X2 are respectively input into the single-component convolutional encoder for encoding according to the time sequence. The data P1 is output after the data to be encoded X1 is encoded. The data P2 is output after the interleaved data X2 is encoded. The data P1 and the data P2 perform tail bit generation operations in the same order to perform rate matching. The data P1 and the data P2 output one path of data in sequence through the above rate matching module, and the output one path of data is merged with the data to be encoded X1 in the above data merging module, and finally the processed data is output. The processing of the above tail bit generation and rate matching is the same as the prior art and will not be elaborated here.

[0066] Compared with the existing technology, this application has multiple coding methods and can be flexibly configured through the above multiplexer, with less restrictions in the actual usage environment and protocol system. At the same time, this application also proposes a parallel-to-serial combination scheme for CRC coding. Generally, CRC coding is based on the data frame length with bytes as the base. However, in actual applications, there are indeed data frame lengths that are not integer multiples of bytes. In this case, the parallel-to-serial combination scheme for CRC coding in this application can be used for coding processing, which improves the processing speed of the data to be encoded and can be used in more scenarios.

[0067] At the same time, this application can be used as a basic platform for upgrading and optimization, with a large room for improvement. For example, a ping-pong mechanism can be added in the required scenario to accelerate the processing of the data to be encoded, thereby improving the coding speed of this application. Other coding modules not available in this application can also be added to meet more usage scenarios.

[0068] In one or more possible embodiments, the register includes a register for storing control parameters, a START register for storing the START signal, and a status monitoring register.

[0069] The register for storing control parameters is used to store the control parameters received through the APB bus interface and send them to the coding module. The control parameters include the logic control parameters sent to the logic control module and the coding parameters sent to the coding module. There can be multiple registers for storing control parameters, which respectively store different types of parameters.

[0070] The START register stores the START signal. Before storing the START signal, logical control parameters are sent to the multiplexer, and encoding parameters are sent to the encoding module. The START register can be used as a signal register indicating that the configuration is complete and the function is started.

[0071] The status monitoring register is used to understand the actual operating status of the IP, so that new operation processes can be carried out.

[0072] The above three registers have different functions. When configuring the encoded data, the control parameters are sent through the APB bus to the register storing the control parameters, and the register storing the control parameters sends the control parameters to the encoding module. When the control parameter sending is completed, the START register storing the START signal sends the START signal. The START signal is used as a signal to start the configuration completion status, and the encoding module starts encoding according to the control parameters. When the encoding is in progress, the status monitoring register starts to work to understand the actual operating status of the IP.

[0073] A multifunctional configurable encoder according to the present application is specifically shown in Figure 5 , which is the service flow chart of the present application;

[0074] Step S501: Configure the control parameters through the APB bus;

[0075] Step S502: The register storing the parameters receives the control parameters and sends them to the encoding module;

[0076] Step S503: Read the data to be encoded through the AXI bus;

[0077] Step S504: Feed the data to be encoded into the encoding module for encoding;

[0078] Step S505: Write out the encoded data through the AXI bus.

[0079] Based on the same inventive concept, an embodiment of the present application provides a multifunctional configurable encoding method. As Figure 6 shown in the flowchart of the multifunctional configurable encoding method, it includes:

[0080] Step S601: Write the corresponding control parameters to the register through the bus interface and send them to the encoding module connected to the register. The control parameters include the logical control parameters sent to the logical control module of the encoding module and the encoding parameters during encoding sent to the encoding module of the encoding module;

[0081] Step S602: Receive the data to be encoded through the encoding module;

[0082] Step S603: The logic control module selects at least one encoding module according to the logic control parameters.

[0083] Step S604: The selected encoding module performs encoding according to the corresponding encoding parameters in the preset encoding order.

[0084] In one or more possible embodiments, the logic control module includes a first-stage multiplexer, an intermediate multiplexer, and a last-stage multiplexer. The logic control module selects at least one encoding module according to the logic control parameters, including:

[0085] According to the logic control parameters, the first-stage multiplexer selects the data to be encoded received from the bus interface or the data encoded by the first-stage encoding module, and outputs it to the next-stage multiplexer and the next-stage encoding module.

[0086] According to the logic control parameters, the intermediate multiplexer outputs the data received from the previous-stage multiplexer or the data encoded by the encoding module at the same level as the intermediate multiplexer to the next-stage multiplexer and the next-stage encoding module.

[0087] According to the logic control parameters, the last-stage multiplexer selects to output the data output by the previous-stage multiplexer or the data output by the last-stage encoding module.

[0088] In one or more possible embodiments, the selected encoding module includes any combination of the following encoding modules:

[0089] CRC and masking encoding module with cyclic redundancy check encoding method, rate-matching Turbo encoding module, interleaving encoding module, scrambling encoding module.

[0090] In one or more possible embodiments, the selected encoding module includes a CRC and masking encoding module, and the CRC and masking encoding module encodes in the following manner:

[0091] Encode the input data to be encoded according to the corresponding encoding parameters. For the data to be encoded in integer multiples of bytes, use parallel CRC encoding; for the data to be encoded that is not an integer multiple of bytes, use serial CRC encoding.

[0092] According to a multifunctional configurable encoder and encoding method provided by the present application, the problem that the encoder can only perform single-function encoding is solved. The present application has multiple encoding methods, and only by configuring relevant parameters can it meet the usage requirements in different scenarios, making the application scenarios more extensive.

[0093] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0094] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0095] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means realizes the functions specified in Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0097] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A multi-functional configurable encoder, characterized in that, The encoder includes: A bus interface, connected to a register and an encoding module. The encoding module includes a plurality of encoding modules connected in a preset order, and a logic control module for performing switch logic control on the encoding modules. The plurality of encoding modules connected in the preset order respectively adopt different encoding methods. The encoding module includes a CRC and masking encoding module, where: the CRC and masking encoding module encodes the data to be encoded in the byte-integer multiple part using a parallel CRC encoding method according to the corresponding encoding parameters, and encodes the data to be encoded in the non-byte-integer multiple part using a serial CRC encoding method, for supporting encoding of data to be encoded with any length; The register is used to store the control parameters received through the bus interface and send them to the encoding module. The control parameters include the logic control parameters sent to the logic control module and the encoding parameters sent to the encoding module; The encoding module is used to receive the data to be encoded. The logic control module selects at least one encoding module according to the logic control parameters, and the selected encoding module encodes according to the preset encoding order and the corresponding encoding parameters.

2. The encoder according to claim 1, wherein The logic control module includes a plurality of multiplexers; One of the multiplexers is used as the first-level multiplexer. The input is connected to the bus interface and the first-level encoding module, and the output is connected to the next-level multiplexer and the next-level encoding module. The first-level multiplexer selects to output the data to be encoded received from the bus interface or the data encoded by the first-level encoding module to the next-level multiplexer and the next-level encoding module according to the logic control parameters; One of the multiplexers is used as the last-level multiplexer. The input is connected to the output of the previous-level multiplexer and the output of the last-level encoding module. The last-level multiplexer selects to output the data output by the previous-level multiplexer or the data output by the last-level encoding module according to the logic control parameters; When at least one intermediate multiplexer is further connected between the first-level multiplexer and the last-level multiplexer, the input of the intermediate multiplexer is connected to the output of the previous-level multiplexer and the output of the encoding module at the same level as the intermediate multiplexer, and the output is connected to the next-level multiplexer and the next-level encoding module. The intermediate multiplexer outputs the data received from the previous-level multiplexer or the data encoded by the encoding module at the same level as the intermediate multiplexer to the next-level multiplexer and the next-level encoding module according to the logic control parameters.

3. The encoder according to claim 1 or 2, characterized in that, The bus interface includes an APB bus and an AXI bus; The APB bus is connected to the register and is used to transmit the control parameters to the register; The AXI bus is connected to the encoding module and is used to transmit the data to be encoded to the encoding module.

4. The encoder according to claim 1 or 2, characterized in that, The data to be encoded includes a plurality of frames to be encoded. The encoding parameters in the control parameters include at least one of the following parameters: The total length of the frame to be encoded, the first data of the encoded frame, the last data of the encoded frame, the actual input frame length of each of the encoding modules, and the actual output frame length.

5. The encoder according to claim 1 or 2, characterized in that, The multiple encoding modules connected in a preset order include any number of the following encoding modules: CRC and masking encoding module using cyclic redundancy check encoding method, rate-matching Turbo encoding module, interleaving encoding module, scrambling encoding module.

6. The encoder according to claim 1 or 2, characterized in that, The register includes a START register for storing the START signal. Before storing the START signal, the START register issues logical control parameters to the logical control module and encoding parameters to the encoding module.

7. The encoder according to claim 1 or 2, characterized in that, The encoding module includes a rate-matching Turbo encoding module, and the rate-matching Turbo encoding module selects a single-component convolutional encoder.

8. The encoder according to claim 7, wherein, The rate-matching Turbo encoding module further includes an interleaver, a rate-matching module, and a data merging module. The interleaver is used to interleave the data to be encoded. The data to be encoded and the interleaved data obtained after the interleaving process by the interleaver are respectively input into the single-component convolutional encoder for encoding according to the time sequence. The rate-matching module performs operations of generating tail bits and rate matching on the encoded data, and merges the data after rate matching with the data to be encoded and then outputs.

9. A multi-functional configurable encoding method, characterized in that, The method includes: Writing corresponding control parameters to the register through the bus interface and issuing them to the encoding module connected to the register. The control parameters include logical control parameters for the logical control module issued to the encoding module and encoding parameters for the encoding module during encoding. Receiving the data to be encoded through the encoding module. The logical control module selects at least one encoding module according to the logical control parameters. The selected encoding module encodes according to the preset encoding order and corresponding encoding parameters. Among them, if the selected encoding module includes a CRC and masking encoding module, the CRC and masking encoding module encodes in the following way: encoding the input data to be encoded according to the corresponding encoding parameters, encoding the data to be encoded in the byte integer multiple part using the parallel CRC encoding method, and encoding the data to be encoded in the non-byte integer multiple part using the serial CRC encoding method to support encoding of data to be encoded with any length.

10. The method according to claim 9, wherein The logical control module includes a first-level multiplexer, an intermediate multiplexer, and a last-level multiplexer. The logical control module selecting at least one encoding module according to the logical control parameters includes: According to the logical control parameters, the first-level multiplexer selects to output the data to be encoded received from the bus interface or the data encoded by the first-level encoding module to the next-level multiplexer and the next-level encoding module. According to the logical control parameters, the intermediate multiplexer outputs the data received from the previous-level multiplexer or the data encoded by the encoding module at the same level as the intermediate multiplexer to the next-level multiplexer and the next-level encoding module. According to the logic control parameter, the last-stage multiplexer selects to output the data output by the previous-stage multiplexer or the data output by the last-stage encoding module.

11. The method according to claim 9 or 10, characterized in that, The selected encoding modules include any combination of the following encoding modules: CRC and masking encoding module using cyclic redundancy check encoding method, rate matching Turbo encoding module, interleaving encoding module, scrambling encoding module.

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