An acceleration method of an aes key expansion algorithm and an instruction set processor

Abstract

The application relates to an acceleration method of an AES key expansion algorithm and an instruction set processor, wherein the acceleration method is based on a VAESKEYE extension instruction set, a plurality of independent AES key expansion algorithms are accelerated in parallel by pipelining execution of instructions in the VAESKEYE extension instruction set; the VAESKEYE extension instruction set adopts a RISC architecture and is used for generating any one of AES key expansion words in the AES key expansion algorithm according to a source operand; the VAESKEYE extension instruction set adopts a plurality of AES key expansion word parallel generation algorithms, the plurality of AES key expansion word parallel generation algorithms refer to algorithms for taking a key word or a key expansion word and an AES key expansion round number in 8 independent AES key expansion algorithms as inputs and respectively completing generation of 8 independent AES key expansion words in parallel. The application greatly improves the speed of executing the AES key expansion algorithm.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processor design and information security technology, and particularly relates to an acceleration method of an AES key expansion algorithm and an instruction set processor. BACKGROUND

[0002] With the rapid development of information technology and the wide application of cryptographic algorithms, cryptographic algorithms play an increasingly important role in the field of information security, and improving the performance of processors executing cryptographic algorithms has become one of the research hotspots. The Advanced Encryption Standard (AES), also known as the Rijndael algorithm, is a general-purpose cryptographic algorithm published by the National Institute of Standards and Technology (NIST) in November 2001. Due to its strong security, flexibility and ease of use, it has become one of the most widely used algorithms in symmetric key encryption and has had a profound impact internationally.

[0003] AES algorithm is a kind of symmetric block cipher algorithm, which can be used to process 128 bits data block, and the input, output block and intermediate block in encryption and decryption process are all 128 bits. The algorithm can use three different key lengths of 128, 192 and 256 bits respectively, called AES-128, AES-192 and AES-256, and uses Nr rounds, each of which needs an extended key Key (for AES-128, AES-192 or AES-256, Nr takes 10, 12 or 14). AES algorithm mainly includes AES encryption algorithm, AES key expansion algorithm and AES decryption algorithm. AES encryption algorithm mainly includes four steps of SubBytes() transformation, ShiftRows() transformation, MixColumns() transformation and AddRoundKey() transformation. Among them, SubBytes() transformation refers to using S-box to generate a state matrix for each Byte according to the S-box corresponding to SubBytes() transformation in AES encryption algorithm; the main operation of ShiftRows() transformation is cyclic shift (right shift); the main operation of MixColumns() transformation is polynomial multiplication and logical exclusive or defined in finite field, and the polynomial multiplication operation is realized by matrix multiplication; the main operation of AddRoundKey() transformation is logical exclusive or. Except for the last round which only performs SubBytes() transformation, ShiftRows() transformation and MixColumns() transformation, each of the remaining rounds uses four reversible transformations. AES decryption algorithm mainly includes four steps of InvShiftRows() transformation, InvSubBytes() transformation, InvMixColumns() transformation and inverse transformation of AddRoundKey() transformation, which is the inverse process of encryption and will not be described in detail here.

[0004] The combination relationship of key length Nk, block length Nb and round number Nr in AES standard algorithm is shown in Table 1.

[0005] Table 1 Relationship of key length Nk, block length Nb and round number Nr in AES-FIPS197 standard algorithm

[0006]

[0007] Limited by the input key length, AES algorithm needs to perform key expansion in the operation process to generate round keys of each round. AES key expansion algorithm accepts the key K of the cipher, runs the key expansion program to generate the result of the key arrangement. The key expansion generates a total of Nb*(Nr+1) key expansion words: the algorithm needs an initial set of Nb words, and each of the Nr rounds needs Nb words of key data. The key arrangement result consists of a linear array of 4-byte words, denoted as W i , where 0≤i<Nb*(Nr+1), according to the AES key expansion program, the first Nk words of the key arrangement result are directly filled by the key of the cipher. Each of the following words W i is equal to the XOR of the previous word W i－1 and the word W i－Nk before Nk positions. For the words at positions that are integer multiples of Nk, a transformation is performed on W i－1 before XOR, which first performs a byte circular shift (RotWord()) of the word, and then performs a byte substitution transformation (SubWord()), that is, a table lookup transformation on the 4 bytes in the word, and then XORs a round constant. In addition, the key expansion program for 256-bit keys (Nk=8) is slightly different from that for 128-bit and 192-bit keys. If Nk=8 and i-4 is an integer multiple of Nk, a byte substitution (SubWord()) transformation is performed on W i－1 before XOR. Among them, the SubWord() function is used to receive a 4-byte input word, and each byte is applied to the S-box of the AES encryption algorithm to obtain an output word; the RotWord() function receives the word [a0, a1, a2, a3] as input, performs a circular shift and returns the word [a1, a2, a3, a0]; the round constant number array Rcon[Row i ] contains the values given by [x i-1 , {00}, {00}, {00}] (note that i starts from 1), x i-1 is the exponential power of x (denoted as {02}) on the finite field GF(2 8 ). Due to the high complexity of the operation process of the AES key expansion algorithm, and the data dependency between the key expansion words in the expansion result, the performance of the processor executing the AES algorithm is limited.

[0008] In order to improve the performance of the processor in executing the AES algorithm, mainstream processor manufacturers have adopted the way of extending the cryptographic algorithm instructions in the instruction set architecture (ISA) to speed up the processor in executing the AES algorithm. For example, Intel X86 proposes the advanced cryptographic standard instruction set AES-NI on the basis of the original instruction set, including 6 AES cryptographic instructions; IBM Power instruction set also adds 5 instructions for accelerating the AES encryption and decryption standard algorithm; ARMv8 instruction set also extends 4 instructions for accelerating the AES algorithm. These extension instructions usually merge several steps in the AES encryption and decryption process, thereby realizing a 128-bit vector instruction; the difference lies in that the Intel AES-NI distinguishes the encryption round and the tail encryption round, retains the column mixing instruction, and provides a key generation instruction corresponding to the AES-256 key expansion rule; the AES extension instruction in Power8 provides instructions for the AES encryption round and the tail encryption round respectively, and separately provides an S-box lookup instruction for byte substitution, which can be used for the key expansion algorithm; the column mixing is separately taken as an instruction in ARMv8, and whether it is the last round is not distinguished. Domestic processor manufacturers and research institutions generally adopt or are compatible with the mainstream general-purpose processor architecture and its instruction set of Intel X86, IBM Power or ARM, and no instruction set for accelerating the AES key expansion algorithm designed specifically for domestic processors has been published. SUMMARY

[0009] The technical problem to be solved by the present application is to provide an acceleration method of the AES key expansion algorithm and an instruction set processor, which can greatly improve the speed of executing the AES key expansion algorithm and simplify the software program.

[0010] The technical scheme adopted by the present application to solve its technical problems is: providing an acceleration method of an AES key expansion algorithm, based on a VAESKEYE expansion instruction set, parallel acceleration of multiple independent AES key expansion algorithms is realized by pipelining execution of instructions in the VAESKEYE expansion instruction set; the VAESKEYE expansion instruction set adopts a RISC architecture, instructions adopt a fixed-length 32-bit format, has three 256-bit source operands and a 256-bit target operand, and is used to generate any one of AES key expansion words in an AES key expansion algorithm according to the source operands; the VAESKEYE expansion instruction set adopts a plurality of AES key expansion word parallel generation algorithms, the plurality of AES key expansion word parallel generation algorithms refer to algorithms that take key words or key expansion words and an AES key expansion round number in 8 independent AES key expansion algorithms as inputs, and complete generation of 8 independent AES key expansion words in parallel respectively; the VAESKEYE expansion instruction set includes an AES-128 key expansion instruction, an AES-192 key expansion instruction and an AES-256 key expansion instruction.

[0011] The parallel acceleration of multiple independent AES key expansion algorithms realized by pipelining execution of instructions in the VAESKEYE expansion instruction set specifically includes the following steps:

[0012] (1) taking the keys K7-K0 of 8 independent AES key expansion algorithms as the 0th- (Nk-1) th key expansion words in the corresponding AES expansion keys respectively;

[0013] (2) taking the key words in the keys K7-K0 in the format of {W 7,0 ,W 6,0 ,W 5,0 ,W 4,0 ,W 3,0 ,W 2,0 ,W 1,0 ,W 0,0} and {W 7,Nk-1 ,W 6,Nk-1 ,W 5,Nk-1 ,W 4,Nk-1 ,W 3,Nk-1 ,W 2,Nk-1 ,W 1,Nk-1 ,W 0,Nk-1} to be loaded into the 256-bit registers Va and Vb in the register file respectively, and taking 8 independent AES key expansion round numbers in the format of {Row 7,0 ,Row 6,0 ,Row 5,0 ,Row 4,0 ,Row 3,0 ,Row 2,0 ,Row 1,0,Row 0,0} into the 256-bit register Vc in the register file;

[0014] (3) execute the 1st key expansion instruction with 8 key words {W 7,0 ,W 6,0 ,W 5,0 ,W 4,0 ,W 3,0 ,W 2,0 ,W 1,0 ,W 0,0} in the register Va, 8 key words {W 7,Nk-1 ,W 6,Nk-1 ,W 5,Nk-1 ,W 4,Nk-1 ,W 3,Nk-1 ,W 2,Nk-1 ,W 1,Nk-1 ,W 0,Nk-1} in the register Vb, and 8 independent AES key expansion round numbers {Row 7,0 ,Row 6,0 ,Row 5,0 ,Row 4,0 ,Row 3,0 ,Row 2,0 ,Row 1,0 ,Row 0,0} in the register Vc as source operands, and generate 8 AES key expansion words {W 7,Nk ,W 6,Nk ,W 5,Nk ,W 4,Nk ,W 3,Nk ,W 2,Nk ,W 1,Nk ,W 0,Nk};

[0015] (4) sequentially pipeline the next key expansion instruction, each time update the execution result {W 7,i-1 ,W 6,i-1 ,W 5,i-1 ,W 4,i-1 ,W 3,i-1 ,W 2,i-1 ,W 1,i-1 ,W 0,i-1} of the previous key expansion instruction as the source operand B of the next instruction, read the updated key words or key expansion words and the data in the register Va and the register Vc after the key expansion round numbers from the register file {W 7,i-Nk ,W 6,i-Nk ,W 5,i-Nk ,W 4,i-Nk ,W 3,i-Nk ,W 2,i-Nk ,W1,i-Nk ,W 0,i-Nk} and {Row 7,i ,Row 6,i ,Row 5,i ,Row 4,i ,Row 3,i ,Row 2,i ,Row 1,i ,Row 0,i} as new source operands A and C, complete 8 independent AES key expansion algorithm one key expansion word {W 7,i ,W 6,i ,W 5,i ,W 4,i ,W 3,i ,W 2,i ,W 1,i ,W 0,i} generation, finally get 8 groups of expanded key expansion words.

[0016] The AES-128 key expansion instruction, the AES-192 key expansion instruction and the AES-256 key expansion instruction all adopt a register format floating point complex operation instruction format, and the instruction formats are VAES128KEYE Va, Vb, Vc, Vd, VAES192KEYE Va, Vb, Vc, Vd and VAES256KEYE Va, Vb, Vc, Vd respectively, which are used to indicate the operation of three source operands in three 256-bit registers Va, Vb and Vc, and the result is saved into a 256-bit target register Vd. The [31:26] bit of the 32-bit instruction represents a 6-bit operation code, the [25:21] bit represents the address of a 256-bit register Va selected from a group of 32 256-bit register files, the [20:16] bit represents the address of a 256-bit register Vb selected from a group of 32 256-bit register files, the [15:10] bit represents a 6-bit function code for determining the specific instruction function, the [9:5] bit represents the address of a 256-bit register Vc selected from a group of 32 256-bit register files, and the [4:0] bit represents the address of a 256-bit target register Vd selected from a group of 32 256-bit register files.

[0017] The AES-128 key expansion instruction is specifically: according to 8 groups of independent AES-128 key expansion algorithm key words or key expansion words {W 7,i-Nk ,W 6,i-Nk ,W 5,i-Nk ,W 4,i-Nk ,W 3,i-Nk ,W 2,i-Nk ,W 1,i-Nk ,W0,i-Nk}、{W 7,i-1 ,W 6,i-1 ,W 5,i-1 ,W 4,i-1 ,W 3,i-1 ,W 2,i-1 ,W 1,i-1 ,W 0,i-1} and 8 independent AES key expansion round numbers {Row 7,i ,Row 6,i ,Row 5,i ,Row 4,i ,Row 3,i ,Row 2,i ,Row 1,i ,Row 0,i} from the register Vc, perform any one round key expansion of the AES-128 key expansion algorithm, and save the obtained execution result {W 7,i ,W 6,i ,W 5,i ,W 4,i ,W 3,i ,W 2,i ,W 1,i ,W 0,i} in the target register Vd, wherein Row 7,i ~Row 0,i are legal values from 4 to 43; in the execution result {W 7,i ,W 6,i ,W 5,i ,W 4,i ,W 3,i ,W 2,i ,W 1,i ,W 0,i}, for j equal to 0, 1, 2, 3, 4, 5, 6, 7, the generation logic of W j,i is: W j,i [31:0] = W j,i-Nk [31:0] XOR Temp j [31:0], wherein Nk = 4, XOR represents bitwise XOR, Temp j is a 32-bit intermediate variable, and when Row j,i is an integer multiple of Nk, the generation logic of Temp j is: Temp j [31:0] = SubWord(RotWord(W j,i-1 [31:0])) XOR Rcon[Row j,i / Nk], wherein the RotWord() function, the SubWord() function and the Rcon[Row j,iThe function is defined by the AES key expansion algorithm. When Row j,i When Temp is not an integer multiple of Nk, j [31:0]=W j,i-1 [31:0]; During any round of key expansion in the AES-128 key expansion algorithm, the RotWord() function, SubWord() function, and Rcon[Row] are used. j,i All functions are implemented directly using hardware logic; executing the AES-128 key extension instruction once can generate 8 independent AES key extension words in parallel. Each time, register Va, register Vb, and register Vc are updated with a new key word or key extension word and AES key extension round number. Executing the AES-128 key extension instruction 40 times consecutively can generate the 4th to 43rd key extension words in the 8 unrelated AES-128 key extension algorithms.

[0018] The AES-192 key expansion instruction specifically refers to: using the key word or key expansion word {W} from 8 sets of independent AES-192 key expansion algorithms derived from registers Va and Vb. 7,i-Nk W 6,i-Nk W 5,i-Nk W 4,i-Nk W 3,i-Nk W 2,i-Nk W 1,i-Nk W 0,i-Nk}、{W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1} and 8 unrelated AES key extension round numbers {Row} from register Vc 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i}, perform any round of key expansion using the AES-192 key expansion algorithm, and record the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i} is stored in the destination register Vd, where Row 7,i~Row 0,i is 6~51; in the execution result {W 7,i ,W 6,i ,W 5,i ,W 4,i ,W 3,i ,W 2,i ,W 1,i ,W 0,i} for j equal to 0, 1, 2, 3, 4, 5, 6, 7, the generation logic of W j,i is: W j,i [31:0] = W j,i-Nk [31:0] XOR Temp j [31:0], where Nk = 6, XOR represents bitwise XOR, Temp j is a 32-bit intermediate variable, when Row j,i is an integer multiple of Nk, the generation logic of Temp j is: Temp j [31:0] = SubWord(RotWord(W j,i-1 [31:0])) XOR Rcon[Row j,i / Nk], where RotWord() function, SubWord() function and Rcon[Row j,i ] function are functions defined by AES key expansion algorithm, when Row j,i is not an integer multiple of Nk, Temp j [31:0] = W j,i-1 [31:0]; in the execution of any round of AES-192 key expansion algorithm, RotWord() function, SubWord() function and Rcon[Row j,i ] function are directly realized by hardware logic; 8 independent AES key expansion words can be generated in parallel by executing the AES-192 key expansion instruction once, and the registers Va, Vb and Vc are updated with new key word or key expansion word and AES key expansion round number each time, and 8 independent key expansion words in the 6th to 51st round of AES-192 key expansion algorithm can be generated by executing the AES-128 key expansion instruction 46 times continuously.

[0019] The AES-256 key expansion instruction is specifically: according to 8 groups of independent AES-256 key expansion algorithm key words or key expansion words {W 7,i-Nk ,W 6,i-Nk ,W 5,i-Nk ,W 4,i-Nk ,W 3,i-Nk ,W 2,i-Nk ,W1,i-Nk W 0,i-Nk}、{W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1} and 8 unrelated AES key extension round numbers {Row} from register Vc 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i}, perform any round of key expansion using the AES-256 key expansion algorithm, and record the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i} is stored in the destination register Vd, where Row 7,i ~Row 0,i Valid values ​​range from 8 to 59; in the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i In the context of}, for j equal to 0, 1, 2, 3, 4, 5, 6, 7, W j,i The generation logic of W is: j,i [31:0]=W j,i-Nk [31:0]XOR Temp j [31:0], where Nk = 8, XOR represents bitwise XOR, and Temp j It is a 32-bit intermediate variable, when Row j,i When Temp is an integer multiple of Nk j The generation logic is: Temp j [31:0] = SubWord(RotWord(W j,i-1 [31:0]))XOR Rcon[Row j,i / Nk], where the RotWord() function, SubWord() function, and Rcon[Row] are used. j,iThe function is a function defined by the AES key expansion algorithm, and when Row j,i When the remainder of Temp j divided by Nk is equal to 4, Temp j [31:0] = SubWord(W j,i-1 [31:0]), and when Row j,i is other values, Temp j [31:0] = W j,i-1 [31:0]; the RotWord() function, the SubWord() function and the Rcon[Row j,i ] function are directly implemented by hardware logic when performing any round key expansion of the AES-256 key expansion algorithm; 8 independent AES key expansion words can be generated in parallel when executing the AES-256 key expansion instruction once, and the registers Va, the register Vb and the register Vc are updated with a new key word or key expansion word and an AES key expansion round sequence number each time, and 8 independent key expansion words in the 8th to 59th of the AES-256 key expansion algorithm can be generated by continuously executing the AES-128 key expansion instruction 52 times.

[0020] The technical scheme adopted by the present application to solve the technical problems is: further provided is an instruction set processor, comprising a register file and a VAESKEYE instruction execution unit, the register file is used for saving a source operand A, a source operand B, a source operand C and an execution result of the VAESKEYE instruction execution unit, and the VAESKEYE instruction execution unit is used for receiving and executing a VAESKEYE expansion instruction set; input signals of the VAESKEYE instruction execution unit comprise the source operand A of 256 bits, the source operand B of 256 bits, the source operand C of 256 bits and a 2-bit instruction control signal, and an output signal is the execution result of 256 bits; the VAESKEYE instruction execution unit comprises an instruction control information processing unit and 8 AES expansion key word generation units executed in parallel, the instruction control information processing unit is used for controlling the AES expansion key word generation units, and the AES expansion key word generation units execute any round key expansion of a key expansion algorithm through hardware logic; the VAESKEYE expansion instruction set comprises an AES-128 key expansion instruction, an AES-192 key expansion instruction and an AES-256 key expansion instruction.

[0021] The execution delay of the AES-128 key expansion instruction, the AES-192 key expansion instruction and the AES-256 key expansion instruction is 1 beat; the output signal of the VAESKEYE instruction execution unit is bypassed to the input end of the VAESKEYE instruction execution unit to serve as the source operand B of the next instruction, and the instruction set processor supports pipeline execution of the AES-128 key expansion instruction, the AES-192 key expansion instruction and the AES-256 key expansion instruction.

[0022] Advantages

[0023] Compared with the prior art, the application has the following advantages and positive effects:

[0024] The application can generate 8 independent AES key expansion words in parallel by using the multiple AES key expansion word parallel generation algorithm, and can generate the Nk~Nb*(Nr+1)-1th key expansion word in 8 independent AES-128 / 192 / 256 key expansion algorithms by executing the VAES128KEYE / VAES192KEYE / VAES256KEYE instruction Nb*(Nr+1)-Nk times, thereby significantly accelerating the execution speed of the AES key expansion algorithm, simplifying the software program of the AES key expansion algorithm, and further reducing the storage cost of the software.

[0025] The application can accelerate 1~8 groups of independent AES key expansion algorithms in parallel by using the pipeline execution of the VAES128KEYE / VAES192KEYE / VAES256KEYE instruction, and is particularly suitable for application scenarios that need to execute a large number of AES key expansion algorithms.

[0026] The execution delay of the VAES128KEYE instruction, the VAES192KEYE instruction and the VAES256KEYE instruction of the processor in the application is 1 beat, and the instruction pipeline execution is supported, and the execution result of the previous instruction in the two continuous VAESKEYE expansion instructions can be bypassed to the next instruction as the input operand. The processor uses the multiple AES key expansion word parallel generation, the hardware logic directly implements the RotWord() function, the SubWord() function, the Rcon[Row j,i ] function and the lookup table and XOR operation methods to improve the execution speed; and the generation of the Nk~Nb*(Nr+1)-1th key expansion word in 8 groups of independent AES-128 / 192 / 256 key expansion algorithms can be completed in only 40 / 46 / 52 beats.

[0027] The present application fully realizes the parallel execution potential of the key expansion word generation in the AES key expansion algorithm, and effectively accelerates the execution of the AES key expansion algorithm. The method for accelerating the AES key expansion algorithm and the instruction execution unit provided by the present application are easy to integrate into an RSIC processor or a special-purpose cryptographic chip, and improve the performance of the RSIC processor or the special-purpose cryptographic chip in executing the AES key expansion algorithm. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is the execution process block diagram of the VAES128KEYE instruction;

[0029] Figure 2 is the execution process block diagram of the VAES192KEYE instruction;

[0030] Figure 3 is the execution process block diagram of the VAES256KEYE instruction;

[0031] Figure 4 is the flowchart of the multiple AES key expansion word parallel generation algorithm;

[0032] Figure 5 is the flowchart of the method for accelerating the AES key expansion algorithm;

[0033] Figure 6 is the schematic diagram of the floating-point composite operation instruction format of the register format;

[0034] Figure 7 is the structural diagram of the processor for accelerating the AES key expansion algorithm;

[0035] Figure 8 is the structural diagram of the VAESKEYE instruction execution unit. DETAILED DESCRIPTION

[0036] The present application will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present application and not used to limit the scope of the present application. Furthermore, it should be understood that after reading the content taught by the present application, those skilled in the art can make various modifications or changes to the present application, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0037] The AES key expansion algorithm includes AES-128, AES-192 and AES-256 key expansion algorithms, and the three parts all include SubWord() function operation, RotWord() operation, round constant calculation, data selection and XOR operation and the like. Since there is data dependence between the key expansion words in the AES key expansion process, the parallel generation of different key expansion words in the same AES key expansion algorithm cannot be directly realized. Therefore, the key to accelerating the AES key expansion algorithm is to fully realize the internal parallelism of the key expansion word generation process, to directly realize the SubWord() function operation, RotWord() operation, round constant calculation, data selection and XOR operation and the like by hardware as much as possible, and to realize the parallel execution of different AES key expansion algorithms.

[0038] The inventor of the present application finds that the key expansion word generation process in the AES key expansion algorithm has parallel execution potential, and the SubWord() function operation, RotWord() operation, round constant calculation, data selection and XOR operation and the like can be directly realized by hardware, so as to accelerate the key expansion word generation process. Moreover, the parallel generation of multiple AES key expansion words can be realized by adopting multiple AES key expansion word parallel generation algorithms, so as to simultaneously complete the key expansion word generation of multiple unrelated AES key expansion algorithms.

[0039] The embodiment of the present application relates to an acceleration method of an AES key expansion algorithm, which is based on a VAESKEYE extension instruction set. The VAESKEYE extension instruction set adopts a RISC architecture, and source operands and target operands are all 256 bits. The VAESKEYE extension instruction set includes an AES-128 key expansion instruction (VAES128KEYE), an AES-192 key expansion instruction (VAES192KEYE) and an AES-256 key expansion instruction (VAES256KEYE), which can be respectively used for accelerating the key expansion algorithms of AES-128 / 192 / 256. The acceleration method of the AES key expansion algorithm adopts a pipeline execution mode of the VAESKEYE extension instruction, so as to realize the parallel acceleration of multiple (1-8) unrelated AES-128 / 192 / 256 key expansion algorithms. The VAES128KEYE, VAES192KEYE or VAES256KEYE instruction is executed Nb*(Nr+1)-Nk times, so as to generate the Nk-Nb*(Nr+1)-1th key expansion word in the 8 unrelated AES-128, AES-192 and AES-256 key expansion algorithms.

[0040] The VAESKEYE extension instruction set adopts a RISC architecture, and the instruction adopts a fixed-length 32-bit format. The instruction has three 256-bit source operands and one 256-bit target operand, as shown in the following table. Figures 1-3As shown, any AES key extension word from the AES-128 / 192 / 256 key extension algorithms can be generated based on the source operand; the VAESKEYE extension instruction set employs multiple parallel AES key extension word generation algorithms, such as... Figure 4 As shown, a single execution can generate 8 independent AES key extension words in parallel; the parallel generation algorithm for multiple AES key extension words refers to using 8 sets of unrelated AES-128 / 192 / 256 key extension algorithms for key words or key extension words {W}. 7,i-Nk W 6,i-Nk W 5,i-Nk W 4,i-Nk W 3,i-Nk W 2,i-Nk W 1,i-Nk W 0,i-Nk}、{W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1} and AES key extension round number {Row 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i The algorithm takes} as input and performs parallel processing to generate eight independent AES key expansion words. The VAESKEYE expansion instruction set includes one AES-128 key expansion instruction (VAES128KEYE), one AES-192 key expansion instruction (VAES192KEYE), and one AES-256 key expansion instruction (VAES256KEYE), which can be used to accelerate the AES-128 / 192 / 256 key expansion algorithms, respectively.

[0041] Methods to accelerate AES key expansion algorithms include pipelining the execution of VAES128KEYE, VAES192KEYE, or VAES256KEYE instructions to achieve parallel acceleration of multiple unrelated AES-128, AES-192, or AES-256 key expansion algorithms, such as... Figure 5 As shown, the specific steps are as follows:

[0042] 1) Use the keys K7 to K0 of the 8 unrelated AES-128, AES-192, or AES-256 key expansion algorithms as the 0th to Nk-1th key expansion words in the corresponding AES expansion keys;

[0043] 2) Take the key words from keys K7 to K0 in step 1) and start with {W 7,0 W 6,0 W 5,0 W 4,0 W 3,0 W 2,0 W 1,0 W 0,0}、{W 7,Nk-1 W 6,Nk-1 W 5,Nk-1 W 4,Nk-1 W 3,Nk-1 W 2,Nk-1 W 1,Nk-1 W 0,Nk-1 The format is loaded into 256-bit registers Va and Vb in the register file, and the eight unrelated AES key extension round numbers are formatted as {Row}. 7,0 Row 6,0 Row 5,0 Row 4,0 Row 3,0 Row 2,0 Row 1,0 Row 0,0 The format is loaded into the 256-bit register Vc in the register file;

[0044] 3) Using the 8 key words {W} in the source register Va 7,0 W 6,0 W 5,0 W 4,0 W 3,0 W 2,0 W 1,0 W 0,0}, the 8 key words {W} in the source register Vb 7,Nk-1 W 6,Nk-1 W 5,Nk-1 W 4,Nk-1 W 3,Nk-1 W 2,Nk-1 W 1,Nk-1 W 0,Nk-1} and the 8 unrelated AES key extension round numbers {Row} in the source register Vc 7,0 Row 6,0 Row 5,0 Row 4,0 Row 3,0 Row 2,0 Row 1,0 Row 0,0} Execute the first VAES128KEYE instruction (VAES192KEYE instruction or VAES256KEYE instruction) on the source operand to generate 8 AES key extension words {W 7,Nk W 6,Nk W 5,Nk W 4,Nk W 3,Nk W 2,Nk W 1,Nk W 0,Nk};

[0045] 4) Following step 3), continue to execute 39 (45 or 51) VAES128KEYE instructions (VAES192KEYE instructions or VAES256KEYE instructions) sequentially, each time processing the result of the previous instruction {W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1 Update the source operand B for the next instruction, and read the data {W} from the source registers Va and Vc after updating the key word (or key extension word) and key extension round number from the register file. 7,i-Nk W 6,i-Nk W 5,i-Nk W 4,i-Nk W 3,i-Nk W 2,i-Nk W 1,i-Nk W 0,i-Nk} and {Row 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i} As new operands A and C, complete a key extension word {W} for eight independent AES-128 (AES-192 or AES-256) key extension algorithms. 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i The generation of} ultimately yields 8 sets of expanded key extension words (each set contains Nb(Nr+1) key extension words).

[0046] The VAES128KEYE, VAES192KEYE, and VAES256KEYE instructions in the VAESKEYE extended instruction set all use a register-formatted floating-point compound arithmetic instruction format, such as... Figure 6 As shown, the instruction formats are VAES128KEYE Va,Vb,Vc,Vd, VAES192KEYE Va,Vb,Vc,Vd, and VAES256KEYE respectively. Va, Vb, Vc, and Vd are used to indicate the operation of three source operands in three 256-bit source registers Va, Vb, and Vc. The result is stored in a 256-bit destination register Vd. In a 32-bit instruction, bits [31:26] represent the 6-bit opcode, bits [25:21] represent the address of a 256-bit register Va selected from a set of 32 256-bit registers, bits [20:16] represent the address of a 256-bit register Vb selected from a set of 32 256-bit registers, bits [15:10] represent the 6-bit function code used to determine the specific function of the instruction, bits [9:5] represent the address of a 256-bit register Vc selected from a set of 32 256-bit registers, and bits [4:0] represent the address of a 256-bit register Vd selected from a set of 32 256-bit registers.

[0047] The AES-128 key extension instruction (VAES128KEYE) uses eight independent sets of AES-128 key extension algorithms from source register Va and source register Vb, with the key word or key extension word {W} as the basis. 7,i-Nk W 6,i-Nk W 5,i-Nk W 4,i-Nk W 3,i-Nk W 2,i-Nk W 1,i-Nk W 0,i-Nk}、{W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1} and 8 unrelated AES key extension round numbers {Row} from source register Vc 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i Row 7,i ~Row0,i Legal values are 4-43, any round key expansion of AES-128 key expansion algorithm is executed, and the execution result {W 7,i ,W 6,i ,W 5,i ,W 4,i ,W 3,i ,W 2,i ,W 1,i ,W 0,i} is saved in the target register Vd, the operation executed by the AES-128 key expansion instruction (VAES128KEYE) is:

[0048]

[0049]

[0050] Wherein, the SubWord() function is used to receive a 4-byte input word, and the S-box of the AES encryption algorithm is applied to each byte to obtain an output word (the same below), the SubWord() function can be directly implemented by hardware logic in the implementation, and the byte substitution operation of the S-box is shown in Table 2, the data in Table 2 are hexadecimal numbers, for example, if W 1,1 ={53}, the replaced value is determined by the intersection of the row marked as 5 and the column marked as 3 in Table 2. That is, the value of W 1,1 is {ed}.

[0051] Table 2 S-box: replacement value of byte xy (in hexadecimal format)

[0052]

[0053] The RotWord() function is used to receive the word [a0, a1, a2, a3] as input, and returns the word [a1, a2, a3, a0] after performing a circular shift (the same below), the RotWord() function can be directly implemented by hardware logic in the implementation; the round constant number array Rcon[Row i ] contains the value given by [x i-1 , {00}, {00}, {00}] (note that i starts from 1), x i-1 is the exponential power of x (denoted as {02}) on the finite field GF(2 8 ); Rcon[Row j,i ] can be directly implemented by hardware logic in the implementation, as shown in Table 3.

[0054] Table 3 Rcon[Row i ] value table (Rcon[Row i ] is in hexadecimal format, and the rest is in decimal)

[0055]

[0056]

[0057] The AES-128 key expansion instruction (VAES128KEYE) can generate 8 independent AES key expansion words in parallel once, update Va, Vb and Vc with a new key word (or key expansion word) and an AES key expansion round number each time, and generate the 4th to 43rd key expansion words (numbered from 0) in 8 independent AES-128 key expansion algorithms by executing the instruction 40 times successively.

[0058] The AES-192 key expansion instruction (VAES192KEYE) can execute any round of the AES-192 key expansion algorithm according to 8 groups of key words or key expansion words {W 7,i-Nk 6,i-Nk 5,i-Nk 4,i-Nk 3,i-Nk 2,i-Nk 1,i-Nk 0,i-Nk} from source registers Va and Vb, and 8 independent AES key expansion round numbers {Row 7,i-1 6,i-1 5,i-1 4,i-1 3,i-1 2,i-1 1,i-1 0,i-1} and 8 independent AES key expansion round numbers {Row 7,i 6,i 5,i 4,i 3,i 2,i 1,i 0,i} from source register Vc, save the execution result {W 7,i 0,i 7,i 6,i 5,i 4,i 3,i 2,i 1,i 0,i} in target register Vd, and the operation of the AES-192 key expansion instruction (VAES192KEYE) is: ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​

[0059]

[0060]

[0061] Executing the AES-192 key expansion instruction (VAES192KEYE) once can generate 8 independent AES key expansion words in parallel. Each time, Va, Vb, and Vc are updated with a new key word (or key expansion word) and the AES key expansion round number. Executing this instruction 46 times consecutively can generate 8 unrelated key expansion words from the 6th to the 51st in the AES-192 key expansion algorithm (numbered starting from 0).

[0062] The AES-256 key extension instruction (VAES256KEYE) uses a keyword or key extension word {W} from eight independent sets of AES-256 key extension algorithms derived from source registers Va and Vb. 7,i-Nk W 6,i-Nk W 5,i-Nk W 4,i-Nk W 3,i-Nk W 2,i-Nk W 1,i-Nk W 0,i-Nk}、{W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1} and 8 unrelated AES key extension round numbers {Row} from source register Vc 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i Row 7,i ~Row 0,i The valid values ​​are 8 to 59. Perform any round of key expansion using the AES-256 key expansion algorithm, and record the result {W}. 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i The key is stored in the destination register Vd. The operation performed by the AES-256 key extension instruction (VAES256KEYE) is as follows:

[0063]

[0064]

[0065] The AES-256 key expansion instruction (VAES256KEYE) instruction can generate 8 independent AES key expansion words in parallel at a time, and update Va, Vb and Vc with a new key word (or key expansion word) and an AES key expansion round number each time. The instruction is executed 52 times in succession to generate the 8th to 59th key expansion words (numbered from 0) in 8 independent AES-256 key expansion algorithms.

[0066] Embodiments of the present application relate to an instruction set processor, such as Figure 7 as shown, comprising an instruction unit, an instruction decode unit, an instruction scheduling and issue unit, an instruction execution unit (including a VAESKEYE instruction execution unit), an instruction commit ROB unit, and a register file including 32 256-bit registers, wherein the VAESKEYE instruction execution unit is configured to receive and execute a VAES128KEYE instruction (or a VAES192KEYE instruction or a VAES256KEYE instruction), and the function of the VAESKEYE instruction execution unit is to perform any one round of key expansion in the AES-128 / 192 / 256 key expansion algorithm according to input information.

[0067] The VAESKEYE instruction execution unit provides pipelined execution for the VAES128KEYE instruction, the VAES192KEYE instruction and the VAES256KEYE instruction, and is configured to receive and execute the VAES128KEYE instruction, the VAES192KEYE instruction or the VAES256KEYE instruction, and the input signals of the VAESKEYE instruction execution unit include: 1 256-bit source operand A (eight independent AES key words or key expansion words {W 7,i-Nk 6,i-Nk 5,i-Nk 4,i-Nk 3,i-Nk 2,i-Nk 1,i-Nk 0,i-Nk 7,i-1 6,i-1 5,i-1 4,i-1 3,i-1 2,i-1 1,i-1 0,i-1 ​​​​​​​​​​​​​​​} from source register Vb or bypass data from the result of the previous instruction execution), a 256-bit source operand C (eight independent AES key expansion round numbers {Row 7,i ,Row 6,i ,Row 5,i ,Row 4,i ,Row 3,i ,Row 2,i ,Row 1,i ,Row 0,i} from source register Vc), and a 2-bit instruction control signal (used to determine the value of Nk according to the instruction type); the output signal is a 256-bit execution result {W 7,i ,W 6,i ,W 5,i ,W 4,i ,W 3,i ,W 2,i ,W 1,i ,W 0,i} (written back to the target register in the register file, and simultaneously determined whether to bypass to the input end of the VAESKEYE instruction execution unit according to the information of the next instruction).

[0068] The structure of the VAESKEYE instruction execution unit is shown in Figure 8 Fig. 1, which is composed of an instruction control information processing unit and eight parallel AES expansion key word generation units. The VAES128KEYE instruction, the VAES192KEYE instruction, and the VAES256KEYE instruction share the hardware implementation, and only one of them can be executed at a time. The AES expansion key word generation unit directly implements the RotWord() function, the SubWord() function, the Rcon[Row j,i ] function, and the XOR operation by using hardware logic, thereby improving the execution speed.

[0069] The instruction set processor of the embodiment has an execution delay of 1 beat (the beat division can be adjusted according to the working frequency of the specific processor (processor core)) for the VAES128KEYE instruction, the VAES192KEYE instruction, and the VAES256KEYE instruction. The output result of the VAESKEYE instruction execution unit can be bypassed to the input end of the VAESKEYE instruction execution unit and used as the source operand B of the next instruction. When the instruction set processor of the embodiment is used to perform AES key expansion, the generation of the Nk~Nb*(Nr+1)-1th key expansion word in the eight independent AES-128 / 192 / 256 key expansion algorithms can be completed in only 40 / 46 / 52 beats at the shortest.

Claims

1. A method of accelerating an AES key expansion algorithm, characterized by, The parallel acceleration of multiple independent AES key expansion algorithms is realized by pipelining the instructions in the VAESKEYE extension instruction set; the VAESKEYE extension instruction set adopts RISC architecture, and the instructions adopt fixed-length 32-bit format, have three 256-bit source operands and one 256-bit target operand, and are used to generate any one of the AES key expansion words in the AES key expansion algorithm according to the source operands; the VAESKEYE extension instruction set adopts a plurality of AES key expansion word parallel generation algorithms, which are algorithms for generating eight independent AES key expansion words in parallel with the key words or key expansion words and the AES key expansion round number in eight independent AES key expansion algorithms as inputs; the VAESKEYE extension instruction set includes AES-128 key expansion instructions, AES-192 key expansion instructions and AES-256 key expansion instructions; The parallel acceleration of multiple independent AES key expansion algorithms is realized by pipelining the instructions in the VAESKEYE extension instruction set; the VAESKEYE extension instruction set adopts RISC architecture, and the instructions adopt fixed-length 32-bit format, have three 256-bit source operands and one 256-bit target operand, and are used to generate any one of the AES key expansion words in the AES key expansion algorithm according to the source operands; the VAESKEYE extension instruction set adopts a plurality of AES key expansion word parallel generation algorithms, which are algorithms for generating eight independent AES key expansion words in parallel with the key words or key expansion words and the AES key expansion round number in eight independent AES key expansion algorithms as inputs; the VAESKEYE extension instruction set includes AES-128 key expansion instructions, AES-192 key expansion instructions and AES-256 key expansion instructions; The AES-128 key expansion instructions, the AES-192 key expansion instructions and the AES-256 key expansion instructions all adopt the floating-point composite operation instruction format of the register format, and the instruction formats are VAES128KEYE Va, Vb, Vc, Vd, VAES192KEYE Va, Vb, Vc, Vd and VAES256KEYE Va, Vb, Vc, Vd respectively, which are used to indicate the operation of three source operands in the 256-bit registers Va, Vb and Vc, and save the result into a 256-bit target register Vd; the 32-bit instruction [31:26] represents a 6-bit operation code, [25:21] represents the address of a 256-bit register Va selected from a group of 32 256-bit register files, [20:16] represents the address of a 256-bit register Vb selected from a group of 32 256-bit register files, [15:10] represents a 6-bit function code for determining the specific instruction function, [9:5] represents the address of a 256-bit register Vc selected from a group of 32 256-bit register files, and [4:0] represents the address of a 256-bit target register Vd selected from a group of 32 256-bit register files. (2) The key words in the keys K7~K0 are loaded into the 256-bit registers Va and Vb in the register file in the format of {W 7,0 ,W 6,0 ,W 5,0 ,W 4,0 ,W 3,0 ,W 2,0 ,W 1,0 ,W 0,0} and {W 7,Nk-1 ,W 6,Nk-1 ,W 5,Nk-1 ,W 4,Nk-1 ,W 3,Nk-1 ,W 2,Nk-1 ,W 1,Nk-1 ,W 0,Nk-1} respectively, and the 8 independent AES key expansion round numbers are loaded into the 256-bit registers Vc in the register file in the format of {Row 7,0 ,Row 6,0 ,Row 5,0 ,Row 4,0 ,Row 3,0 ,Row 2,0 ,Row 1,0 ,Row 0,0}; (3) the 8 key words {W 7,0 ,W 6,0 ,W 5,0 ,W 4,0 ,W 3,0 ,W 2,0 ,W 1,0 ,W 0,0} in the register Va, the 8 key words {W 7,Nk-1 ,W 6,Nk-1 ,W 5,Nk-1 ,W 4,Nk-1 ,W 3,Nk-1 ,W 2,Nk-1 ,W 1,Nk-1 ,W 0,Nk-1} in the register Vb, and the 8 independent AES key expansion round numbers {Row 7,0 ,Row 6,0 ,Row 5,0 ,Row 4,0 ,Row 3,0 ,Row 2,0 ,Row 1,0 ,Row 0,0} in the register Vc as source operands to perform the 1st key expansion instruction to generate the 8 AES key expansion words {W 7,Nk ,W 6,Nk ,W 5,Nk ,W 4,Nk ,W 3,Nk ,W 2,Nk ,W 1,Nk ,W 0,Nk}; (4) sequentially execute the next key expansion instruction, each time update the execution result of the previous key expansion instruction {W 7,i-1 ,W 6,i-1 ,W 5,i-1 ,W 4,i-1 ,W 3,i-1 ,W 2,i-1 ,W 1,i-1 ,W 0,i-1} to the source operand B of the next instruction, read the updated key word or key expansion word and the data in the register Va and the register Vc after the key expansion round number from the register file {W 7,i-Nk ,W 6,i-Nk ,W 5,i-Nk ,W 4,i-Nk ,W 3,i-Nk ,W 2,i-Nk ,W 1,i-Nk ,W 0,i-Nk} and {Row 7,i ,Row 6,i ,Row 5,i ,Row 4,i ,Row 3,i ,Row 2,i ,Row 1,i ,Row 0,i} as the new source operand A and source operand C, complete the generation of 8 independent AES key expansion algorithm one key expansion word {W 7,i ,W 6,i ,W 5,i ,W 4,i ,W 3,i ,W 2,i ,W 1,i ,W 0,i}, finally get 8 groups of expanded key expansion words.

2. The method of claim 1, wherein the AES key expansion algorithm is accelerated by, ​ 3. The method of claim 1, wherein the AES key expansion algorithm is accelerated by, The AES-128 key expansion instructions are specifically: based on the key word or key expansion word {W} from 8 sets of independent AES-128 key expansion algorithms from registers Va and Vb. 7,i-Nk W 6,i-Nk W 5,i-Nk W 4,i-Nk W 3,i-Nk W 2,i-Nk W 1,i-Nk W 0,i-Nk }、{W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1 } and 8 unrelated AES key extension round numbers {Row} from register Vc 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i }, perform any round of key expansion using the AES-128 key expansion algorithm, and record the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i } is stored in the destination register Vd, where Row 7,i ~Row 0,i Valid values ​​are 4 to 43; in the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i In the context of}, for j equal to 0, 1, 2, 3, 4, 5, 6, 7, W j,i The generation logic of W is: j,i [31:0]=W j,i-Nk [31:0]XOR Temp j [31:0], where Nk = 4, XOR represents bitwise XOR, and Temp... j It is a 32-bit intermediate variable, when Row j,i When Temp is an integer multiple of Nk j The generation logic of Temp j [31:0] = SubWord(RotWord(W j,i-1 [31:0])) XOR Rcon[Row j,i / Nk], wherein the RotWord() function, the SubWord() function and the Rcon[Row j,i ] function are functions defined by the AES key expansion algorithm, Temp j,i [31:0] = W j [31:0] when Row j,i-1 is not an integer multiple of Nk; the RotWord() function, the SubWord() function and the Rcon[Row j,i ] function are directly implemented by hardware logic when performing any round of the AES-128 key expansion algorithm; 8 independent AES key expansion words can be generated in parallel by executing the AES-128 key expansion instruction once, and the registers Va, Vb and Vc are updated with a new key word or key expansion word and an AES key expansion round number each time; 8 independent key expansion words in the 4th to 43rd rounds of the AES-128 key expansion algorithm can be generated by consecutively executing the AES-128 key expansion instruction 40 times.

4. The method of claim 1, wherein the AES key expansion algorithm is accelerated by, The AES-192 key expansion instruction specifically refers to: using the key word or key expansion word {W} from 8 sets of independent AES-192 key expansion algorithms derived from registers Va and Vb. 7,i-Nk W 6,i-Nk W 5,i-Nk W 4,i-Nk W 3,i-Nk W 2,i-Nk W 1,i-Nk W 0,i-Nk }、{W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1 } and 8 unrelated AES key extension round numbers {Row} from register Vc 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i }, perform any round of key expansion using the AES-192 key expansion algorithm, and record the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i } is stored in the destination register Vd, where Row 7,i ~Row 0,i Valid values ​​are 6 to 51; in the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i In the context of}, for j equal to 0, 1, 2, 3, 4, 5, 6, 7, W j,i The generation logic of W is: j,i [31:0]=W j,i-Nk [31:0]XOR Temp j [31:0], where Nk = 6, XOR represents bitwise XOR, and Temp j It is a 32-bit intermediate variable, when Row j,i When Temp is an integer multiple of Nk j The generation logic of Temp j [31:0] = SubWord(RotWord(W j,i-1 [31:0])) XOR Rcon[Row j,i / Nk], wherein the RotWord() function, the SubWord() function and the Rcon[Row j,i ] function are functions defined by the AES key expansion algorithm, Temp j,i [31:0] = W j [31:0] when Row j,i-1 is not an integer multiple of Nk; the RotWord() function, the SubWord() function and the Rcon[Row j,i ] function are directly implemented by hardware logic when performing any round of the AES-192 key expansion algorithm; 8 independent AES key expansion words can be generated in parallel when the AES-192 key expansion instruction is executed once, and the registers Va, Vb and Vc are updated with a new key word or key expansion word and an AES key expansion round number each time; 8 independent key expansion words in the 6th to 51st rounds of the AES-192 key expansion algorithm can be generated when the AES-128 key expansion instruction is executed 46 times continuously.

5. The method of claim 1, wherein the AES key expansion algorithm is accelerated by, The AES-256 key expansion instruction specifically refers to: using the key word or key expansion word {W} from eight independent AES-256 key expansion algorithms derived from registers Va and Vb. 7,i-Nk W 6,i-Nk W 5,i-Nk W 4,i-Nk W 3,i-Nk W 2,i-Nk W 1,i-Nk W 0,i-Nk }、{W 7,i-1 W 6,i-1 W 5,i-1 W 4,i-1 W 3,i-1 W 2,i-1 W 1,i-1 W 0,i-1 } and 8 unrelated AES key extension round numbers {Row} from register Vc 7,i Row 6,i Row 5,i Row 4,i Row 3,i Row 2,i Row 1,i Row 0,i }, perform any round of key expansion using the AES-256 key expansion algorithm, and record the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i } is stored in the destination register Vd, where Row 7,i ~Row 0,i Valid values ​​range from 8 to 59; in the execution result {W 7,i W 6,i W 5,i W 4,i W 3,i W 2,i W 1,i W 0,i In the context of}, for j equal to 0, 1, 2, 3, 4, 5, 6, 7, W j,i The generation logic of W is: j,i [31:0]=W j,i-Nk [31:0]XOR Temp j [31:0], where Nk = 8, XOR represents bitwise XOR, and Temp j It is a 32-bit intermediate variable, when Row j,i When Temp is an integer multiple of Nk j The generation logic is: Temp j [31:0] = SubWord(RotWord(W j,i-1 [31:0]))XORRcon[Row j,i / Nk], where the RotWord() function, SubWord() function, and Rcon[Row] are used. j,i The function is defined by the AES key expansion algorithm. When Row j,i When Temp is divided by Nk, the remainder is 4. j The generation logic is: Temp j [31:0] = SubWord(W j,i-1 [31:0]), when Row j,i When it is any other value, Temp j [31:0]=W j,i-1 [31:0]; During any round of key expansion of the AES-256 key expansion algorithm, the RotWord() function, SubWord() function, and Rcon[Row] are used. j,i All functions are implemented directly using hardware logic; executing the AES-256 key extension instruction once can generate 8 independent AES key extension words in parallel. Each time, register Va, register Vb, and register Vc are updated with a new key word or key extension word and AES key extension round number. Executing the AES-128 key extension instruction 52 times consecutively can generate the 8th to 59th key extension words in the 8 unrelated AES-256 key extension algorithm.

6. An instruction set processor implementing an accelerated method of any of the AES key expansion algorithms of claims 1-5, characterized in that, The VAESKEYE instruction execution unit is used for receiving and executing a VAESKEYE extension instruction set; an input signal of the VAESKEYE instruction execution unit comprises one 256-bit source operand A, one 256-bit source operand B, one 256-bit source operand C and one 2-bit instruction control signal, and an output signal is one 256-bit execution result; the VAESKEYE instruction execution unit comprises an instruction control information processing unit and eight AES extension key word generation units which are executed in parallel, the instruction control information processing unit is used for controlling the AES extension key word generation units, and the AES extension key word generation units execute any one round of key expansion of a key expansion algorithm through hardware logic; the VAESKEYE extension instruction set comprises an AES-128 key expansion instruction, an AES-192 key expansion instruction and an AES-256 key expansion instruction.

7. The instruction set processor of claim 6, wherein, The execution delay of the AES-128 key expansion instruction, the AES-192 key expansion instruction and the AES-256 key expansion instruction is one clock; an output signal of the VAESKEYE instruction execution unit is bypassed to an input end of the VAESKEYE instruction execution unit to be used as a source operand B of a next instruction; and the instruction set processor supports pipeline execution of the AES-128 key expansion instruction, the AES-192 key expansion instruction and the AES-256 key expansion instruction.

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