Ramp Signal Correction Circuit Applied to CMOS Image Sensor

Abstract

The present invention discloses a ramp signal correction circuit applied to a CMOS image sensor, which includes a ramp signal generator. One input end of the ramp signal generator is respectively connected to a reference voltage V REF and an integration current I REF . The other input end of the ramp signal generator is connected to the left output end of a logic control circuit logic. The output end V RAMP of the ramp signal generator is connected to one input end of an analog-to-digital conversion circuit. One input end of the analog-to-digital conversion circuit is connected to the reference voltage V CM . The output end of the analog-to-digital conversion circuit is connected to the input end of the logic control circuit logic. The present invention realizes the correction of the ramp signal by correcting the configuration capacitor module. By using the circuit of the present invention, the accuracy of the ramp signal can be improved, and the imaging performance of the CMOS image sensor can be enhanced.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital conversion, and relates to a ramp signal correction circuit applied to a CMOS image sensor. Background Art

[0002] Due to the advantages of low power consumption and fast imaging speed of CMOS image sensors, they have received a great deal of attention. With the extensive development of image sensors, people have put forward higher requirements for the imaging quality of CMOS image sensors. As the quantization reference of the column-level analog-to-digital conversion circuit, the accuracy of the ramp signal will directly affect the analog-to-digital conversion result and thus affect the imaging quality.

[0003] However, in actual operation, the ramp signal will change with non-ideal factors such as PVT, which will deteriorate the accuracy of the ramp signal. However, the image sensor structures reported on the market so far have not effectively solved this problem. Summary of the Invention

[0004] The purpose of the present invention is to provide a ramp signal correction circuit applied to a CMOS image sensor. The circuit structure is based on error detection and dynamic trimming technology, which greatly improves the accuracy of the ramp signal.

[0005] The technical solution adopted by the present invention is that a ramp signal correction circuit applied to a CMOS image sensor includes a ramp signal generator. One input end of the ramp signal generator is respectively connected to a reference voltage V REF and an integration current I REF . The other input end of the ramp signal generator is connected to the left output end of a logic control circuit logic. The output end V RAMP of the ramp signal generator is connected to one input end of an analog-to-digital conversion circuit. One input end of the analog-to-digital conversion circuit is connected to a reference voltage V CM . The output end of the analog-to-digital conversion circuit is connected to the input end of the logic control circuit logic.

[0006] The characteristics of the present invention also lie in that:

[0007] The ramp signal generator includes an operational amplifier AMP. The non-inverting input end of the operational amplifier AMP is connected to a reference voltage V REF . The inverting input end of the operational amplifier AMP is respectively connected to the input end of a reference current I REF , the input end of a reset switch RST, one plate of an integration capacitor C3, and the input end of a configuration capacitor module. The inverting output end V RAMP of the operational amplifier AMP is respectively connected to the output end of the reset switch RST, the other plate of the integration capacitor C3, and the output end of the configuration capacitor module.

[0008] The configuration capacitor module includes switches Z1, Z2, ……, Z N and 2 N -1 unit configuration capacitor modules C2. The input ends of switches Z1, Z2, ……, Z N are all connected to the inverting input end of the operational amplifier AMP. The output ends of switches Z1, Z2, ……, Z N are respectively connected to one side plate of the unit configuration capacitor module C2; the other side plates of each unit configuration capacitor module C2 are all connected to V RAMP .

[0009] The unit configuration capacitor module C2 includes switches S1, S2, ……, S M and 2 M -1 capacitors C1. The input ends of switches S1, S2, ……, S M are respectively connected to the output ends of switches Z1, Z2, ……, Z N . The output ends of switches S1, S2, ……, S M are respectively connected to one side plate of the capacitor C1; the other side plates of each capacitor C1 are all connected to V RAMP .

[0010] In the normal working mode, switches Z1, Z2, ……, Z N are encoded as Nbit in binary and controlled by the logic control module logic. Switch Z1 is the lowest bit, and switch Z N is the highest bit. The working states of switches Z1, Z2, ……, Z N are set according to the error detection result, and the working states of switches S1, S2, ……, S M are configured according to the unit configuration capacitor correction result.

[0011] The beneficial effect of the present invention is that the present invention adopts a ramp signal correction circuit to reduce the influence of non-ideal factors such as PVT on the accuracy of the ramp signal and enhance the image quality. The present invention realizes the correction of the ramp signal by correcting the configuration capacitor module. The circuit of the present invention can improve the accuracy of the ramp signal and enhance the imaging performance of the CMOS image sensor. Description of the Drawings

[0012] Figure 1 is a schematic structural diagram of the ramp signal correction circuit applied to the CMOS image sensor of the present invention;

[0013] Figure 2 is a schematic correction diagram of the ramp signal correction circuit applied to the CMOS image sensor of the present invention. Detailed Embodiment

[0014] The present invention will be described in detail below with reference to the drawings and specific embodiments.

[0015] The ramp signal correction circuit applied to the CMOS image sensor in the present invention, as Figure 1 shown, includes a ramp signal generator, a logic control circuit logic, and an analog-to-digital conversion circuit. The present invention improves the ramp signal accuracy through error detection and dynamic trimming techniques.

[0016] Next, the working process of the entire circuit will be described in detail with reference to the attached Figure 2 drawings.

[0017] First, the reset process is described. During the reset process, switches Z1, Z2,..., Z N are disconnected, and switches S1, S2,..., S M are disconnected. At this time, the slope of the ramp signal is the largest. During the entire working process of the circuit, the reset switch RST always works periodically, and one period is one ramp period. The analog-to-digital conversion circuit performs an analog-to-digital conversion operation within one ramp period.

[0018] Next, the unit configuration capacitor correction process is described. During the unit configuration capacitor correction process, switches Z1, Z2,..., Z N are disconnected. Switches S1, S2,..., S M are encoded as M bits in binary and are controlled by the logic control module logic. Switch S1 is the least significant bit, and switch S M is the most significant bit. Then, switches S1, S2,..., S M are configured from all 0s to all 1s in sequence, and the analog-to-digital conversion circuit continuously performs analog-to-digital conversion operations within each ramp period. Next, the logic control module logic monitors the output of the analog-to-digital conversion circuit and stores the analog-to-digital conversion result when switches S1, S2,..., S M are configured with all 0s. After each configuration of switches S1, S2,..., S M , the analog-to-digital conversion result is compared with the analog-to-digital conversion result when configured with all 0s. When the output of the analog-to-digital conversion circuit changes for the first time, the logic control module logic stores the configuration information of switches S1, S2,..., S M . When the output of the analog-to-digital conversion circuit changes for the second time, the logic control module logic stores the configuration information of switches S1, S2,..., S M again. Then, the logic control module subtracts the configuration information of switches S1, S2,..., S M when the output of the analog-to-digital conversion circuit changes for the second time from that when it changes for the first time. The subtraction result is used as the unit configuration capacitor correction result to configure the states of switches S1, S2,..., S M in the normal working stage.

[0019] Next, the error detection stage is described.

[0020] During the error detection phase, switches Z1, Z2, ……, Z N are turned off, and switches S1, S2, ……, S M are turned off. In the logic control module logic, the analog-to-digital conversion results of quantifying V CM under an ideal ramp are pre-stored. During the error detection process, the ramp signal contains many non-ideal factors that affect the accuracy of the ramp signal and also affect the conversion results of the analog-to-digital conversion circuit. In the logic control module logic, the analog-to-digital conversion result under the ideal ramp is subtracted from the analog-to-digital conversion result in the error correction phase. The subtraction result is used as the error detection result to configure the states of switches Z1, Z2, ……, Z N in the normal working phase.

[0021] Finally, the normal working mode is described. In the normal working mode, switches Z1, Z2, ……, Z N are encoded in binary as Nbit and are controlled by the logic control module logic. Switch Z1 is the least significant bit, and switch Z N is the most significant bit. The working states of switches Z1, Z2, ……, Z N are set according to the error detection result. The working states of switches S1, S2, ……, S M are configured according to the unit capacitance correction result. Finally, after calibration, the ramp signal error caused by non-ideal factors such as PVT is corrected, and the accuracy of the ramp signal is improved.

Claims

1. A ramp signal correction circuit applied to a CMOS image sensor, characterized in that: It includes a ramp signal generator. One input terminal of the ramp signal generator is respectively connected to a reference voltage V REF and an integration current I REF . The other input terminal of the ramp signal generator is connected to the left output terminal of a logic control circuit logic. The output terminal V RAMP of the ramp signal generator is connected to one input terminal of an analog-to-digital conversion circuit. One input terminal of the analog-to-digital conversion circuit is connected to the reference voltage V CM . The output terminal of the analog-to-digital conversion circuit is connected to the input terminal of the logic control circuit logic; The ramp signal generator includes an operational amplifier AMP. The non-inverting input terminal of the operational amplifier AMP is connected to a reference voltage V REF , and the inverting input terminal of the operational amplifier AMP is respectively connected to the input terminal of a reference current I REF , the input terminal of a reset switch RST, one side plate of an integrating capacitor C3, and the input terminal of a configuration capacitor module. The inverting output terminal V RAMP of the operational amplifier AMP is respectively connected to the output terminal of the reset switch RST, the other side plate of the integrating capacitor C3, and the output terminal of the configuration capacitor module; The configured capacitance module includes switches Z1, Z2, ……, Z N and 2 N to -1 unit configured capacitance modules C2. The input terminals of the switches Z1, Z2, ……, Z N are all connected to the inverting input terminal of the operational amplifier AMP. The output terminals of the switches Z1, Z2, ……, Z N are respectively connected to one side plate of the unit configured capacitance module C2; the other side plates of each unit configured capacitance module C2 are all connected to V RAMP ; switch Z1 is connected to 2 0 unit configured capacitance modules C2. The capacitance formed by 2 0 unit configured capacitance modules C2 is 2 0 C2; switch Z2 is connected to 2 1 unit configured capacitance modules C2. The capacitance formed by 2 1 unit configured capacitance modules C2 is 2 1 C2; ……; switch Z N is connected to 2 N-1 unit configured capacitance modules C2. The capacitance formed by 2 N-1 unit configured capacitance modules C2 is 2 N-1 C2; The unit-configured capacitance module C2 includes switches S1, S2, ……, S M and 2 M to -1 capacitors C1. The input terminals of the switches S1, S2, ……, S M are respectively connected to the output terminals of the switches Z1, Z2, ……, Z N . The output terminals of the switches S1, S2, ……, S M are respectively connected to one side plate of the capacitor C1. The other side plates of all the capacitors C1 are connected to V RAMP ; The switch S1 is connected to 2 0 capacitors C1, and the capacitance formed by 2 0 capacitors C1 is 2 0 C1; The switch S2 is connected to 2 1 capacitors C1, and the capacitance formed by 2 1 capacitors C1 is 2 1 C1; The switch S3 is connected to 2 2 capacitors C1, and the capacitance formed by 2 2 capacitors C1 is 2 2 C1; ……; The switch S M is connected to 2 M-1 capacitors C1, and the capacitance formed by 2 M-1 capacitors C1 is 2 M-1 C1; During the entire operation of the circuit, the reset switch RST always works periodically. One period is a ramp period. The analog-to-digital conversion circuit performs an analog-to-digital conversion operation within one ramp period. During the unit configuration capacitor calibration process, switches Z1, Z2, ……, Z N are turned off, and switches S1, S2, ……, S M are encoded in binary as Mbit and controlled by the logic control module logic. Switch S1 is the least significant bit, and switch S M is the most significant bit; then, switches S1, S2, ……, S M are configured from all 0s to all 1s in sequence, and the analog-to-digital conversion circuit continuously performs analog-to-digital conversion operations during each ramp period; next, the logic control module logic monitors the output of the analog-to-digital conversion circuit and stores the analog-to-digital conversion result under the all-0 configuration of switches S1, S2, ……, S M ; after each configuration of switches S1, S2, ……, S M , the analog-to-digital conversion result is compared with the analog-to-digital conversion result under the all-0 configuration. When the output of the analog-to-digital conversion circuit changes for the first time, the logic control module logic stores the configuration information of switches S1, S2, ……, S M ; when the output of the analog-to-digital conversion circuit changes for the second time, the logic control module logic stores the configuration information of switches S1, S2, ……, S M again; the logic control module subtracts the configuration information of switches S1, S2, ……, S M stored when the output of the analog-to-digital conversion circuit changes for the second time from the configuration information of switches S1, S2, ……, SM stored when the output changes for the first time. The subtraction result is used as the unit configuration capacitor calibration result to configure the states of switches S1, S2, ……, S M during the normal operation stage; In the error detection phase, switches Z1, Z2, ……, Z N are turned off, and switches S1, S2, ……, S M are turned off; in the logic control module logic, the analog-to-digital conversion results of quantifying V CM under the ideal ramp are pre-stored. In the logic control module logic, the analog-to-digital conversion result under the ideal ramp is subtracted from the analog-to-digital conversion result in the error correction phase, and the subtraction result is used as the error detection result to configure the states of switches Z1, Z2, ……, Z N in the normal operation phase.

2. The ramp signal correction circuit applied to the CMOS image sensor according to claim 1, wherein: In the normal working mode, the switches Z1, Z2, ……, Z N are encoded in binary as Nbit and controlled by the logic control module logic. Switch Z1 is the least significant bit, and switch Z N is the most significant bit. The working states of switches Z1, Z2, ……, Z N are set according to the error detection result, and the working states of switches S1, S2, ……, S M are configured according to the unit configuration capacitance correction result.

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