Chip packaging structure and electronic equipment

Abstract

The embodiments of the present application provide a chip packaging structure and an electronic device, which relate to the field of chip packaging technology and are used to improve the problem of long interconnection paths between some chips while increasing the number of chips integrated in the electronic device. The chip packaging structure includes an interconnection substrate and at least one chip stacking structure. The chip stacking structure includes a first chip and a second chip that are vertically interconnected. The first chip includes a first metal layer, and the first metal layer includes an analog circuit. The second chip includes a second metal layer, and the second metal layer includes a digital circuit. An advanced process can be used to manufacture a second chip with a digital circuit to obtain a second chip with a smaller size and higher performance. A second chip with an analog circuit is manufactured using a sub-advanced process to ensure the performance and yield of the first chip.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure and electronic equipment. Background Art

[0002] With the development of semiconductor technology, in order to meet the requirements of diversified functions of electronic equipment, a variety of chips with different functions are integrated in the electronic equipment. At present, multiple chips or chip packaging structures can be set on the same circuit board, and the multiple chips or chip packaging structures can realize signal transmission through the conductive structure in the circuit board. However, the above-mentioned circuit board, as an interconnection medium between multiple chips or chip packaging structures, will cause the interconnection path between the chips or chip packaging structures to be too long, which is not conducive to improving the efficiency of signal transmission. Alternatively, multiple chips can be stacked, but the number of stacked chips is limited, which is not conducive to improving the integration of electronic equipment. Summary of the invention

[0003] The embodiments of the present application provide a chip packaging structure and an electronic device, which are used to improve the problem of long interconnection paths between some chips while increasing the number of chips integrated in the electronic device.

[0004] In order to achieve the above objectives, this application adopts the following technical solutions:

[0005] In one aspect of an embodiment of the present application, a chip packaging structure is provided. The chip packaging structure includes an interconnect substrate and at least one chip stacking structure. The chip stacking structure includes a first chip and a second chip. The active surface of the first chip faces the interconnect substrate, and the first chip is electrically connected to the interconnect substrate. The active surface of the second chip faces the back of the first chip, and the second chip is electrically connected to the first chip. Among them, the first chip includes a first substrate, a plurality of first through holes, and a first metal layer. The first through hole runs through the first substrate. The first metal layer is located on a side of the first substrate away from the second chip, and is electrically connected to the first through hole and the interconnect substrate. The first metal layer includes an analog circuit. The second chip includes a second substrate and a second metal layer. The second metal layer is located on a side of the second substrate close to the first chip, and is electrically connected to the first metal layer and the interconnect substrate through the first through hole; the second metal layer includes a digital circuit. In summary, the chip stacking structure in the chip packaging structure provided in the embodiment of the present application includes at least two chips vertically bonded using 3D integration technology, such as the above-mentioned first chip and second chip. In this way, in the chip packaging structure provided by the embodiment of the present application, multiple chips in the chip stacking structure are vertically bonded using 3D integration technology, so that vertical interconnection can be achieved between multiple chips in the chip stacking structure, thereby reducing the interconnection path and improving the efficiency of signal transmission. In addition, for the first chip as an analog chip, due to the constraints of factors such as the reliability and precision of the transistor in the analog chip process, it is difficult to reduce the size of the transistor, so a process of about 65nm (the minimum line width of the transistor in the chip) can be used to prepare the above-mentioned first chip. However, for the second chip as a digital chip, a more advanced process of 7nm or 5nm (the minimum line width of the transistor in the chip) can be used to prepare the second chip, so as to obtain a second chip with a smaller size and higher performance, and reduce the cost of the product. On this basis, a first through hole is made on the first substrate of the first chip, and the first chip is an analog chip. It can be seen from the above that the preparation process used to make the analog chip has a larger line width of the transistor obtained, for example, about 65nm, and the process is more mature. Therefore, the first chip as the analog chip is arranged close to the interconnection substrate, and the first through hole is arranged in the first chip, which is beneficial to improving the yield of the first through hole.

[0006] Optionally, the analog circuit includes a plurality of capacitors, and the capacitors are integrated in the first metal layer, so that the capacitors in the analog circuit can be prepared when the first chip is prepared, and there is no need to separately set capacitors on the interconnect substrate.

[0007] Optionally, the analog circuit includes at least a portion of an analog control module in the power management unit for processing analog signals. The digital circuit includes a digital control module in the power management unit for processing digital signals, and a central processing unit or a system on a chip. Among them, the power management unit is used to supply power to the central processing unit or the system on a chip. In this way, since the first chip and the second chip are vertically bonded, the power supply path is the above-mentioned vertical power supply path, so the power supply efficiency of the power management unit to the central processing unit or the system on a chip, and the integration of the power management unit with the central processing unit or the system on a chip can be improved. It is beneficial to improve the computing power of the central processing unit or the system on a chip, and the platform competitiveness of electronic devices having the chip packaging structure.

[0008] Optionally, the interconnect substrate is a redistribution layer. The first chip further includes a plurality of first under-bump metal pads, and the first under-bump metal pads are located on a side of the first metal layer away from the first substrate. The first under-bump metal pads are electrically connected to the first metal layer and the metal traces in the redistribution layer. In this way, the first metal layer in the first chip can be electrically connected to the redistribution layer through the first under-bump metal pads.

[0009] Optionally, the analog circuit includes a plurality of first inductors, and the first inductors are integrated into the metal wiring of the redistribution layer. In this way, the first inductors can be prepared during the process of making the redistribution layer, and there is no need to separately set the first inductors on the interconnect substrate.

[0010] Optionally, the chip packaging structure also includes at least one third chip. The active surface of the third chip faces the interconnect substrate, and the third chip and the chip stacking structure are located on the same side of the interconnect substrate. At this time, the chip stacking structure and the third chip adopt 2.5D integration technology, so that the two can achieve signal transmission through the interconnect substrate. In this way, relative to the chip packaging structure prepared only by 3D integration technology, the present application combines 3D integration technology with 2.5D integration technology, and can integrate a larger number of chips without increasing the difficulty of the process. In addition, the third chip includes a third substrate, a third metal layer and a plurality of second under-bump metal pads located on one side of the third substrate close to the interconnect substrate in sequence. The second under-bump metal pad is electrically connected to the third metal layer and the metal routing in the redistribution layer. In this way, the third chip can be electrically connected to the chip stacking structure through the redistribution layer.

[0011] Optionally, the interconnect substrate includes an adapter plate, the adapter plate includes a fourth substrate, a rewiring structure arranged in the fourth substrate, and a plurality of second through holes that penetrate a portion of the fourth substrate. The rewiring structure is arranged on a side of the second through hole close to the chip stacking structure, and the metal routing in the rewiring structure is electrically connected to the second through hole. The first chip also includes a plurality of first under-bump metal pads, and the first under-bump metal pads are located on a side of the first metal layer away from the first substrate. The chip packaging structure also includes a plurality of first micro-bumps, and the first micro-bumps are located between the chip stacking structure and the interconnect substrate. A first micro-bump is electrically connected to a first under-bump metal pad and a metal routing in the rewiring structure. In this way, the chip stacking structure can be electrically connected to the second through hole in the adapter plate through the first micro-bumps, the rewiring structure, and the second through hole.

[0012] Optionally, the chip packaging structure also includes at least one third chip. The active surface of the third chip faces the interconnect substrate, and the third chip and the chip stacking structure are located on the same side of the interconnect substrate. The technical effect of the third chip and the chip stacking structure being located on the same side of the interconnect substrate is the same as described above and will not be repeated here. In addition, the third chip includes a third substrate, a third metal layer, and a plurality of second under-bump metal pads located on the side of the third substrate close to the interconnect substrate in sequence. The chip packaging structure also includes a plurality of second micro-bumps, and the second micro-bumps are located between the third chip and the interconnect substrate. A second micro-bump is electrically connected to a second under-bump metal pad and a metal trace in the rewiring structure. In this way, the third chip can be electrically connected to the chip stacking structure through an adapter plate.

[0013] Optionally, the first chip also includes a plurality of third metal pads under bumps, and a third metal pad under bumps is electrically connected to a first through hole. The second chip also includes a plurality of fourth metal pads under bumps, and the fourth metal pad under bumps is electrically connected to the second metal layer. The chip stacking structure also includes a plurality of third micro-bumps and a plurality of fourth micro-bumps located between the first chip and the second chip. A third micro-bump is bonded to a third metal pad under bumps. A fourth micro-bump is bonded to a fourth metal pad under bumps and a third micro-bump. It can be seen from this that the fourth metal pad under bumps, the fourth micro-bumps, the third micro-bumps, the third metal pad under bumps, and the first through hole can constitute a vertical interconnection path between the second metal layer and the first metal layer, so that there is a shorter signal transmission distance between the first chip and the second chip, thereby improving the efficiency of signal transmission between the first chip and the second chip.

[0014] Optionally, the third chip includes an interface chip or a memory chip. In this way, the chip packaging structure can integrate a system-on-chip module (i.e., a chip stacking structure) with computing and power supply capabilities, and an interface chip and a memory chip, thereby increasing the number of integrated chips in the chip packaging structure on the basis of improving the chip power supply efficiency, thereby improving the chip integration of the chip packaging structure.

[0015] Optionally, the chip packaging structure further includes a packaging substrate. The packaging substrate is located on a side of the interconnection substrate away from the chip stacking structure. The chip packaging structure further includes a plurality of fifth micro-bumps, and the fifth micro-bumps are located between the packaging substrate and the interconnection substrate. The fifth micro-bumps are used to electrically connect the packaging substrate and the interconnection substrate. In this way, the chip stacking structure and the third chip can be electrically connected to the packaging substrate through the interconnection substrate and the fifth micro-bumps.

[0016] Optionally, the analog circuit includes a plurality of second inductors, and the second inductors are integrated in the packaging substrate. In this way, the second inductors can be prepared during the process of manufacturing the packaging substrate, thereby eliminating the need to separately set the second inductors on the interconnection substrate.

[0017] Optionally, the chip packaging structure further includes a plastic encapsulation layer, which wraps the chip stacking structure and the periphery of the third chip and is connected to the interconnect substrate. The plastic encapsulation layer can wrap the chip stacking structure and the periphery of the third chip to protect and reinforce the chip stacking structure and the third chip.

[0018] Optionally, the chip packaging structure further includes a thermal interface material layer, a heat dissipation cover, and a base glue. The thermal interface material layer covers the chip stacking structure and the surface of the third chip on one side away from the interconnection substrate. The heat dissipation cover covers the thermal interface material layer and is connected to the packaging substrate. Under the heat conduction effect of the thermal interface material layer, the heat generated by the chip stacking structure and the third chip can be introduced into the heat dissipation cover to dissipate heat through the heat dissipation cover. In addition, the base glue is arranged between the interconnection substrate and the packaging substrate to protect the micro bumps between the interconnection substrate and the packaging substrate.

[0019] Another aspect of the embodiment of the present application provides an electronic device, including a printed circuit board and any one of the chip packaging structures described above. The chip packaging structure is electrically connected to the printed circuit board. The electronic device has the same technical effect as the chip packaging structure provided in the above embodiment, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of some components of an electronic device provided in an embodiment of the present application;

[0021] Figure 2A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0022] Figure 3a A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0023] Figure 3b for Figure 3a A schematic diagram of the structure of the first chip;

[0024] Figure 4 for Figure 3a A schematic diagram of a chip stacking structure;

[0025] Figure 5 for Figure 3a Another schematic diagram of the structure of the chip stacking structure;

[0026] Figure 6a , Figure 6b , Figure 6c Made for Figure 5 Schematic diagram of the manufacturing process of the chip stacking structure shown;

[0027] Figure 7 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0028] Figure 8a A schematic diagram of a chip packaging structure using a fan-out type packaging cover provided in an embodiment of the present application;

[0029] Figure 8b For Figure 8a A schematic diagram showing a fifth micro-bump disposed below the redistribution layer;

[0030] Figure 8c A schematic diagram of another chip packaging structure using a fan-out type packaging cover provided in an embodiment of the present application;

[0031] Figure 8d For the general Figure 8c A schematic diagram of the structure shown being connected to a packaging substrate;

[0032] Figure 8e For Figure 8d A schematic diagram of a structure in which a heat dissipation cover and a solder ball array are added to the structure shown;

[0033] Figure 9a A schematic diagram of the structure of the adapter board provided in the embodiment of the present application;

[0034] Figure 9b A schematic diagram of a chip packaging structure using an adapter plate provided in an embodiment of the present application;

[0035] Fig.9cA schematic diagram of another chip packaging structure using an adapter plate provided in an embodiment of the present application;

[0036] Figure 9d For the general Fig.9c A schematic diagram of the structure shown being connected to a packaging substrate;

[0037] Fig.9e For Figure 9d A schematic diagram of a structure in which a heat dissipation cover and a solder ball array are added to the structure shown.

[0038] Reference numerals:

[0039] 01-electronic device; 10-chip packaging structure; 11-PCB; 12-BGA; 20-interconnect substrate; 30-chip stacking structure; 301-first chip; 302-second chip; 40-third chip; 311-first substrate; 312-first metal layer; 313-first through hole; 321-second substrate; 322-second metal layer; 41-third substrate; 42-third metal layer; 300-dielectric layer; 31-metal trace; 32-through hole; 403-third metal pad under bump; 404-fourth metal pad under bump Solder pad; 503-third micro-bump; 504-fourth micro-bump; 330-digital control module; 401-first metal pad under the bump; 500-carrier; 402-second metal pad under the bump; 50-rewiring layer; 60-copper pillar; 505-fifth micro-bump; 70-plastic layer; 80-packaging substrate; 51-bottom glue; 71-heat dissipation cover; 72-thermal interface material layer; 90-adapter; 901-fourth substrate; 902-rewiring structure; 903-second through hole; 501-first micro-bump; 502-second micro-bump. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0041] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0042] In addition, in the present application, directional terms such as "up", "down", "left" and "right" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to the changes in the orientation of the components in the drawings.

[0043] In this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. In addition, the term "electrical connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0044] The embodiment of the present application provides an electronic device. The electronic device may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and other devices that need to be charged. The above-mentioned electronic device may also be a rechargeable electric car, a rechargeable small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, and other electronic devices. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device.

[0045] The electronic device 01, such as Figure 1 As shown, it may include a chip packaging structure 10 and a printed circuit board (PCB) 11. The chip packaging structure 10 may be electrically connected to the PCB 11 through a ball grid array (BGA) 12 or a plurality of copper pillar bumps arranged in an array. Thus, the chip stacking structure 30 can realize signal transmission with other chips or chip stacking structures on the PCB.

[0046] The structure of the chip packaging structure 10 is described in detail below.

[0047] like Figure 2 As shown, the chip package structure 10 may include an interconnect substrate 20 and a chip stacking structure 30. The chip stacking structure 30 includes a stacked first chip 301 and a second chip 302. The active surface F1 of the first chip 301 faces the interconnect substrate 20. In addition, the first chip 301 is electrically connected to the interconnect substrate 20. The active surface F2 of the second chip 302 faces the back surface B1 of the first chip 301. In addition, the second chip 302 is electrically connected to the first chip 301.

[0048] In this way, the first chip 301 and the second chip 302 can be stacked along a direction Y perpendicular to the upper surface A1 of the interconnection substrate 20. At this time, the integration mode of the first chip 301 and the second chip 302 is a three-dimensional (3D) integration mode. In this case, the interconnection mode between the first chip 301 and the second chip 302 is a vertical interconnection, and the interconnection path is short, so that the efficiency of signal transmission between the first chip 301 and the second chip 302 can be improved.

[0049] It should be noted that the above description is based on the example that the chip stacking structure 30 includes two vertically stacked first chips 301 and second chips 302. In other embodiments of the present application, when the chip stacking process can meet the performance requirements of electronic products, in the above chip stacking structure 30, the remaining chips can also be stacked on the back side B2 of the second chip 302 along the direction Y perpendicular to the upper surface A1 of the interconnect substrate 20. The stacking method of the remaining chips is the same as the stacking method of the first chip 301 and the second chip 302, and will not be described in detail here.

[0050] In addition, if Figure 2 As shown, the chip package structure 10 further includes at least one third chip 40. The chip stacking structure 30 and the third chip 40 may be both located on the same side of the interconnection substrate 20. For example, the chip stacking structure 30 and the third chip 40 are both disposed on the upper surface A1 of the interconnection substrate 20. Moreover, the active surface F3 of the third chip 40 faces the interconnection substrate 20, and the third chip 40 may be electrically connected to the interconnection substrate 20.

[0051] It should be noted that any chip in the embodiments of the present application may include a substrate and a circuit structure disposed on the substrate, and the circuit structure may enable the chip to realize its own functions during operation, such as logical operations or data storage, etc. Among them, the material constituting the above-mentioned substrate may include glass, amorphous silicon (a-Si), or silicon carbide (SiC), etc. The surface of the side of the above-mentioned circuit structure in the chip away from the substrate may be called the active surface F of the chip, and the surface of the side of the substrate away from the circuit structure may be called the back side B of the chip.

[0052] For example, Figure 3a As shown, the first chip 301 may include a first substrate 311 and a first metal layer 312. The first metal layer 312 is located on a side of the first substrate 311 away from the second chip 302. The first metal layer 312 is used to form a circuit structure of the first chip 301. In addition, in order to allow the second chip 302 located above the first chip 301 to be electrically connected to the first chip 301, as shown in FIG. Figure 3aAs shown, the first chip 301 may further include a first through hole 313 penetrating the first substrate 311 .

[0053] It should be noted that, in the embodiment of the present application, the metal layer arranged on the substrate in the chip, such as the above-mentioned first substrate 311, such as the above-mentioned first metal layer 312, not only includes electronic components made on the substrate, such as transistors, but also includes a plurality of layers located on the side of the electronic component away from the substrate for electrically connecting multiple electronic components together. Metal wiring.

[0054] For example, when the first substrate 311 is a silicon substrate made of a semiconductor material containing silicon, the first through hole 313 formed on the silicon substrate may be referred to as a through silicon via (STV).

[0055] The first metal layer 312 may include: Figure 3b The multi-layer metal wiring 31 shown is made of metal material. The first chip 301 may also include a dielectric layer 300 made of resin material. Two adjacent layers of metal wiring 31 in the first metal layer 312 may be separated by the dielectric layer 300. In addition, in order to enable the metal wiring 31 of different layers to be electrically connected, the first metal layer 312 may also include a through hole 32 made on the dielectric layer 300, and the two adjacent layers of metal wiring 31 may be electrically connected through the through hole 32.

[0056] In addition, if Figure 3a As shown, the second chip 302 may include a second substrate 321 and a second metal layer 322. The second metal layer 322 is located on a side of the second substrate 321 close to the first chip 301. In addition, the second metal layer 322 may be electrically connected to the interconnection substrate 20 and the first metal layer 312 in the first chip 301 through a first through hole 313 provided on the first substrate 311 of the first chip 301. In this way, the second chip 302 may transmit signals to the first chip 301, and the second chip 302 may transmit signals to the interconnection substrate 20 through the first chip 301. The second metal layer 322 is arranged in the same manner as described above and will not be described in detail here.

[0057] Based on this, in order to enable the vertically stacked first chip 301 and the second chip 302 to be electrically connected to achieve signal transmission, as shown in FIG. Figure 4As shown, the first chip 301 further includes a plurality of third under bump metallization (UBM) pads 403. One third under bump metallization pad 403 is electrically connected to one first via 313. The second chip 302 further includes a plurality of fourth under bump metallization pads 404. The fourth under bump metallization pad 404 is electrically connected to the second metal layer 322.

[0058] In addition, the chip stacking structure 30 also includes a plurality of third micro bumps (μbump) 503 and a plurality of fourth micro bumps 504 located between the first chip 301 and the second chip 302. Among them, a third micro bump 503 is bonded to a third under-bump metal pad 403. A fourth micro bump 504 is bonded to a fourth under-bump metal pad 404 and a third micro bump 503. In this way, the second metal layer 322 in the second chip 302 can be electrically connected to the first metal layer 312 in the first chip 301 through a plurality of fourth under-bump metal pads 404, a plurality of fourth micro bumps 504, a plurality of third micro bumps 503, a plurality of third under-bump metal pads 403, and a plurality of first through holes 313.

[0059] It can be seen from this that the fourth under-bump metal pad 404, the fourth micro-bump 504, the third micro-bump 503, the third under-bump metal pad 403 and the first through hole 313 can constitute a vertical interconnection path between the second metal layer 322 and the first metal layer 312, so that there is a shorter signal transmission distance between the first chip 301 and the second chip 302, thereby improving the efficiency of signal transmission between the first chip 301 and the second chip 302.

[0060] In addition, by the same token, Figure 3a As shown, the third chip 40 located on one side of the chip stacking structure 30 may include a third substrate 41 and a third metal layer 42 located on the side of the third substrate 41 close to the interconnection substrate 20. The third metal layer 42 is arranged in the same manner as described above and will not be described again here. The third metal layer 42 is used to form a circuit structure of the third chip 40, which can be electrically connected to the interconnection substrate 20, so that signal transmission can be achieved through the interconnection substrate 20 and the first chip 301 and the second chip 302 in the chip stacking structure 30.

[0061] As can be seen from the above, the first chip 301 is electrically connected to the interconnection substrate 20, the second chip 302 is electrically connected to the first chip 301, and the third chip 40 is also electrically connected to the interconnection substrate 20. Therefore, the first chip 301 can transmit signals with the interconnection substrate 20, and the second chip 302 can transmit signals through the first chip 301 and the interconnection substrate 20. In this case, the first chip 301 and the second chip 302 in the chip stacking structure 30 can be indirectly electrically connected to the third chip 40 through the interconnection substrate 20, so that the first chip 301 and the second chip 302 can transmit signals through the interconnection substrate 20 and the third chip 40. At this time, the integration mode of the chip stacking structure 30 and the third chip 40 is a 2.5D integration mode.

[0062] It should be noted that the embodiment of the present application does not limit the number of third chips 40 , and the number of third chips 40 may be limited according to the size of the upper surface A1 of the interconnect substrate 20 and the package size of the third chips 40 .

[0063] In summary, the chip packaging structure 10 provided in the embodiment of the present application includes at least one chip stacking structure 30 and at least one third chip 40. Among them, the chip stacking structure 30 includes at least two chips vertically bonded using 3D integration technology, such as the first chip 301 and the second chip 302 mentioned above. The chip stacking structure 30 and the third chip 40 adopt 2.5D integration technology, so that the two can achieve signal transmission through the interconnection substrate 20. In this way, on the one hand, relative to the chip packaging structure 10 prepared only by 3D integration technology, the present application combines 3D integration technology and 2.5D integration technology, and can integrate a larger number of chips without increasing the process difficulty. On the other hand, in the chip packaging structure 10 provided in the embodiment of the present application, multiple chips in the chip stacking structure 30 are vertically bonded using 3D integration technology, so that vertical interconnection can be achieved between multiple chips in the chip stacking structure 30, thereby reducing the interconnection path and improving the efficiency of signal transmission.

[0064] On this basis, in some embodiments of the present application, Figure 4 In the chip stacking structure 30 shown, the first chip 301 may be an analog chip, and the second chip 302 may be a digital chip. In this case, the first metal layer 312 of the first chip 301 may include an analog circuit. At this time, the circuit structure of the first chip 301 mainly composed of the first metal layer 312 can be used to transmit, transform, process, amplify, measure and display analog signals. Among them, the analog signal is a continuously changing electrical signal. For example, the analog circuit mainly composed of the first metal layer 312 may include an amplification circuit, a signal operation circuit, a signal processing circuit, an oscillation circuit, a modulation and demodulation circuit, and a power supply circuit.

[0065] In addition, the second metal layer 322 of the second chip 302 may include a digital circuit. In this case, the circuit structure of the second chip 302 mainly composed of the second metal layer 322 can be used to perform arithmetic operations and logic operations on digital signals.

[0066] For example, the digital circuit in the second chip 302 may include a central processing unit (CPU) or a system on a chip (SOC). Figure 5 As shown, the digital circuit in the second chip 302 may also include a digital control module 330 in a power management unit (PMU) for processing analog signals. The analog circuit in the first chip 301 may include at least a portion of an analog control module in a PMU for processing digital signals.

[0067] For example, in the case where the PMU includes an LC oscillating circuit, the capacitor C in the LC oscillating circuit, such as Figure 5 As shown, it can be integrated in the first metal layer 312. In this way, the capacitor C can be prepared in the process of making the first metal layer 312, so there is no need to set the capacitor C separately on the interconnect substrate 20. Figure 5 The position of capacitor C is a schematic position and does not represent the actual position of capacitor C.

[0068] As can be seen from the above, the first metal layer 312 includes multiple layers of metal traces 31 made of metal materials. In this case, the above-mentioned capacitor C can be formed between two adjacent layers of metal traces 31. For example, when the first metal layer 312 includes 10 layers of metal traces 31, a portion of the 8th layer of metal traces 31 can be used as the lower substrate of the capacitor C, and a portion of the 9th layer of metal traces 31 can be used as the upper substrate of the capacitor C. The capacitor C in the LC oscillation circuit can store and release electric energy during the process of charging management of the PMU.

[0069] In this case, the PMU in the first chip 301 can supply power to the CPU or SOC in the second chip 302. At this time, the chip stacking structure 30 composed of the first chip 301 and the second chip 302 can be used as a system on integrated chips (SOIC) module with computing and power supply capabilities.

[0070] In this way, since the first chip 301 and the second chip 302 are vertically bonded, their power supply path is the vertical power supply path, so the power supply efficiency of the PMU to the CPU or SOC and the integration of the PMU and the CPU or SOC can be improved. This is conducive to improving the computing power of the CPU or SOC and the platform competitiveness of the electronic device 01 having the chip packaging structure 10.

[0071] In addition, from the above, it can be seen that the digital control module 330 and the analog control module in the PMU can be disassembled, and the digital control module 330 and the CPU or SOC can be integrated into the digital circuit in the second chip 302 mainly composed of the second metal layer 322, and the analog control module can be integrated into the analog circuit in the first chip 301 mainly composed of the first metal layer 312.

[0072] In this case, for the first chip 301 as an analog chip, due to the constraints of factors such as the reliability and precision of the transistors in the analog chip process, it is difficult to reduce the size of the transistors, so a process of about 65nm (the minimum line width of the transistors in the chip) can be used to prepare the first chip 301. However, for the second chip 302 as a digital chip, a more advanced process of 7nm or 5nm (the minimum line width of the transistors in the chip) can be used to prepare the second chip 302, thereby obtaining a second chip 302 with a smaller size and higher performance, thereby reducing the cost of the product.

[0073] On this basis, Figure 5 It can be seen that the first substrate 311 of the first chip 301 is provided with a first through hole 313, and the first chip 301 is an analog chip. As can be seen from the above, the manufacturing process used to manufacture the analog chip has a relatively large line width of transistors, for example, about 65nm, and the process is relatively mature. Therefore, the first chip 301 as an analog chip is arranged close to the interconnection substrate 20, and the first through hole 313 is arranged in the first chip 301, which is conducive to improving the yield of the first through hole 313.

[0074] It should be noted that the above description is based on the example that the first chip 301 is an analog chip and the second chip 302 is a digital chip. When making through holes on a digital chip can meet the process yield and cost requirements, in other embodiments of the present application, the first chip 301 can be a digital chip and the second chip 302 can be an analog circuit. In this case, the digital control module 330 in the PMU can be integrated with the CPU or SOC in the first chip 301 close to the interconnect substrate 20, and the analog control module in the PMU can be integrated in the second chip 302 away from the interconnect substrate 20. In this case, the first through hole 313 is made in the first chip 301 as a digital chip.

[0075] In addition, the above description is based on the example of separating the digital control module 330 and the analog control module in the PMU and integrating them into different chips. In other embodiments of the present application, the digital control module and the analog control module in other core (intellectual property, IP) circuits can also be separated and integrated into different chips in the chip stacking structure 30 when issued.

[0076] By way of example, the IP circuit may include a high band width memory (HBM) circuit, a physical layer device (PHY), a peripheral component interconnect express (PCI-Express) circuit, a double data rate physical (DDR PHY), or a parallel input / output (IO) interface circuit.

[0077] The following Figure 5 The manufacturing method of the chip stacking structure 30 shown in FIG. Figure 6a As shown, a first metal layer 312 and a dielectric layer 300 are prepared on a first substrate 311 formed of a silicon wafer. Next, a first through hole 313 is made. One end of the first through hole 313 is electrically connected to the first metal layer 312, and the other end penetrates into the first substrate 311.

[0078] When the circuit structure formed by the first metal layer 312 includes an analog control module of the PMU, the capacitor C in the analog control module can be integrated into the first metal layer 312 while the first metal layer 312 is manufactured. The integration method of the capacitor C is the same as described above and will not be repeated here. In addition, a plurality of first under-bump metal pads 401 can be manufactured on a side of the first metal layer 312 away from the first substrate 311, and the first under-bump metal pads 401 are electrically connected to the first metal layer 312.

[0079] Next, if Figure 6bAs shown, the side where the first substrate 311 is located is upward, and a temporary bonding process is used on the side where the first under-bump metal pad 401 is located to bond a carrier wafer 500. Next, the first substrate 311 is thinned to expose one end of the first through hole 313. Then, a third under-bump metal pad 403 and a third micro-bump 503 bonded to the third under-bump metal pad 403 are formed on the first through hole 313.

[0080] Next, if Figure 6c As shown, on the second substrate 321 formed by another silicon wafer, a second metal layer 322 is manufactured. The digital control module 330, CPU or SOC in the above-mentioned PMU can be integrated in the second metal layer 322. Then, a fourth under-bump metal pad 404 electrically connected to the second metal layer 322 and a fourth micro-bump 504 bonded to the fourth under-bump metal pad 404 are manufactured. Next, a plurality of third micro-bumps 503 are bonded to a plurality of fourth micro-bumps 504 one by one.

[0081] Next, mechanical grinding or laser cutting can be used to remove Figure 6c The carrier board 500 shown in FIG. 1 is removed, and the structure after the carrier board 500 is removed is cut, so that a plurality of structures as shown in FIG. 1 and FIG. Figure 5 The chip stacking structure 30 is shown.

[0082] Next, the chip stacking structure 30 and the third chip may be bonded to the same side of the interconnection substrate 20 to form a Figure 7 The chip packaging structure 10 shown. For example, the third chip may be an I / O interface chip or an HBM memory chip. Figure 7 The chip packaging structure 10 shown may include at least two third chips, for example, a third chip 40a and a third chip 40b respectively located on both sides of the chip stacking structure 30. The third chip 40a may be the above-mentioned I / O interface chip, and the third chip 40b may be the above-mentioned HBM memory chip. In this way, the chip packaging structure 10 may integrate a SOIC module (i.e., the chip stacking structure 30) with computing and power supply capabilities, and an I / O interface chip and an HBM memory chip, so that the number of integrated chips in the chip packaging structure 10 can be increased on the basis of improving the chip power supply efficiency, thereby improving the chip integration of the chip packaging structure 10.

[0083] Next, the structure of the interconnection substrate 20 and the bonding method of the chip stacking structure 30 and the third chip 40 to the interconnection substrate 20 are described by way of examples in combination with different examples.

[0084] Example 1

[0085] In this example, the interconnect substrate 20 may be Figure 8a The redistribution layer (RDL) 50 is shown. During the manufacturing process, multiple layers of metal traces 31 and dielectric layers 300 may be manufactured on a substrate 500 to form the RDL 50.

[0086] Based on this, in the first chip 301, the analog circuit includes at least a part of the analog control module in the PMU, and when the PMU includes an LC oscillating circuit, a part of the inductance in the LC oscillating circuit, for example Figure 8a The first inductor L1 shown can be integrated into the metal trace 31 in the redistribution layer 50. In this way, the first inductor L1 can be prepared during the process of manufacturing the redistribution layer 50, so there is no need to separately set an inductor on the interconnection substrate 20.

[0087] The first inductor L1 in the LC oscillation circuit can buffer the charging and discharging process of the capacitor C during the charging management of the PMU, so that the amount of electricity in the capacitor C can gradually increase or decrease. The embodiment of the present application does not limit the number of the first inductor L1, and can be set according to the design requirements of the power supply architecture in the PMU.

[0088] Next, it can be known from the above that the first chip 301 in the chip stacking structure 30 has a plurality of first under-bump metal pads 401. The first under-bump metal pads 401 are located on a side of the first metal layer 312 in the first chip 301 away from the first substrate 311, and are bonded to the first metal layer 312. In this case, in order to electrically connect the chip stacking structure 30 with the redistribution layer 50, the first under-bump metal pads 401 can be electrically connected to the metal traces 31 in the redistribution layer 50 through the copper pillars 60.

[0089] In addition, it can be known from the above that the third chip 40 may include a third substrate 41, and a third metal layer 42 located on the side of the third substrate 41 close to the interconnect substrate 20. In addition, the third chip 40 may also include a plurality of second under-bump metal pads 402, and the second under-bump metal pads 402 are bonded to the third metal layer 42. In this case, in order to electrically connect the third chip 40 to the redistribution layer 50, the second under-bump metal pads 402 may be electrically connected to the metal traces in the redistribution layer 50 through the copper pillars 60.

[0090] Next, you can Figure 8a Then, the carrier board 500 is removed. Figure 8bAs shown, a fifth micro bump 505 is formed on the side of the redistribution layer 50 away from the chip stacking structure 30 and the third chip 40. The fifth micro bump 505 may be a controlled collapse chip connection (C4) bump.

[0091] Figure 8a and Figure 8b The description is made by taking the chip package structure 10 including a chip stacking structure 30 and a third chip 40 located on the redistribution layer 50 as an example. In other embodiments of the present application, Figure 8c As shown, the chip package structure 10 may include a chip stack structure 30 located on the redistribution layer 50 and third chips 40 located on the left and right sides of the chip stack structure 30 .

[0092] On this basis, if Figure 8c As shown, the chip package structure 10 may further include a molding layer 70. The molding layer 70 may wrap the chip stacking structure 30 and the periphery of the third chip 40 to protect and reinforce the chip stacking structure 30 and the third chip 40.

[0093] Next, the chip packaging structure 10 further includes: Figure 8d The package substrate 80 is shown. The package substrate 80 is located on the interconnect substrate, that is, the side of the above-mentioned redistribution layer 50 away from the chip stacking structure 30. The package substrate 80 can be electrically connected to the redistribution layer 50 through the fifth micro-bump 505 located below the redistribution layer 50. In order to protect the fifth micro-bump 505, a dispensing process can be used to fill the underfill 51 between the package substrate 80 and the redistribution layer 50.

[0094] Based on this, in the first chip 301, the analog circuit includes at least a part of the analog control module in the PMU, and when the PMU includes an LC oscillating circuit, a part of the inductance in the LC oscillating circuit, for example Figure 8d The second inductor L2 shown can be integrated into the packaging substrate 80. In this way, the second inductor L2 can be prepared during the process of manufacturing the packaging substrate 80, so that there is no need to separately set capacitors and inductors on the interconnection substrate 20.

[0095] The second inductor L2 in the LC oscillator circuit can buffer the charging and discharging process of the capacitor C during the charging management of the PMU, so that the amount of electricity in the capacitor C can gradually increase or decrease. The embodiment of the present application does not limit the number of the second inductor L2, and can be set according to the design requirements of the power supply architecture in the PMU.

[0096] Next, if Figure 8e As shown, a heat dissipation cover (lid) 71 is installed. A thermal interface material layer (TIM) 72 is provided between the heat dissipation cover 71 and the chip stacking structure 30 and the third chip 40. The thermal interface material layer 72 covers the chip stacking structure 30 and the third chip 40 away from the interconnection substrate, i.e., the side surface of the above-mentioned redistribution layer 50. The above-mentioned heat dissipation cover 71 covers the thermal interface material layer 72 and is connected to the packaging substrate 80. Under the heat conduction effect of the thermal interface material layer 72, the heat generated by the chip stacking structure 30 and the third chip 40 can be introduced into the heat dissipation cover 71 to dissipate heat through the heat dissipation cover 71.

[0097] Then, a BGA 12 is fabricated on a surface of the packaging substrate 80 that is away from the redistribution layer 50 , thereby completing the preparation of the chip packaging structure 10 .

[0098] As can be seen from the above, the method of using the redistribution layer 50 as the interconnection substrate 20 to electrically connect the chip stacking structure 30, the third chip 40 and the packaging substrate 80 to form the chip packaging structure 10 can be called a fan-out packaging method.

[0099] Example 2

[0100] In this example, the interconnect substrate 20 may be Figure 9a The interposer 90 shown in the figure includes a fourth substrate 901, a redistribution structure 902 disposed in the fourth substrate 901, and a plurality of second through holes 903 penetrating a portion of the fourth substrate 901. The redistribution structure 902 is disposed on a side of the second through hole 903 close to the chip stacking structure 30, and the metal traces 31 in the redistribution structure 902 are electrically connected to the second through hole 903.

[0101] Next, if Figure 9b As shown, the first chip 301 in the chip stacking structure 30 has a plurality of first under bump metal pads 401. The first under bump metal pads 401 are located on a side of the first metal layer 312 in the first chip 301 away from the first substrate 311.

[0102] In this case, in order to enable the chip stack structure 30 to be electrically connected to the interconnection substrate 20, as shown in FIG. Figure 9bAs shown, the chip packaging structure 10 further includes a plurality of first micro-bumps 501. The first micro-bumps 501 are located between the chip stacking structure 30 and the adapter plate 90. A first micro-bump 501 is electrically connected to a first under-bump metal pad 401 and a metal trace 31 in a redistribution structure 902. In this way, the chip stacking structure 30 can be electrically connected to the second through hole 903 in the adapter plate 90 through the first micro-bumps 501 and the redistribution structure 902.

[0103] In addition, if Figure 9b As shown, the third chip 40 may include a third substrate 41, a third metal layer 42, and a plurality of second under-bump metal pads 402, which are sequentially located on the side of the third substrate 41 close to the interconnect substrate 20. In addition, the second under-bump metal pads 402 are electrically connected to the third metal layer 42.

[0104] In this case, in order to electrically connect the third chip 40 to the adapter board 90, the chip packaging structure 10 further includes a plurality of second micro-bumps 502. The second micro-bumps 502 are located between the third chip 40 and the adapter board 90. A second micro-bump 502 is electrically connected to a second under-bump metal pad 402 and a metal trace 31 in the rewiring structure 902. In this way, the third chip 40 can be electrically connected to the second through hole 903 in the adapter board 90 through the second micro-bump 502 and the rewiring structure 902, so that the third chip 40 and the chip stacking structure 30 can realize signal transmission through the second through hole 903 in the adapter board 90.

[0105] Next, if Fig.9c As shown, a fifth micro bump 505 is formed on the side of the transfer board 90 away from the chip stacking structure 30 and the third chip 40. Figure 9b The description is made by taking the chip package structure 10 including a chip stacking structure 30 and a third chip 40 located on a transfer board 90 as an example. In other embodiments of the present application, Fig.9c As shown, the chip package structure 10 may include two chip stack structures 30 located on the transfer board 90 and third chips 40 located on the left and right sides of the two chip stack structures 30. The present application does not limit the number of chip stack structures 30 in the chip package structure 10.

[0106] In order to protect the first micro-bump 501 and the second micro-bump 502, a primer 51 may be filled between the chip stacking structure 30, the third chip 40 and the adapter board 90. Then, a plastic encapsulation layer 70 is made to wrap the chip stacking structure 30 and the periphery of the third chip 40. The function of the plastic encapsulation layer 70 is the same as described above and will not be repeated here.

[0107] Next, a fifth micro bump 505 is formed on the side of the adapter plate 90 away from the chip stacking structure 30. Figure 9d As shown, the transfer board 90 carrying the chip stacking structure 30 and the third chip 40 can be electrically connected to the package substrate 80 through the fifth micro bump 505. As above, in order to protect the fifth micro bump 505, the bottom glue 51 can be filled between the package substrate 80 and the transfer board 90.

[0108] As described above, in the case where the analog circuit in the first chip 301 includes at least a portion of the analog control module in the PMU, and the PMU includes an LC oscillating circuit, a portion of the inductance in the LC oscillating circuit, such as Fig.9e The second inductor L2 shown may be integrated into the packaging substrate 80 .

[0109] Next, if Fig.9e As shown, a heat dissipation cover (lid) 71 is installed. A thermal interface material layer 72 is provided between the heat dissipation cover 71 and the chip stacking structure 30 and the third chip 40. The arrangement of the thermal interface material layer 72 is the same as described above and will not be repeated here. Next, a BGA 12 is made on the surface of the packaging substrate 80 away from the redistribution layer 50, thereby completing the preparation of the chip packaging structure 10.

[0110] For any one of the above examples 1 and 2, the first chip 301 in the chip stacking structure 30 prepared by the 3D chip integration technology may integrate the analog control module in the PMU and the analog control module of the IP circuit. The second chip 302 may integrate the digital control module 330 in the PMU, the digital control module of the IP circuit, and the CPU or SOC. Thus, a vertical power supply path is provided between the PMU and the CPU or SOC, thereby improving the power supply efficiency of the PMU.

[0111] In addition, by using 2.5D chip integration technology, at least one third chip 40 can be integrated with the chip stacking structure 30 on the same redistribution layer 50 or adapter board 90. The third chip 40 can be an I / O interface chip or an HBM memory chip. Thus, the chip packaging structure 10 can integrate a SOIC module (i.e., the chip stacking structure 30) with computing and power supply capabilities, as well as an I / O interface chip and an HBM memory chip.

[0112] In addition, when at least two chip stacking structures 30 are integrated in the chip packaging structure 10, each SOIC module with computing and power supply capabilities (i.e., the chip stacking structure 30) has an independent power management function, and the power supply is not affected by other SOIC modules. Therefore, according to the product application requirements, multiple SOIC modules of different specifications can be integrated in the same chip packaging structure 10 to flexibly meet the product design requirements.

[0113] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: Interconnect substrate; At least one chip stacking structure; the chip stacking structure comprises a first chip and a second chip; the active surface of the first chip faces the interconnect substrate, and the first chip is electrically connected to the interconnect substrate; the active surface of the second chip faces the back surface of the first chip, and the second chip is electrically connected to the first chip; The first chip is an analog chip; the first chip includes: first base; A plurality of first through holes penetrating the first substrate; A first metal layer is located on a side of the first substrate away from the second chip and is electrically connected to the first through hole and the interconnect substrate; the first metal layer includes an analog circuit; The second chip is a digital chip; the second chip includes: Second base; The second metal layer is located on a side of the second substrate close to the first chip and is electrically connected to the first metal layer and the interconnection substrate through the first through hole; the second metal layer includes a digital circuit.

2. The chip packaging structure according to claim 1, characterized in that: The analog circuit includes a plurality of capacitors, and the capacitors are integrated in the first metal layer.

3. The chip packaging structure according to claim 1, characterized in that: The analog circuit includes at least a portion of an analog control module in a power management unit for processing analog signals; The digital circuit includes a digital control module in the power management unit for processing digital signals, and a central processing unit CPU or a system on chip SOC; Wherein, the power management unit is used to supply power to the CPU or the SOC.

4. The chip packaging structure according to claim 1, characterized in that: The interconnect substrate is a redistribution layer; The first chip also includes a plurality of first under-bump metal pads, which are located on a side of the first metal layer away from the first substrate; the first under-bump metal pads are electrically connected to the first metal layer and metal traces in the redistribution layer.

5. The chip packaging structure according to claim 4, characterized in that: The analog circuit includes a plurality of first inductors, and the first inductors are integrated into metal traces of the redistribution layer.

6. The chip packaging structure according to claim 4, characterized in that: The chip packaging structure further includes at least one third chip, the active surface of the third chip faces the interconnection substrate, and the third chip and the chip stacking structure are located on the same side of the interconnection substrate; The third chip includes: a third substrate, a third metal layer and a plurality of second under-bump metal pads located in sequence on the third substrate near the interconnect substrate; the second under-bump metal pads are electrically connected to the third metal layer and metal traces in the redistribution layer.

7. The chip packaging structure according to claim 1, characterized in that: The interconnect substrate comprises an adapter plate, the adapter plate comprises a fourth substrate, a redistribution structure arranged in the fourth substrate, and a plurality of second through holes penetrating a portion of the fourth substrate; the redistribution structure is arranged on a side of the second through hole close to the chip stacking structure, and the metal traces in the redistribution structure are electrically connected to the second through hole; The first chip further includes a plurality of first under-bump metal pads, wherein the first under-bump metal pads are located on a side of the first metal layer away from the first substrate; The chip packaging structure also includes a plurality of first micro-bumps, wherein the first micro-bumps are located between the chip stacking structure and the interconnection substrate; one of the first micro-bumps is electrically connected to one of the first under-bump metal pads and the metal routing in the redistribution structure.

8. The chip packaging structure according to claim 7, characterized in that: The chip packaging structure further includes at least one third chip, the active surface of the third chip faces the interconnection substrate, and the third chip and the chip stacking structure are located on the same side of the interconnection substrate; The third chip comprises: a third substrate, a third metal layer and a plurality of second under-bump metal pads sequentially located on a side of the third substrate close to the interconnect substrate; The chip packaging structure also includes a plurality of second micro-bumps, wherein the second micro-bumps are located between the third chip and the interconnect substrate; one of the second micro-bumps is electrically connected to one of the second under-bump metal pads and the metal routing in the redistribution structure.

9. The chip packaging structure according to claim 6 or 8, characterized in that: The third chip includes an interface chip or a storage chip.

10. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The first chip further includes a plurality of third under-bump metal pads, one of the third under-bump metal pads being electrically connected to one of the first through holes; The second chip further includes a plurality of fourth under-bump metal pads, wherein the fourth under-bump metal pads are electrically connected to the second metal layer; The chip stacking structure further includes: A plurality of third micro bumps are located between the first chip and the second chip; one of the third micro bumps is bonded to one of the third under-bump metal pads; A plurality of fourth micro-bumps are located between the first chip and the second chip; one of the fourth micro-bumps is bonded to one of the fourth under-bump metal pads and one of the third micro-bumps.

11. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The chip packaging structure further comprises a packaging substrate; the packaging substrate is located on a side of the interconnection substrate away from the chip stacking structure; The chip packaging structure further includes a plurality of fifth micro bumps, wherein the fifth micro bumps are located between the packaging substrate and the interconnection substrate; the fifth micro bumps are used to electrically connect the packaging substrate and the interconnection substrate.

12. The chip packaging structure according to claim 11, characterized in that: The analog circuit includes a plurality of second inductors, and the second inductors are integrated in the packaging substrate.

13. The chip packaging structure according to claim 6 or 8, characterized in that: The chip packaging structure further includes a plastic encapsulation layer, which wraps the chip stacking structure and the periphery of the third chip and is connected to the interconnection substrate.

14. The chip packaging structure according to claim 13, characterized in that: The chip packaging structure further includes: A packaging substrate, the packaging substrate being located at a side of the interconnection substrate away from the chip stacking structure; A thermal interface material layer, covering the chip stacking structure and a surface of the third chip on a side away from the interconnection substrate; A heat dissipation cover, covering the thermal interface material layer and connected to the packaging substrate; The base glue is arranged between the interconnection substrate and the packaging substrate.

15. An electronic device, characterized in that: It comprises a printed circuit board and a chip packaging structure as claimed in any one of claims 1 to 14; the chip packaging structure is electrically connected to the printed circuit board.

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