Low cost wafer level package and silicon

Abstract

The present disclosure relates to low-cost wafer-level packages and silicon. Described herein is a method of forming a wafer-level package from a wafer. The method includes adhesively attaching a front side of a first integrated circuit within the wafer to a back side of a second integrated circuit such that pads on the front side of the first integrated circuit and pads on a front side of the second integrated circuit are exposed. The method also includes forming a laser direct structuring (LDS) activatable layer on the front sides of the first and second integrated circuits and on an edge of the second integrated circuit, and forming a desired pattern of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired pattern of structured areas to form conductive areas within the LDS activatable layer.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 203,539, filed July 27, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to techniques for forming wafer-level packages, and more particularly to forming wafer-level packages having a redistribution layer formed using laser direct structure, so as to enable the formation of a compact package containing multiple interconnect integrated circuit dies. Background Technology

[0004] Integrated circuit dies are packaged to protect them from the operating environment and to provide an electrical interface between the die and the electronic devices that utilize it. Traditionally, die packaging technology differs from semiconductor manufacturing technology used in wafer-level processing. However, in recent years, wafer-level processing technologies such as wafer-level chip-scale packaging (WLCSP) have begun to be used to build die packages.

[0005] Figure 1 It is a cross-sectional view of a known package 10 including a first integrated circuit die 9 connected to a second integrated circuit die 8 via a corresponding redistribution layer formed on the first integrated circuit die 9.

[0006] More specifically, the first integrated circuit die 9 has a rear side shown as exposed and a front side on which pads 12a and 12b are formed, the pads 12a and 12b providing connections to internal circuitry within the first integrated circuit die 9. A passivation layer 13 is disposed on the front side of the first integrated circuit die 9, and a solder mask layer 15 is formed on the passivation layer 13. A first redistribution layer formed within the passivation layer 13 and the solder mask layer 15 includes interconnects 14a and 14d respectively connected to the pads 12a and 12b, and interconnects 14b, 14c, 27a, and 27b connected to pads (not shown) on the front side of the first integrated circuit die 9. Solder balls 16a-16d are connected to interconnects 14a-14d respectively.

[0007] The second integrated circuit die 8 has a rear side enclosed by an encapsulation layer 23 and a front side on which pads 19a and 19b are formed, the pads 19a and 19b providing connections to internal circuitry within the second integrated circuit die 8. A passivation layer 20 is disposed on the front side of the second integrated circuit die 8, and a solder resist layer 22 is formed on the passivation layer 20. A second redistribution layer formed within the passivation layer 20 and the solder resist layer 22 includes interconnects 21a and 21b respectively connected to the pads 19a and 19b. Solder balls 17a and 17b connect interconnects 27a and 27b of the first integrated circuit die 9 to interconnects 21a and 21b of the second integrated circuit die 8. The encapsulation layer 23 encapsulates the edge sides and front surface of the second integrated circuit die 8 and seals them with the solder resist 15 of the first integrated circuit die 9.

[0008] According to such Figure 1 Existing wafer-level processing techniques have several limitations in forming wafer-level packages. For example, the cost of forming high-density, large-size, and high-pin-count wafer-level packages may be higher than desired, especially when fan-out arrangements are used. Furthermore, wafer-level packages utilizing multiple integrated circuit dies may be difficult to form, and using solder balls to connect different dies may consume an undesirable amount of space.

[0009] Therefore, further development is needed. Summary of the Invention

[0010] This document discloses a method for forming a wafer-level package from a wafer, comprising: adhesively attaching the back side of a second integrated circuit to the front side of a wafer comprising a plurality of first integrated circuits, such that pads on the front side of the first integrated circuits and pads on the front side of the second integrated circuits are exposed; forming a laser direct structured (LDS) activatable layer on the front sides of the first and second integrated circuits and on the edge of the second integrated circuit; activating a portion of the LDS activatable layer to form a desired pattern of structured regions within the LDS activatable layer, some of the desired pattern of the structured regions within the LDS activatable layer extending from pads on the front side of the second integrated circuit to pads on the front side of the first integrated circuit; metallizing the desired pattern of the structured regions to form conductive regions within the LDS activatable layer, some of the formed conductive regions electrically connecting pads of the first integrated circuits to pads of the second integrated circuits; and dicing the wafer to form a plurality of wafer-level packages, each wafer-level package comprising one of the first integrated circuits and one of the second integrated circuits.

[0011] Solder balls can be attached to desired conductive regions within the formed conductive regions, such that some of the solder balls attached to the front side of the first integrated circuit are electrically connected to pads on the front side of the second integrated circuit.

[0012] A coating can be formed on the back side of the first integrated circuit before it is cut into individual pieces.

[0013] A solder resist layer can be formed on the LDS activatable layer.

[0014] Passive components can be attached to desired conductive regions formed in conductive regions on a first integrated circuit, which are electrically connected to desired pads on the front side of a second integrated circuit, and a molding layer can be formed on the passive components.

[0015] A molding layer can be formed on the first integrated circuit, a pad can be formed on the bottom side of the molding layer, and a via can be formed in the molding layer to electrically connect a desired conductive region formed in a conductive region on the first integrated circuit to a pad formed on the bottom side of the molding layer, and the conductive region is electrically connected to a pad on the front side of the first integrated circuit.

[0016] A molding layer can be formed on the first integrated circuit, pads can be formed on the bottom side of the molding layer, and interconnects can be formed to connect the pads on the bottom side of the molding layer to desired pads on the front side of the second integrated circuit.

[0017] The chip can be attached to a desired conductive region in a conductive region formed on a first integrated circuit using solder balls, such that the chip's pads face the desired conductive region in the conductive region, and a molding layer is formed on the chip.

[0018] This document also discloses a wafer-level package comprising: a first integrated circuit die having a plurality of pads on its front side; a second integrated circuit die having a plurality of pads on its front side, wherein an adhesive layer adheres the rear side of the second integrated circuit die to the front side of the first integrated circuit die; a resin layer surrounding the edge side of the second integrated circuit die and the front side of the second integrated circuit die, and surrounding the front side of the first integrated circuit die, wherein the resin layer comprises an activatable catalyst material; a solder resist layer having its rear side in contact with the front surface of the resin layer; and a redistribution layer. The redistribution layer comprises: a first activated and metallized portion of the resin layer adjacent to the plurality of pads on the front side of the second integrated circuit die; a second activated and metallized portion of the resin layer adjacent to the plurality of pads on the front side of the first integrated circuit die; and a third activated and metallized portion of the resin layer extending downward from a given portion of the first activated and metallized portion of the resin layer along the edge side of the second integrated circuit die and across a portion of the resin layer on the front side of the first integrated circuit die, thereby providing an electrical connection between a given pad among the plurality of pads on the front side of the second integrated circuit die and a location on the resin layer on the front side of the first integrated circuit die.

[0019] The fourth activation and metallization portion of the resin layer can electrically connect certain portions of the first activation and metallization portion of the resin layer to certain portions of the second activation and metallization portion of the resin layer, thereby electrically connecting certain pads on the front side of the second integrated circuit die to certain pads on the front side of the first integrated circuit die.

[0020] The fourth activation and metallization portion of the resin layer may be located on the front side of the first integrated circuit die. The fifth activation and metallization portion of the resin layer may electrically connect one of the first activation and metallization portions to the fourth activation and metallization portion of the resin layer.

[0021] Passive components can be electrically connected to the fourth activated and metallized portion of the resin layer.

[0022] Molded layers can encapsulate passive components.

[0023] The molding layer may encapsulate a portion of the first integrated circuit die and one of the second activated and metallized portions of the resin layer. Pads may be formed on the molding layer. Vias may extend from the pads formed on the molding layer through the molding layer to contact one of the second activated and metallized portions of the resin layer, thereby electrically connecting the pads formed on the molding layer to one of the second activated and metallized portions of the resin layer.

[0024] The chip can be connected to one of the third activated and metallized portions of the resin layer on the front side of the first integrated circuit die.

[0025] The molding layer can encapsulate the chip. Attached Figure Description

[0026] Figure 1 It is a cross-sectional view of a wafer-level package formed using existing technology.

[0027] Figures 2A to 2B This is a cross-sectional view of the first wafer-level package formed using the technology described herein.

[0028] Figures 3 to 11 Manufacturing process is shown Figure 2A The series of steps involved in the first chip-level package.

[0029] Figure 12 This is a cross-sectional view of a second wafer-level package formed using the techniques described herein.

[0030] Figures 13 to 19 Manufacturing process is shown Figure 12 The series of steps involved in the second wafer-level package.

[0031] Figure 20 This is a cross-sectional view of a third wafer-level package formed using the technology described herein. Detailed Implementation

[0032] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those described in detail above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or implied herein.

[0033] In the following disclosure, the reference to "connection" of a component may indicate which components are electrically connected, and may be directly electrically connected as well as physically connected.

[0034] First refer to Figure 2A The first wafer-level package 10' is now described. The first wafer-level package 10' includes: a first integrated circuit die 11 having pads 12a and 12b on its front side and a coating 31 on its rear side; and a second integrated circuit die 18 having pads 19a-19b on its front side and its rear side facing the front side of the first integrated circuit die 11. An adhesive layer 30 attaches the rear side of the second integrated circuit die 18 to the front side of the first integrated circuit die 11. Therefore, note that the pads 12a and 12b of the first integrated circuit die 11 do not face the pads 19a-19b of the second integrated circuit die 18.

[0035] A resin layer 13' is disposed on the front side and across the front side of the first integrated circuit die 11, on and above the edge side of the second integrated circuit die 18, and on the front side and across the front side of the second integrated circuit die 18. A solder mask layer 15' is disposed on and across the resin layer 13'.

[0036] A redistribution layer (RDL) is formed within and on resin layer 13' and is covered by solder mask layer 15'. The RDL includes interconnects 41a and 41d connected to pads 12a and 12b, respectively, and interconnects 41e and 41f connected to pads 19c and 19d, respectively. The RDL also includes interconnects 41b and 41c that extend from pads 19a and 19b across portions of resin layer 13' on the front side of the second die 18, downward along portions of resin layer 13' on the edge side of the second die 18, and across portions of resin layer 13' on the front side of the integrated circuit die 11. In some embodiments, interconnects 41b or 41c can connect pads 19a or 19c to corresponding pads on the first integrated circuit die 11, for example... Figure 2B As shown, interconnect 41b connects pad 19a to pad 12c on the first integrated circuit die 11.

[0037] Solder balls 16a and 16d are connected to interconnects 41a and 41d, respectively. Solder balls 16b and 16c are connected to the portions of interconnects 41b and 41c that extend across the resin layer 13' on the front side of the first integrated circuit die 11, respectively. Solder balls 16e and 16f are connected to interconnects 41e and 41f, respectively.

[0038] It is important to note that interconnects 41a-41f are not formed using conventional techniques. As will be explained in detail below, interconnects 41a-41f are formed by activating desired regions of resin layer 13' (and drilling appropriate regions before activating the desired regions and the walls of holes formed via drilling) and then electroplating the activated regions, the resin layer 13' containing an activatable catalyst.

[0039] Now for reference Figures 3 to 11 The following series of figures are used to describe the formation of the first wafer-level package 10'. First refer to... Figure 3 Each die 5 has an integrated circuit die location 7 formed therein; two such integrated circuit die locations 7 are shown, but it should be understood that any number of such integrated circuit die locations 7 may exist. Each integrated circuit die location 7 has pads 12a and 12b formed on its front side.

[0040] like Figure 4 As shown, an adhesive layer 30 is formed on the front side of each integrated circuit die location 7, and then the rear side of the integrated circuit 18 is attached to the adhesive layer 30, such that the rear side of the integrated circuit 18 is attached to the front side of the integrated circuit die location 7. The integrated circuit 18 has pads 19a-19d formed on its front side.

[0041] like Figure 5 As shown, the conformal deposit, for example by spraying, is made of laser direct structuring (LDS) compatible resin 13' on the combined structure of integrated circuit die location 7 and integrated circuit die 18'. Specifically, LDS compatible resin 13' is sprayed onto the exposed portions of the front side of integrated circuit die location 7 and integrated circuit die 18, and is also sprayed onto the side surface of integrated circuit 18. The LDS compatible resin is infused or embedded with laser-activated catalysts or particles that are activated or exposed to form structured regions when subjected to certain laser radiation (such as infrared (IR) laser radiation). These structured regions can then be converted into conductive regions via metallization.

[0042] For example, the LDS resin layer 13' may have embedded particles such as copper chromium oxide spinel, copper sulfate, copper hydroxide phosphate, or copper rhodanoate. The molded layer 13' is then cured.

[0043] Next, as Figure 6As shown, through-cavities 71a-71b and 72a-72d are formed through the LDS resin layer 13' by laser drilling, and the desired pattern of structured regions is formed in the LDS resin layer 13' by activating or exposing the catalyst in the walls of the through-cavities 71a-71b and 72a-72d using a laser.

[0044] The structured region refers to the area in the LDS resin layer 13' where the catalyst is activated or exposed due to the application of a laser to the relevant portion of the LDS resin layer 13'. As described below, the structured region can be metallized to form a conductive region. For example, laser activation can be applied to the walls of the cavities 71a-71b and 72a-72d to construct those walls.

[0045] After that, as Figure 7 As shown, a metallization process is performed to metallize vias 71a-71b and 72a-72d, forming traces connected to them and extending across the LDS resin layer 13', thereby forming interconnects 41a-41f. This metallization process may include electroless copper deposition, wherein a suitable wet chemical bath reacts with exposed chromium particles within the LDS resin layer 13' to produce a thin (e.g., 5 μm thick) copper pattern on a pattern of structured regions on the LDS resin layer 13'. This thin copper pattern can be thickened by electrodeposition to achieve the desired thickness (e.g., 10 μm) for the proper formation of interconnects 41a-41f.

[0046] Next, as Figure 8 As shown, a solder resist layer 15 is formed on the LDS resin layer 13' and the interconnects 41a-41f. Then, as... Figure 9 As shown, solder balls 16a-16d are connected to interconnects 41a-41d, and solder balls 16e-16f are connected to interconnects 41e-41f. Then, as... Figure 10 As shown, coating 31 is applied to the rear side of integrated circuit die location 7, and then, as... Figure 11 As shown, the wafer is sliced ​​into integrated circuit dies 11 to form wafer-level packages 10a' and 10b'.

[0047] First refer to Figure 12 The second wafer-level package 10 is now described. The second wafer-level package 10 includes: a first integrated circuit die 11 having pads 12a and 12b on its front side and a coating 31 on its rear side; and a second integrated circuit die 18 having pads 19a-19b on its front side and its rear side facing the front side of the first integrated circuit die 11. An adhesive layer 30 attaches the rear side of the second integrated circuit die 18 to the front side of the first integrated circuit die 11. Therefore, note that the pads 12a and 12b of the first integrated circuit die 11 do not face the pads 19a-19b of the second integrated circuit die 18.

[0048] A resin layer 13' is disposed on the front side and across the front side of the front integrated circuit die 11, on and above the edge side of the second integrated circuit die 18, and on and across the front side of the second integrated circuit die 18. A solder mask layer 15' is disposed on and across the resin layer 13'.

[0049] A redistribution layer (RDL) is formed within and on the resin layer 13' and is covered by a solder mask layer 15'. The RDL includes interconnects 41a and 41d connected to pads 12a and 12b, respectively, and interconnects 41e and 41f connected to pads 19c and 19d, respectively. The RDL includes interconnects 41b and 41c that extend downward from pads 19a and 19b across a portion of the resin layer 13' on the front side of the second die 18, down along a portion of the resin layer 13' on the edge side of the second die 18, and across a portion of the resin layer 13' on the front side of the integrated circuit die 11.

[0050] Solder balls 35a and 35b are connected to interconnects 41c and 41d and to pads on chip 40, the front side of chip 40 facing the front side of first integrated circuit die 11. Molding layer 44 encapsulates chip 40 and extends along one side of second integrated circuit die 18 and across a portion of the front surface of first integrated circuit die 15.

[0051] Passive components 45, such as capacitors, are connected to interconnects 41b. Vias 46 are connected to interconnects 41a. A molding layer 44 encapsulates the passive components 45 and extends along the other side of the second integrated circuit die 18 and across another portion of the front surface of the first integrated circuit die 11.

[0052] Note that the solder resist 14 also extends across the molding layer 44 and sandwiches the molding layer 44 on both sides. Pad 33a is located in the solder resist 14 at the illustrated position opposite to interconnect 41a and is connected to via 46, and solder ball 16a is connected to pad 33a. Pad and interconnect 33b extend in the solder resist 14 from interconnect 41e to the illustrated position opposite to passive component 45 and interconnect 41b, and solder ball 16b is connected to pad 33b. Pad and interconnect 33c extend in the solder resist 14 from interconnect 41f to the illustrated position opposite to chip 40 and interconnect 41c, and solder ball 16c is connected to pad 33c. Pad 33d is in the solder resist 14 opposite to interconnect 41d, and solder ball 16d is connected to pad 33d.

[0053] It is important to note that interconnects 41a-41f are not formed by drilling and filling. Interconnects 41a-41f are formed by activating the desired areas of the resin layer 13' (and drilling appropriate areas before activating the desired areas and the walls of the holes formed via drilling) and then electroplating the activated areas, the resin layer 13' containing an activatable catalyst. It should also be noted that the pads 33a, pads and interconnects 33b, pads and interconnects 33c, and pads 33d within the solder resist 15, as well as the via 46, are formed using conventional techniques rather than LDS technology.

[0054] The formation of the second wafer-level package 10” begins in the same manner as the first wafer-level package 10', as shown in the reference above. Figures 3 to 8 As stated above. Now refer to another source. Figures 13 to 19 The remaining portion of the formation of the second wafer-level package 10” is described below. After the solder resist layer 16 is formed on the LDS resin layer 13’ and interconnects 41a-41f, the passive component 45 is attached to the interconnect 41b, as follows. Figure 13 As shown. Additionally, chip 40 is connected to interconnects 41c and 41d at this time.

[0055] Next, as Figure 14 As shown, a molding layer 44 is deposited on the solder resist 15, the passive component 45, and the chip 40. Then, as... Figure 15 As shown, vias 46 are formed in the molding layer 44 using conventional techniques. These vias 46 extend from the front of the molding layer 44 to reach the interconnect 41a.

[0056] The pad 33a is formed in the solder resist 14 at the illustrated position opposite to the interconnect 41a and is connected to the via 46, and the solder ball 16a is connected to the pad 33a using conventional techniques.

[0057] Pads and interconnects 33b are formed in solder resist 14 extending from interconnect 41e to the illustrated location opposite passive component 45 and interconnect 41b, and solder balls 16b are connected to pads 33b using conventional techniques. Pads and interconnects 33c are formed in solder resist 14 extending from interconnect 41f to the illustrated location opposite chip 40 and interconnect 41c, and solder balls 16c are connected to pads 33c using conventional techniques. Pad 33d is formed in solder resist 14 opposite interconnect 41d, and solder balls 16d are also connected to pads 33d using conventional techniques.

[0058] Then, as Figure 16 As shown, an additional portion of the solder resist 15 is formed on the molding layer 44, and holes 76a-76d are drilled in the molding layer 44. Thereafter, as... Figure 17 As shown, solder balls 16a-16d are connected to pads and interconnects 33a-33d, and as... Figure 18As shown, coating 31 is applied to the rear side of integrated circuit die location 7, and then as... Figure 19 As shown, the integrated circuit is cut into integrated circuit dies 10a and 10b.

[0059] It should be understood that the embodiments given above are examples of possible possibilities when using LDS technology. Figure 20 Another example is shown in the package 10”, which is similar to Figure 2A The package 10' is the same as the one in the package, except that another solder mask 51 is deposited on the back side of the integrated circuit die location 7, and pads 52a-52d are formed thereon. Connectors 53a and 53b extend through the integrated circuit die location 7 to provide interconnection between components in the solder mask layers 51 and 13.

[0060] Although this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure. Therefore, the scope of this disclosure is limited only by the appended claims.

Claims

1. A method for forming a wafer-level package from a wafer, comprising: The rear side of the second integrated circuit is adhesively attached to the front side of the wafer comprising a plurality of first integrated circuits, such that pads on the front side of the first integrated circuits and pads on the front side of the second integrated circuits are exposed. A laser-direct-structured LDS activatable layer is formed on the front side of the first integrated circuit, the front side of the second integrated circuit, and the edge of the second integrated circuit. A portion of the LDS activatable layer is activated to form a desired pattern of structured regions within the LDS activatable layer, some of the desired patterns of the structured regions within the LDS activatable layer extending from the pads on the front side of the second integrated circuit to the pads on the front side of the first integrated circuit; Metallize the desired pattern of the structured region to form conductive regions within the LDS activatable layer, some of which electrically connect the pads of the first integrated circuit to the pads of the second integrated circuit; and The wafer is diced to form multiple wafer-level packages, each wafer-level package containing one integrated circuit from the first integrated circuit and one integrated circuit from the second integrated circuit.

2. The method of claim 1, further comprising attaching solder balls to a desired conductive region within the formed conductive region, such that some of the solder balls attached to the formed conductive region on the front side of the first integrated circuit are electrically connected to the pads on the front side of the second integrated circuit.

3. The method of claim 1, further comprising forming a coating on the back side of the first integrated circuit prior to cutting the order.

4. The method according to claim 1, further comprising forming a solder resist layer on the LDS activatable layer.

5. The method according to claim 1, further comprising: A passive component is attached to a desired conductive region formed on the first integrated circuit, the conductive region being electrically connected to a desired pad on the front side of the second integrated circuit, and a molding layer is formed on the passive component.

6. The method of claim 1, further comprising forming a molding layer on the first integrated circuit, forming pads on the bottom side of the molding layer, and forming vias in the molding layer, the vias electrically connecting a desired conductive region formed on the conductive region of the first integrated circuit to the pads formed on the bottom side of the molding layer, the conductive region being electrically connected to pads on the front side of the first integrated circuit.

7. The method of claim 1, further comprising forming a molding layer on the first integrated circuit, forming pads on the bottom side of the molding layer, and forming interconnects that connect the pads on the bottom side of the molding layer to desired pads on the front side of the second integrated circuit.

8. The method of claim 1, further comprising attaching a chip to a desired conductive region in the conductive region formed on the first integrated circuit using solder balls, such that the pads of the chip face the desired conductive region in the conductive region, and forming a molding layer on the chip.

9. A wafer-level package, comprising: A first integrated circuit die, wherein the front side of the first integrated circuit die has a plurality of pads; A second integrated circuit die has a plurality of pads on its front side, wherein an adhesive layer adheres the rear side of the second integrated circuit die to the front side of the first integrated circuit die; A resin layer surrounds the edge side and the front side of the second integrated circuit die, and surrounds the front side of the first integrated circuit die, wherein the resin layer includes an activatable catalyst material; A solder resist layer, wherein the rear surface of the solder resist layer is in contact with the front surface of the resin layer; as well as The redistribution layer includes: The first activated and metallized portion of the resin layer is adjacent to the plurality of pads on the front side of the second integrated circuit die; The second activated and metallized portion of the resin layer is adjacent to the plurality of pads on the front side of the first integrated circuit die; and The third activated and metallized portion of the resin layer extends from a given portion of the first activated and metallized portion of the resin layer down along the edge side of the second integrated circuit die and across a portion of the resin layer on the front side of the first integrated circuit die, thereby providing an electrical connection between a given pad among the plurality of pads on the front side of the second integrated circuit die and a location on the resin layer on the front side of the first integrated circuit die.

10. The wafer-level package according to claim 9, comprising: The fourth activation and metallization portion of the resin layer electrically connects certain portions of the first activation and metallization portion of the resin layer to certain portions of the second activation and metallization portion of the resin layer, thereby electrically connecting certain pads on the front side of the second integrated circuit die to certain pads on the front side of the first integrated circuit die.

11. The wafer-level package according to claim 9, further comprising: The fourth activation and metallization portion of the resin layer is on the front side of the first integrated circuit die; The fifth activation and metallization portion of the resin layer electrically connects one of the first activation and metallization portions to the fourth activation and metallization portion of the resin layer; as well as A passive component, electrically connected to the fourth activated and metallized portion of the resin layer.

12. The wafer-level package of claim 11, further comprising a molding layer encapsulating the passive component.

13. The wafer-level package according to claim 9, further comprising: A molding layer, a portion encapsulating the first integrated circuit die, and one of the second activated and metallized portions of the resin layer; Pads are formed on the molding layer; as well as A via extends from the pad formed on the molding layer through the molding layer to contact one of the second activated and metallized portions of the resin layer, thereby electrically connecting the pad formed on the molding layer to one of the second activated and metallized portions of the resin layer.

14. The wafer-level package of claim 9, further comprising a chip connected to one of the third activated and metallized portions of the resin layer on the front side of the first integrated circuit die.

15. The wafer-level package of claim 14, further comprising a molding layer encapsulating the chip.

16. A method for forming a wafer-level package from a wafer, comprising: The back side of the second integrated circuit is adhered to the front side of a wafer comprising a plurality of first integrated circuits, such that the pads on the front side of the first integrated circuits and the pads on the front side of the second integrated circuit are exposed. A laser-direct-structured LDS activatable layer is formed on the front side of the first integrated circuit, the front side of the second integrated circuit, and the edge of the second integrated circuit. A desired pattern of structured regions is formed within the LDS activatable layer, some of which extend from pads on the front side of the second integrated circuit to pads on the front side of the first integrated circuit; and The desired pattern of the structured region is metallized to form a conductive region within the LDS activatable layer, the conductive region electrically connecting the pads of the first integrated circuit to the pads of the second integrated circuit.

17. The method of claim 16, further comprising attaching solder balls to a desired conductive region in the formed conductive region, such that some of the solder balls attached to the formed conductive region on the front side of the first integrated circuit are electrically connected to the pads on the front side of the second integrated circuit.

18. The method of claim 16, further comprising attaching a passive element to a desired conductive region formed on the conductive region of the first integrated circuit, the conductive region being electrically connected to a desired pad on the front side of the second integrated circuit, and forming a molding layer on the passive element.

19. The method of claim 16, further comprising forming a molding layer on the first integrated circuit, forming pads on the bottom side of the molding layer, and forming vias in the molding layer, the vias electrically connecting a desired conductive region formed on the conductive region of the first integrated circuit to the pads formed on the bottom side of the molding layer, the conductive region being electrically connected to pads on the front side of the first integrated circuit.

20. The method of claim 16, further comprising attaching a chip to a desired conductive region in the conductive region formed on the first integrated circuit using solder balls, such that the pads of the chip face the desired conductive region in those conductive regions, and forming a molding layer on the chip.

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