ATPG Test Methodology for Latch-Based Memories to Reduce Area

Abstract

Embodiments of the present disclosure relate to an area-reduced ATPG test method for latch-based memories. Logic circuits and techniques are disclosed herein for operating the hardware to enable building a first-in-first-out (FIFO) buffer from latches while simultaneously allowing stuck-at-1 fault testing of the enable pins of those latches and testing of the data path at various points through the FIFO buffer.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit devices, and in particular to circuits and techniques that facilitate the operation of first-in-first-out (FIFO) buffers constructed from latches in a test mode, thereby allowing complete testing of the write / read paths of these FIFO buffers. Background Art

[0002] The complexity of integrated circuit devices, such as systems on a chip (SoCs) and microcontrollers, continues to increase, and new advanced features are regularly introduced. As a result, the area of ​​such devices occupied by digital logic is increasing, which is undesirable because it increases costs. Consequently, attempts have been made to reduce this area consumption.

[0003] One area of ​​focus is reducing the area of ​​data first-in, first-out (FIFO) buffers used in SoCs and microcontrollers. FIFO buffers are typically formed from flip-flops. Some area reduction efforts have focused on replacing the flip-flops of data FIFO buffers with latches, as this can reduce the physical area consumed by such FIFO buffers by 45% to 50%. However, this raises questions about the ability to fully test the FIFO buffers.

[0004] The FIFO buffer 4 formed by the latch and its associated logic circuits are Figure 1 1. Here, data to be written to the FIFO buffer 4 is first written to the write data register 2 and then passed to the FIFO buffer 4 by means of and through the write logic circuit 3 as appropriate to perform the writing. Data to be read from the FIFO buffer 4 is passed to the read data register 6 by means of and through the read logic circuit 5 as appropriate. Note that the write data register 2 and the read data register 6 are part of a scan chain used in test mode. Test logic 7 operates on the FIFO buffer 4, the write data register 2 portion of the scan chain, the write logic circuit 3, the FIFO buffer 4, the read logic circuit 5, and the read data register 6 portion of the scan chain to perform testing on the FIFO buffer 4, for example using known techniques such as automatic test pattern generation (ATPG) testing and logic built-in self-test (LBIST) testing.

[0005] In order to test the FIFO buffer 4 using ATPG testing and LBIST testing, the latches within the FIFO buffer 4 are made transparent by applying asserted enable signals to their enable pins by the test logic 7 at appropriate times during the test process, thereby enabling the correct transfer of data from the write data register 2 through the FIFO buffer 4 to the read data register 6, and enabling testing for stuck-at-0 faults on the latch enable pins of the FIFO buffer 4. However, this testing capability is more limited than expected, as only the entire data path from the write data register 2 through the FIFO buffer 4 to the read data register 6 is tested as a whole. This means that the data path from the write data register 2 to the FIFO buffer 4 and the data path from the FIFO buffer 4 to the read data register 6 cannot be tested separately. Furthermore, the FIFO buffer 4 cannot be tested for stuck-at-1 faults on its latch enable pins.

[0006] Therefore, there is a need to further develop the field of FIFO buffers that utilize latches as their storage elements to be able to perform a wider range of tests on these FIFO buffers. Summary of the Invention

[0007] Disclosed herein is a system operable in a functional mode and a test mode, the system comprising: a write data register clocked by a clock signal and configured to store data to be written; a read data register clocked by a clock signal and configured to store data to be read; a first-in-first-out (FIFO) buffer composed of a latch group, the latch group being enabled by an enable signal, and the latch group being arranged to store a plurality of words, wherein a word can be selected at a time by a write address signal to write data from the write data register into the latch group, and a word can be selected at a time by a read address signal to read data stored in the latch group into the read data register; A control circuit device configured to receive a write request signal and a write address signal, and generate a write enable signal; wherein the control circuit device is further configured to receive a read request signal and a read address signal, and generate a read enable signal; and glue logic configured to generate an internal write enable signal from at least the write enable signal and to generate an internal read enable signal from at least the read enable signal; wherein when the system is in a functional mode, a latch group of the FIFO buffer is enabled by the write enable signal and the read enable signal; and wherein when the system is in a test mode, the latch group of the FIFO buffer is enabled by the internal write enable signal and the internal read enable signal.

[0008] When the test mode is an automatic test pattern generation (ATPG) test mode, the control circuit device and the glue logic can cooperate to operate the system in the test mode by setting the scan control signal to logic 1 and the transition mode signal to logic 0 to start a fixed test; and performing a test setup phase to initialize the FIFO buffer for the ATPG test mode. The test setup phase can be performed by setting the scan reset signal to logic 0 to put the write data register and the read data register in a reset state; using an external enable signal to enable the latch group of the FIFO buffer to make the latch group transparent; removing the external enable signal to latch the latch group; and setting the scan reset signal to logic 1 to release the write data register and the read data register from the reset state while not providing a clock signal to the write data register, thereby completing the test setup phase.

[0009] When the test mode is an ATPG test mode, the control circuit device and the glue logic may also cooperate to operate the system in the test mode by: performing a shift phase by shifting the ATPG test pattern to the FIFO buffer, so that after the last shift, the write data register holds the value of the last bit to be shifted; wherein when the FIFO buffer experiences a stuck-on-1 fault at the enable input of one or more latch groups, the FIFO buffer contains the value of the last bit to be shifted, but when the FIFO buffer does not experience a stuck-on-1 fault at the enable input of the one or more latch groups, the FIFO buffer does not contain the value of the last bit to be shifted at this time; and performing a capture phase, wherein when the FIFO buffer experiences a stuck-on-1 fault at the enable input of the one or more latch groups, the read data register holds the value of the last bit to be shifted, but when the FIFO buffer does not experience a stuck-on-1 fault at the enable input of the one or more latch groups, the read data register holds a logic 0.

[0010] When the test mode is a logic built-in self-test (LBIST) mode, the control circuit device and the glue logic may cooperate to operate the system in the test mode by: using an enable signal to enable the latch groups of the FIFO buffer, thereby making the latch groups transparent; generating an LBIST pattern and passing the LBIST pattern through the FIFO buffer; and after a given number of bits of the LBIST pattern have passed through the FIFO buffer, deasserting the enable signal so that when the FIFO buffer experiences a stuck-one fault at the enable input of one or more latch groups, the FIFO buffer continues to pass through the LBIST pattern, but when the FIFO buffer does not experience a stuck-one fault at the enable input of the one or more latch groups, the FIFO buffer stops passing through the LBIST mode.

[0011] The glue logic may include a first glue logic circuit, the first glue logic circuit including: a first flip-flop having a data input for receiving a scan enable signal, an output, and a clock input for receiving a clock signal; a second flip-flop having a data input for receiving the output of the first flip-flop, an output for generating an internal scan enable signal, and a clock input for receiving the clock signal; and an AND gate having a first inverting input for receiving the scan enable signal, a second inverting input for receiving the output of the first flip-flop, and a third non-inverting input for receiving the internal scan enable signal, wherein the AND gate generates a gated scan enable signal at its output.

[0012] The glue logic may also include a second glue logic circuit, the second glue logic circuit including: an AND gate having a first input for receiving a write request signal and a second input for receiving a gated scan enable signal, and having an output; a first multiplexer having a first data input for receiving a pad enable signal, a second data input for receiving the output of the AND gate, a selection input for receiving a conversion mode signal, and an output; and a second multiplexer having a first data input for receiving a write request signal, a second data input for receiving the output of the first multiplexer, a selection input for receiving a scan control signal, and an output for generating an internal write enable signal.

[0013] The glue logic may also include a third glue logic circuit, the third glue logic circuit including: an AND gate having a first non-inverting input for receiving a read valid signal, a second inverting input for receiving an internal scan enable signal, a third inverting input for receiving a scan enable signal, and an output; and a multiplexer having a first data input for receiving a read valid signal, a second data input for receiving the output of the AND gate of the third glue logic circuit, a selection input for receiving a conversion mode signal, and an output for generating an internal read valid signal.

[0014] The glue logic may also include a fourth glue logic circuit, the fourth glue logic circuit including: an AND gate having a first non-inverting input for receiving a read enable signal, a second inverting input for receiving an internal scan enable signal, a third inverting input for receiving a scan enable signal, and an output; and a multiplexer having a first data input for receiving a read enable signal, a second data input for receiving the output of the AND gate of the fourth glue logic circuit, a selection input for receiving a conversion mode signal, and an output for generating an internal read enable signal.

[0015] When the control circuit device and the glue logic cooperate to operate the system in the test mode when the test mode is an automatic test pattern generation (ATPG) mode in which a clock signal is externally provided, the circuit used within the glue logic may include a fifth glue logic circuit, the fifth glue logic circuit including: a first AND gate having a first input receiving a write request signal, a second input receiving a pad enable signal, and an output; a second AND gate having a first non-inverting input receiving a conversion mode signal, a second inverting input receiving a scan enable signal, and an output; a first multiplexer having a first data input receiving the pad enable signal, a second data input receiving the output of the first AND gate, a select input receiving the output of the second AND gate, and an output; and a second multiplexer having a first data input receiving the write request signal, a second data input receiving the output of the first multiplexer, a select input receiving the scan control signal, and an output generating an internal write enable signal.

[0016] When the control circuit device and the glue logic cooperate to operate the system in the test mode in an ATPG mode in which the test mode is an externally provided clock signal, the circuit used within the glue logic may further include a sixth logic circuit, the sixth logic circuit including: a first AND gate having a first non-inverting input receiving a read valid signal, a second inverting input receiving a pad enable signal, and an output; a second AND gate having a first non-inverting input receiving a conversion mode signal, a second inverting input receiving a scan enable signal, and an output; and a multiplexer having a first data input receiving the read valid signal, a second data input receiving the output from the first AND gate, a select input receiving the output of the second AND gate, and an output generating an internal read valid signal.

[0017] When the control circuit device and the glue logic cooperate to operate the system in the test mode when the test mode is an ATPG mode in which a clock signal is externally provided, the circuit used within the glue logic may further include a seventh logic circuit, the seventh logic circuit including: a first AND gate having a first non-inverting input receiving a read enable signal, a second inverting input receiving a pad enable signal, and an output; a second AND gate having a first non-inverting input receiving a conversion mode signal, a second inverting input receiving a scan enable signal, and an output; and a multiplexer having a first data input receiving the read enable signal, a second data input receiving an output from the first AND gate of the seventh logic circuit, a select input receiving an output of the second AND gate of the seventh logic circuit, and an output generating an internal read enable signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a high-level block diagram of a prior art FIFO buffer, circuitry associated with its operation, and circuitry associated with its testing.

[0019] Figure 2 is a high-level block diagram of a FIFO buffer, circuitry associated with its operation, and circuitry associated with its testing as described herein.

[0020] Figure 3 yes Figure 2 A more detailed block diagram of a FIFO buffer and the circuitry associated with its operation.

[0021] Figure 4 It shows Figure 3 A timing diagram of the states of the various signals during FIFO buffer operation in non-test mode.

[0022] Figures 5A-5D is a schematic block diagram of a first embodiment of a logic circuit for generating Figure 3 A control signal for the operation of the FIFO buffer during operation in non-test and test modes.

[0023] Figure 6 is shown during the FIFO buffer operation to perform conversion mode testing, Figures 5A-5D A timing diagram showing the states of various signals, where the clock signal used during the test is provided by a phase-locked loop.

[0024] Figures 7A-7C is a schematic block diagram of a second embodiment of a logic circuit for generating Figure 3 A control signal for the operation of the FIFO buffer during operation in non-test and test modes.

[0025] Figure 8 During the FIFO buffer operation to perform the conversion mode test, Figures 7A-7C A timing diagram showing the states of various signals, where the clock signal used during testing is provided by an external source at the pad. DETAILED DESCRIPTION

[0026] The following disclosure enables one skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those described in detail above without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0027] Figure 2Shown is a FIFO buffer 14 such as used in a SOC or microcontroller. FIFO buffer 14 consists of a group of latches (illustrated here as n D latches 14[0], ..., 14[n]) that receive data from a write data register 12 and output the data to a read data register 16. Write logic circuitry 13 passes data from write data register 12 to all latches in FIFO buffer 14, and read logic circuitry 15 receives data from all latches in the FIFO buffer and passes it to a read data register 16. The latches of FIFO buffer 14 are enabled by an enable signal.

[0028] Test logic 17 operates on the FIFO buffer 14, the write data register 12 portion of the scan chain, the write logic circuitry 13, the FIFO buffer 14, the read logic circuitry 15, and the read data register 16 portion of the scan chain to perform testing on the FIFO buffer 14, such as using known techniques such as automatic test pattern generation (ATPG) testing and logic built-in self-test (LBIST) testing. The write data register 12 and the read data register 16, which are part of the scan chain, are used during testing to shift data to be written into the FIFO buffer 14 and read data out of the FIFO buffer 14, respectively. Note that a write pointer register Wr_Ptr, a read pointer register Rd_Ptr, and a control register that receives write request signals Wr_Req and read request signals Rd_Req, as described below, also exist as part of the scan chain and are used to select latches to be written to the FIFO buffer 14 and to select latches to be read from the FIFO buffer 14.

[0029] The operation of enabling ATPG testing of the FIFO buffer 14 can test two data paths (from the write data register 12 to the FIFO buffer 14, shown as data path A to B; and from the FIFO buffer 14 to the read data register 16, shown as data path B to C), and now refers to Table 1 (shown below) to describe the stuck-at-1 fault on its latch enable pin.

[0030] Table 1

[0031]

[0032]

[0033] The test begins by setting the scan control signal to logic 1 and the transition mode signal Transition_Mode to logic 0 to indicate that a fixed test is to be performed, and then enters a test setup phase that initializes the FIFO buffer 14 and its associated circuitry for ATPG mode.

[0034] At the beginning of the test setup phase, the scan reset signal is set to logic 0 (e.g., by applying a signal to a pad or pin via external test equipment), thereby resetting the write data register 12 and the read data register 16, forcing their contents to logic 0 (the contents of the write data register 12 are shown as "A out" and the contents of the read data register 16 are shown as "C out" in Table 1). Then, the enable signal at the enable input of the latch of the FIFO buffer 14 (shown as "EN" in Table 1) is asserted by applying a signal to the pad or pin by external test equipment, thereby making these latches transparent.

[0035] In a non-faulty situation (none of the latches experiences a stuck-at-1 fault at its enable pin), the output of FIFO buffer 14 (shown as "B out" in Table 1) will therefore be a logic 0 due to latch transparency, and when the scan reset signal is set to a logic 0, read data register 16 will store a logic 0. In a faulty situation (where one or more latches experience a stuck-at-1 fault at their enable pin), the corresponding latch or latches output from FIFO buffer 14 will remain at a logic 0, and when the scan reset signal is set to a logic 0, read data register 16 will continue to store a logic 0.

[0036] Next, while still in the test setup phase, the enable signals at the enable inputs of the latches of the FIFO buffer 14 are deasserted, causing the latches to latch. Thus, in a non-fault condition (where none of the latches experienced a stuck-at-1 fault at their enable pins), since these latches previously output a logic 0, it is expected that they will continue to do so. Thus, it is expected that the output of the FIFO buffer 14 will be a logic 0, and when the scan reset signal is set to a logic 0, the output of the read data register 16 will remain at a logic 0. In a fault condition (where one or more latches experience a stuck-at-1 fault at their enable pins), since the write data register 12 continues to store a logic 0, the output of one or more corresponding latches from the FIFO buffer 14 will continue to be a logic 0.

[0037] Next, the scan reset signal is set to logic 1, releasing the write data register 12 and the read data register 16 from their reset states. However, no clock pulse is supplied to the write data register 12 yet, so the contents of the write data register 12 remain at logic 0.

[0038] In a non-fault condition (where none of the latches experience a stuck-at-1 fault at their enable pins), the output of FIFO buffer 14 will remain at logic 0 because the enable signals of its latches are still at 0, and the contents of read data register 16 remain at logic 0 because no clock pulse has been provided to read data register 16. In a fault condition (where one or more latches experience a stuck-at-1 fault at their enable pins), since the contents of write data register 12 are still at logic 0, it is expected that the corresponding latch or latches output from FIFO buffer 14 will remain at logic 0, and the contents of read data register 16 remain at logic 0 because no clock pulse has been provided to read data register 16.

[0039] At this point the test setup phase is complete, and the shifting of the ATPG test pattern through the scan chain into the FIFO buffer 14 occurs during the shift phase. As shown, after the last shift, the write data register 12 holds the value of the last bit to be shifted in, which is marked by "as" in Table 1.

[0040] Since the enable signal of FIFO buffer 14 will be at logic 0 at this time, in a non-fault condition (where none of the latches experience a stuck-at-1 fault at their enable pins), the value “as” (which may be logic 0 or logic 1) from write data register 12 has not yet been latched into the output of FIFO buffer 14, and read data register 16 holds the value “cs” (which may also be logic 0 or logic 1) of the last bit to be shifted in. In a fault condition (where one or more latches of FIFO buffer 14 experience a stuck-at-1 fault at their enable inputs), the corresponding latch or latches of FIFO buffer 14 have become transparent, and therefore the output from the corresponding latch or latches of FIFO buffer 14 is the value “as”, and read data register 16 holds the value “cs” of the last bit to be shifted in.

[0041] As the last shift is performed, the capture phase begins. During the capture phase, the scan chain is no longer formed, and the captured value is from the functional path (non-scan path). Since the enable signal to FIFO buffer 14 will be at logic 0 at this time, in a non-faulty situation (where none of the latches of FIFO buffer 14 experience a stuck-at-1 fault at their enable inputs), the value "ac" (which can be either logic 0 or logic 1) from write data register 12 has not yet been latched to the output of FIFO buffer 14, and thus the read data register 16 captures the value "0". In a faulty situation (where one or more latches of FIFO buffer 14 experience a stuck-at-1 fault at their enable inputs), the one or more corresponding latches of FIFO buffer 14 have become transparent, and thus the output captured in the one or more corresponding latches of FIFO buffer 14 is the value "ac", while the read data register 16 captures the value of FIFO buffer 14 at the end of the last shift, which is "as" for the latches with the stuck-at-1 fault at their enable inputs. When the contents of the read data register 16 are shifted out as part of the scan chain, this will create a mismatch on the next shift.

[0042] Describe now the operation of the LBIST test enabling of FIFO buffer 14. Initially, the enable input of FIFO buffer 14 is asserted so that latch becomes transparent and LBIST pattern is generated internally. After feeding a given number of bits by FIFO buffer 14, the enable input of FIFO is deasserted. In non-fault situations (wherein FIFO buffer 14 does not experience stuck-at-1 faults at its enable input), read data register 16 captures the output of FIFO buffer 14 when enable input is deasserted. Therefore, when signature is generated from the data that writes read data register 16 and compared with the known non-fault signature of a given number of bits, mismatch will not occur.

[0043] However, in a fault condition (where one or more latches of the FIFO buffer 14 experience a stuck-at-1 fault at their inputs), the corresponding latch or latches of the FIFO buffer 14 remain transparent, capturing different values ​​from the write data register 12 as the LBIST mode continues. Therefore, when the signature is generated from the data written to the read data register 16 and compared to a known non-faulty signature for a given number of bits, a mismatch will occur, indicating the presence of a stuck-at-1 fault on the enable input of the FIFO buffer 14.

[0044] Details of the write data register 12, write logic 13, FIFO buffer 14, read logic 15 and read data register 16 can be found in Figure 3 In the example shown, the FIFO buffer 14 is composed of 16 latch groups, the 16 latches being labeled DN-0 to D N-15 , where D N-0 For n:0, similarly, D N-1 For n:0, D N-2 For n:0,....D N-15 is n:0, where n is one less than the bit width of the FIFO buffer 14, for example, 31. Write logic 13 and read logic 15 are included within the read / write controller. Write data register 12 stores data 12(a) to be written to the FIFO buffer 14, labeled Wr_Data, and write pointer 12(b) is another register that indicates the address Wr_Addr of the data 12(a) to be written within the FIFO buffer 14. Read data register 16 stores data 16(a) (labeled Rd_Data) read from the FIFO buffer 14 based on a value from read pointer 16(b), which indicates the address Rd_Addr of the data 16(a) to be read. Write / read controller 13 / 15 is operable to receive a write request signal Wr_Req and a read request signal Rd_Req, which respectively indicate when a request is made to write data 12(a) from the write data register 12 to the FIFO buffer 14, and when a request is made to read data 16(a) from the FIFO buffer 14 to the read data register 16. The write / read controller 13 / 15 is further operable to receive the write data pointer 12(b) and the read data pointer 16(b) from the write pointer register 12(b) and the read pointer register 16(b), and to generate a FIFO_Empty signal and a FIFO_Full signal, the FIFO_Empty signal indicating when the FIFO buffer 14 is not full and the FIFO_Full signal indicating when the FIFO buffer 14 is full. Based on the FIFO_Empty signal and the FIFO_Full signal and the write request Wr_Req and the read request Rd_Req, the write / read controller 13 / 15 generates a write enable signal Wr_En (which is a buffered version of the write request signal Wr_Req and serves as an enable signal to the latch group of the FIFO buffer 14 and facilitates writing data to the latch group selected using Wr_Addr [D N-0 or D N-1 or D N-2 ...or D N-15 ]) and the read enable signal Rd_En (which is a buffered version of the read request signal Rd_Req so that at the appropriate time, the latch group [D N-0 or D N-1 or D N-2 ...or D N-15 ] to read data).

[0045] Specifically, when the FIFO buffer 14 is not full, the FIFO buffer 14 has one or more latches that do not store the current data bit. When the FIFO buffer 14 is full, the FIFO buffer 14 stores the current data bit in each latch. The FIFO_Empty signal and the FIFO_Full signal are used by the write / read controller 13 / 15 to generate the write enable signal Wr_En and the read enable signal Rd_En to ensure that data is not written when the FIFO buffer 14 is full (so that the current bit that has not been read is not overwritten), and to ensure that data is not read when the FIFO buffer 14 is empty (so that the non-current bit is not read).

[0046] Now additionally refer to Figure 4 0000_0000), and the data currently stored in the FIFO buffer 14 is 0x0000_0000. Rd_Req at logic 1 is shown as being read, the read enable signal is shown as being at logic 0, the read data register currently contains the data 0x0000_0000 (the same data as stored in the FIFO buffer 14), and the read valid signal Rd_Valid is also at logic 1. At time T1, the write request signal Wr_Req transitions to logic 1, as does the write enable signal Wr_En, because the FIFO_Empty signal is logic 1. Therefore, at time T2, the latch group [D N-0 or D N-1 or D N-2 ...or D N-15 ] (Since the write pointer 12(b) is set to 4'b0000, select D N-0 ) has become transparent by the assertion of the write enable signal Wr_En, and the data 0xABCD_0123 is written into the corresponding latch group [D N-0 ].

[0047] The clock CLK then transitions to logic 0, and then at time T3, the clock CLK goes high again, causing the read enable signal Read_En and the read valid signal Rd_Valid to become logic 1 at time T4, setting up the read operation. At time t4, the write request Wr_Req and the write enable signal Wr_En fall to logic 0, the write data register 12 is loaded with the next data 12 (a) to be written, which is shown here as 0x0000_0000, the write pointer 12 (b) advances to 4'b0001, and due to the write, the FIFO buffer 14 is no longer empty, and therefore the FIFO empty signal FIFO_Empty falls to logic 0. By time T5, the read is complete, and therefore the read request signal Read_Req falls to logic 0 and the read data signal Rd_Valid falls to logic 0. Also as a result of the read completion, the read data register 16 stores the corresponding latch group [D N-0 ]The read data 16(a) of 0xABCD_0123 is read, and the read pointer 16(b) is accordingly advanced to 4'b0001. Since the read is complete, the FIFO buffer 14 is now empty again, and the FIFO empty signal FIFO_Empty rises to logic 1 again.

[0048] Thus, within two clock cycles, writing from the write data register 12 to the FIFO buffer 14 and then reading from the FIFO buffer 14 to the read data register 16 are completed.

[0049] The following describes logic circuitry for generating control signals for the FIFO buffer 14 when used to perform conversion (at-speed) testing. In these specific examples, the FIFO buffer 14 operates based on an internal write enable signal int_Wr_Enan, an internal read enable signal int_Rd_En, and an internal read valid signal int_Rd_Valid generated by the logic circuitry, as opposed to the direct write enable signal Wr_En, write request signal Wr_Req, read enable signal Rd_En, and read request signal Rd_Req described above.

[0050] Now refer to Figures 5A-5D A logic circuit for generating an internal write enable signal int_Wr_En, an internal read enable signal int_Rd_En, and an internal read valid signal int_Rd_Valid when performing an at-speed test upon receiving a clock for the at-speed test as an output of a phase-locked loop (PLL) is described.

[0051] First reference Figure 5A1 and 2 will now describe the first logic circuit 30. The first logic circuit 30 includes a first flip-flop 31 and a second flip-flop 33, both of which are clocked by a clock signal CLK and reset by the complement of a reset signal RST_B. The first flip-flop 31 receives a scan enable signal Scan_En at its data input and generates an output received by the data input of the flip-flop 33. The output of the flip-flop 33 generates an internal scan enable signal Internal_Scan_En, which is received at the input of an AND gate 35. The AND gate 35 also receives the scan enable signal Scan_En as an input via an inverter, receives the output of the flip-flop 31 via an inverter, and generates a gated scan enable signal Gated_Scan_En as an output.

[0052] Now refer to Figure 5B Next, the second logic circuit 40 is described. The second logic circuit 40 includes an AND gate 41 that receives a write request signal Wr_Req / write enable signal Wr_En and a gated scan enable signal Gated_Scan_En as inputs and provides an output to a first data input of a multiplexer 43. Multiplexer 43 has a second data input that receives a signal from an enable pad (labeled En_Pin_From_Pad) and a select input that receives a transition mode signal Transition_Mode. Multiplexer 45 receives the write request signal Wr_Req / write enable signal Wr_En at its second data input, the output of multiplexer 43 at its first data input, the scan control signal Scan_Ctrl at its select input, and generates an internal write enable signal int_Wr_En at its output.

[0053] Now refer to Figure 5C The third logic circuit 50 is described below. The third logic circuit 50 includes an AND gate 51, which receives the read valid signal Rd_Valid as a first input, receives the internal scan enable signal Internal_Scan_En as a second input via an inverter, receives the scan enable signal Scan_En as a third input via an inverter, and provides an output to a multiplexer 53. The multiplexer 53 receives the read valid signal Rd_Valid at a second data input, receives the output of the AND gate 51 at a first data input, receives the transition mode signal Transition_Mode at a select input thereof, and generates the internal read valid signal int_Rd_Valid at an output thereof.

[0054] Now refer to Figure 5DThe fourth logic circuit 60 is described. The fourth logic circuit 60 includes an AND gate 61, which receives the read enable signal Rd_En as a first input, receives the internal scan enable signal Internal_Scan_En as a second input via an inverter, receives the scan enable signal Scan_En as a third input via an inverter, and provides an output to a multiplexer 63. The multiplexer 63 receives the read enable signal Rd_En at its second data input, receives the output of the AND gate 61 at its first data input, receives the transition mode signal Transition_Mode at its select input, and generates the internal read enable signal int_Rd_En at its output.

[0055] The first logic circuit 30 , the second logic circuit 40 , the third logic circuit 50 , and the fourth logic circuit 60 are test glue and MUX logic 98 added on top of the functional logic portion of the write / read controller 13 / 15 .

[0056] Now refer to Figure 6 The operation of performing the ATPG test of the FIFO buffer 14 in the switching mode (at-speed test) when the clock signal CLK is received as the output of the PLL will be described.

[0057] Before time T0 , a shift phase is performed, during which the scan control signal Scan_Ctrl, the transition mode signal Transition_Mode, and the scan enable signal Scan_En are at logic 1.

[0058] Capture begins at time T0. At time T0, the scan enable signal Scan_En transitions to logic 0, while the internal scan enable signal Internal_Scan_En remains at logic 1. The gated scan enable signal Gated_Scan_En is logic 1, the internal write enable signal int_Wr_En is logic 0, and the internal read enable signal Rd_En and the internal read valid signal int_Rd_Valid are logic 0. At this time, the logic values ​​of the write request signal Wr_Req, the write enable signal Wr_En, the read enable signal Rd_En, and the valid read signal Rd_Valid can be 1 or 0 without affecting the operation. Also at this time, the force enable signal from the pad (labeled En_Pin_From_Pad) is forced to logic 0.

[0059] The first capture cycle starts at time T1, where data 0xABCD_0123 is loaded into the write data register 12, and the write request signal Wr_Req and the write enable signal Wr_En rise to logic 1. Note that before time T0, the scan enable signal Scan_En is at logic 1. Therefore, returning to the reference Figure 5A, when the first rising edge of the clock signal CLK in the conversion mode occurs at time T1, the flip-flop 31 already holds a logic 1. This means that at time T1, when the flip-flop 33 is clocked by the clock signal CLK, the internal scan enable signal Internal_Scan_En is set to a logic 1. Also note that since the scan enable signal Scan_En is a logic 0 at this time, when the flip-flop 31 is clocked by the clock signal CLK at time T1, its output is set to a logic 0. Therefore, at time T1, the internal scan enable Internal_Scan_En, the complement of the scan enable Scan_En, and the complement of the output of the flip-flop 31 are all logic 1, which means that the AND gate 35 has received a logic 1 at all inputs, and therefore, as shown in FIG. Figure 6 As shown in the timing diagram of , its output (ie, the gated scan enable signal Gated_Scan_En) rises to logic 1.

[0060] Now return to reference Figure 5B Note that at this time, the AND gate 41 will receive the write request signal Wr_Req / write enable signal Wr_En and the gated scan enable signal Gated_Scan_En at its input, both of which are logic 1. Therefore, the output of the AND gate 41 will be logic 1. Since the transition mode signal Transition_Mode is logic 1 at this time, the multiplexer 43 selects the output of the AND gate 41 as its output. Similarly, Figure 6 As shown in the timing diagram of , since the scan control signal Scan_Ctrl is logic 1 at this time, the multiplexer 45 selects the output of the multiplexer 43 as its output, which serves as the internal write enable signal int_Wr_En.

[0061] Since the internal write enable signal int_Wr_En is used for the operation of the FIFO buffer 14, this means that according to the above-mentioned FIFO operation, one of the latch groups of the FIFO buffer 14 selected based on the Wr_Addr value [D N-0 or D N-1 or D N-2 ...or D N-15 ](Wr_Addr is driven by the write pointer register 12(b) which is part of the scan chain) will become transparent at this time, thereby loading the data 0xABCD_0123 from the write data register 12 into the corresponding latch group of the FIFO buffer 14.

[0062] At the second rising edge of the clock signal CLK, the second rising edge occurs at time T2, as shown in FIG. Figure 6 As reflected in the timing diagram, Figure 5AThe flip-flop 33 passes the logic 0 at its input to its output as the internal scan enable signal Internal_Scan_En. As the internal scan enable signal Internal_Scan_En becomes logic 0, Figure 5A The input of AND gate 35 in becomes logic 0, and thus Figure 6 As shown, the gated scan enable signal Gated_Scan_En falls to logic 0. As the gated scan enable signal Gated_Scan_En falls to logic 0, Figure 5B One of the inputs of AND gate 41 becomes logic 0, indicating that the output of AND gate 41 drops to logic 0. Since the transition mode signal Transition_Mode is still logic 1, multiplexer 43 still selects the output of AND gate 41 as its output. Since the scan control signal Scan_Ctrl is still logic 1, multiplexer 45 still uses the output of multiplexer 43 as its output, resulting in a logic 0 being passed as the internal write enable signal int_Wr_En, which is reflected in Figure 6 The timing diagram is shown in the figure.

[0063] Additionally, since writing is complete, reading can now begin. Therefore, at time T2 and in response to the second rising edge of the clock signal CLK after entering the conversion mode, the read enable signal Rd_En and the read valid signal Rd_Valid rise to logic 1. However, if the last shift value is logic 1, then when it was also logic 1 before T2, as shown in FIG. Figure 6 As shown, since the internal scan enable signal Internal_Scan_En falls to logic 0 at this time, since the scan enable signal Scan_En remains at logic 0, and since the read valid signal Rd_Valid rises to logic 1, the AND gate 51 has logic 1 at each of its inputs and therefore outputs logic 1. Since the transition mode signal Transition_Mode is still logic 1, the multiplexer 53 still selects the output of the AND gate 51 to be passed as the internal read valid signal int_Rd_Valid. Therefore, as Figure 6 As shown in the timing diagram of FIG, at time T2, the internal read valid signal int_Rd_Valid rises to logic 1.

[0064] In addition, since the internal scan enable signal Internal_Scan_En falls to logic 0 at this time, the scan enable signal Scan_En remains at logic 0, and the read enable signal Rd_En rises to logic 1, the AND gate 61 has logic 1 at each of its inputs and thus outputs logic 1. Since the transition mode signal Transition_Mode is still logic 1, the multiplexer 63 still selects the output of the AND gate 61 as the internal read enable signal int_Rd_En. Therefore, as Figure 6As shown in the timing diagram of , at time T2, the internal read enable signal int_Rd_En rises to logic 1.

[0065] At the third rising edge of the clock signal CLK (i.e., at the end of the period started by the previous rising edge of the clock signal CLK), which occurs at time T3, when the data 0xABCD_0123 previously written to the latch group of the FIFO buffer 14 is selected based on the Rd_Addr value of the read data register 16 (Rd_Addr is driven from the read pointer register 16 (b) as part of the scan chain), the reading of the data 0xABCD_0123 previously written to the latch group of the FIFO buffer 14 is completed from the corresponding latch group of the FIFO buffer 14. Therefore, within two clock cycles, the data 0xABCD_0123 has been written from the write data register 12 to the latch group of the FIFO buffer 14 [D N-0 or D N-1 or D N-2 ...or D N-15 ] and has been read from the latch group [D N-0 or D N-1 or D N-2 ...or D N-15 ]Read.

[0066] In some cases, the read valid signal Rd_Valid and the read enable signal Rd_En may fall to logic 0 at time T3. In this case, since the read valid signal Rd_Valid is logic 0, the output of the AND gate 51 therefore falls to logic 0, and the internal read valid signal int_Rd_Valid at the output of the multiplexer 53 will become logic 0; similarly, since the read enable signal Rd_En is logic 0, the output of the AND gate 61 therefore falls to logic 0, and the internal read enable signal int_Rd_En at the output of the multiplexer 63 will become logic 0. In the case where the read valid signal Rd_Valid and the read enable signal Rd_En maintain logic 1 at time T3, the internal read valid signal int_Rd_Valid and the internal read enable signal int_Rd_En remain at logic 1.

[0067] At time T4, the scan enable signal Scan_En rises to logic 1, indicating that the conversion mode test is finished. Since the scan enable signal Scan_En rises to logic 1, the output of the AND gate 51 drops to logic 0, and the internal read valid signal int_Rd_Valid at the output of the multiplexer 53 is logic 0; similarly, the output of the AND gate 61 will also drop to logic 0, and the internal read enable signal int_Rd_En at the output of the multiplexer 63 will become logic 0. This is Figure 6 The timing diagram of the reaction.

[0068] At time T5, the next rising edge of the clock signal CLK arrives, clocking the flip-flops 31 and 33, so that the logic 1 of the scan enable signal Scan_En is passed to the output of the flip-flop 31. At time T6, the next rising edge of the clock signal CLK arrives, and the flip-flops 31 and 33 are clocked again. Therefore, at time T6, as shown in FIG. Figure 6 As shown in the timing diagram of , the logic 1 output of the flip-flop 31 is transmitted through the flip-flop 33 as the internal scan enable signal Internal_Scan_En.

[0069] From the above description, please note that the frequency of the clock signal CLK used during the at-speed test is higher than in other cases.

[0070] Now refer to Figures 7A-7C This section describes the logic circuitry used to generate the internal write enable signal int_Wr_En, the internal read enable signal int_Rd_En, and the internal read valid signal int_Rd_Valid. These signals are used to perform a transition test at a low frequency when the clock for the low-frequency transition test is received from a pad. The transition test performed using the clock received from the pad is due to limitations of the ATE or pad; therefore, while this is a transition test, it is not a full-speed, high-frequency test.

[0071] Now refer to Figure 7A Next, fifth logic circuit 70 is described. Fifth logic circuit 70 includes a first AND gate 71 that receives a write request signal Wr_Req / write enable signal Wr_En and a signal from an enable pad (labeled En_Pin_From_Pad). A first multiplexer 73 receives the output of AND gate 71 at a first input, En_Pin_From_Pad at a second input, and the output of AND gate 77 at a select input, and provides the output to multiplexer 75. AND gate 77 receives a transition mode signal Transition_Mode at a first input and a scan enable signal Scan_En via an inverter at a second input, and provides the output to a select input of multiplexer 73. Multiplexer 75 has a second input that receives the write request signal Wr_Req / write enable signal Wr_En, a first input that receives the output of multiplexer 73, a select input that receives the scan control signal Scan_Ctrl, and an output that generates an internal write enable signal int_Wr_En.

[0072] Now refer to Figure 7BNext, the sixth logic circuit 80 is described. The sixth logic circuit 80 includes an AND gate 81, which receives a read valid signal Rd_Valid and an En_Pin_From_Pad via an inverter as inputs and provides an output to a multiplexer 83. Multiplexer 83 receives the read valid signal Rd_Valid at its second input, the output of AND gate 81 at its first input, the output of AND gate 85 at its select input, and generates an internal read valid signal int_Rd_Valid at its output. AND gate 85 receives a transition mode signal Transition_Mode at its first input, a scan enable signal Scan_En via an inverter at its second input, and provides an output to the select input of multiplexer 83.

[0073] Now refer to Figure 7C Next, the seventh logic circuit 90 is described. The seventh logic circuit 90 includes an AND gate 93, which receives a read enable signal Rd_En and an En_Pin_From_Pad via an inverter as inputs and provides an output to a multiplexer 91. Multiplexer 91 receives the read enable signal Rd_En at its second input, the output of AND gate 93 at its first input, the output of AND gate 95 at its select input, and generates an internal read enable signal int_Rd_En at its output. AND gate 95 receives a transition mode signal Transition_Mode at its first input, a scan enable signal Scan_En via an inverter at its second input, and provides an output to the select input of multiplexer 91.

[0074] Now refer to Figure 8 The operation of performing ATPG testing of the FIFO buffer 14 in transition mode (low frequency) when receiving the clock signal CLK from the pad is described below. Before time T0, shifting is performed, during which the scan control signal Scan_Ctrl, the transition mode signal Transition_Mode, and the scan enable signal Scan_En are at logic 1.

[0075] At time T0, the scan enable signal Scan_En is set to logic 0, thereby starting the capture mode. Note that En_Pin_From_Pad is at logic 1 at this time.

[0076] At time T1, the write request signal Wr_Req and the write enable signal Write_En rise to logic 1, as do the read valid signal Rd_Valid and the read enable signal Rd_En. Figure 7A, the transition mode signal Transition_Mode is logic 1 and the scan enable signal Scan_En is logic 0, which means that the AND gate 77 has logic 1 at both inputs, and thus causes the multiplexer 73 to select its first input to pass as the output. Since the AND gate 71 receives the write request signal Wr_Req and En_Pin_From_Pad, which are both logic 1 at this time, the output of the AND gate 71 is passed through the multiplexer 73 as its output. Since the scan control signal Scan_Ctrl is logic 1 at this time, the multiplexer 75 passes the output of the multiplexer 73 as the output, and thus as shown in Figure 8 As can be observed in FIG, the internal write enable signal int_Wr_En is set to logic 1 at time T1. This allows the data 0xABCD_0123 written in the data register 12 at this time to be written into the latch group [D N-0 or D N-1 or D N-2 ...or D N-15 ] based on a latch group selected based on the Wr_Addr value (Wr_Addr is driven by the write pointer register 12(b) which is part of the scan chain).

[0077] At time T2, data writing to the FIFO buffer 14 is complete, and Ein_Pin_From_Pad drops to logic 0. Since Ein_Pin_From_Pad is logic 0 at this time, the output of the AND gate 71 becomes logic 0, resulting in Figure 8 As can be observed in the timing diagram, the internal write enable signal int_Wr_En falls to logic 0, thus ending the write.

[0078] Return Reference Figure 7B , the transition mode signal Transition_Mode is logic 1 and the scan enable signal Scan_En is logic 0, which means that the AND gate 85 has logic 1 at both inputs, and thus causes the multiplexer 83 to select its first input through as the output. Since the read valid signal Rd_Valid is logic 1 and Ein_Pin_From_Pad has fallen to logic 0 at this time, the AND gate 81 has logic 1 at both inputs, and thus outputs logic 1, as can be seen in Figure 8 As observed in , logic 1 is passed by multiplexer 83 as the internal read valid signal int_Rd_Valid. Return to Reference Figure 7C, the transition mode signal Transition_Mode is logic 1 and the scan enable signal Scan_En is logic 0, which also means that the AND gate 95 has logic 1 at both inputs, and thus causes the multiplexer 91 to select its first input as the output. Since the read enable signal Rd_En is logic 1 at this time and Ein_Pin_From_Pad has fallen to logic 0, the AND gate 93 has logic 1 at both of its inputs and therefore outputs logic 1, as can be seen in Figure 8 As observed in FIG, logic 1 is passed by multiplexer 91 as the internal read enable signal int_Rd_En.

[0079] This sets up the read to be done at T3, and so when a selection is made based on the Rd_Addr value of the read data register 16 (Rd_Addr is driven from the read pointer register 16(b) which is part of the scan chain), the data 0xABCD_0123 previously written to the latch group of the FIFO buffer 14 is seen to be read from the corresponding latch group of the FIFO buffer 14. At time T4, the scan enable signal Scan_En rises to logic 1 to end the conversion mode test.

[0080] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments can be conceived without departing from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. A system operating in a functional mode and a test mode, the system comprising: a write data register, timed by the clock signal and configured to store data to be written; a read data register clocked by the clock signal and configured to store read data therein; a first-in-first-out (FIFO) buffer, comprising a latch group, the latch group being enabled by an enable signal and arranged to store a plurality of words, wherein a word can be selected each time by a write address signal to write the data from the write data register into the latch group, and a word can be selected each time by a read address signal to read the data stored in the latch group into the read data register; a control circuit device configured to receive a write request signal and the write address signal and generate a write enable signal; wherein the control circuit device is further configured to receive a read request signal and the read address signal, and generate a read enable signal; as well as glue logic configured to generate an internal write enable signal from at least the write enable signal and to generate an internal read enable signal from at least the read enable signal; wherein when the system is in the functional mode, the latch group of the FIFO buffer is enabled by the write enable signal and the read enable signal; and When the system is in the test mode, the latch group of the FIFO buffer is enabled by the internal write enable signal and the internal read enable signal.

2. The system of claim 1 , wherein when the test mode is an automatic test pattern generation (ATPG) test mode, the control circuitry and the glue logic cooperate to operate the system in the test mode by: Setting the scan control signal to logic 1 and the conversion mode signal to logic 0 to start the fixed test; The test setup phase is performed to initialize the FIFO buffer for the ATPG test pattern in the following manner: Setting a scan reset signal to logic 0, thereby placing the write data register and the read data register in a reset state; enabling the latch group of the FIFO buffer using an external enable signal, thereby making the latch group transparent; removing the external enable signal, thereby causing the latch group to latch; as well as The scan reset signal is set to logic 1, thereby releasing the write data register and the read data register from the reset state, while not providing the clock signal to the write data register, thereby completing the test setup phase.

3. The system of claim 2 , wherein when the test mode is the ATPG test mode, the control circuitry and the glue logic further cooperate to operate the system in the test mode by: performing a shift phase by shifting ATPG test patterns into the FIFO buffer such that after a last shift, the write data register holds the value of the last bit to be shifted; wherein the FIFO buffer contains the value of the last bit to be shifted when the FIFO buffer experiences a stuck-on-1 fault at the enable input of one or more of the latch groups, but does not contain the value of the last bit to be shifted when the FIFO buffer does not experience the stuck-on-1 fault at the enable input of one or more of the latch groups; and A capture phase is performed wherein the read data register holds a value of a last bit to be shifted when the FIFO buffer experiences the stuck-on-1 fault at the enable inputs of one or more of the latch groups, but holds a logic 0 when the FIFO buffer does not experience the stuck-on-1 fault at the enable inputs of one or more of the latch groups.

4. The system of claim 2 , wherein when the test mode is a logic built-in self-test (LBIST) mode, the control circuitry and the glue logic cooperate to operate the system in the test mode by: enabling the latch group of the FIFO buffer using an enable signal, thereby making the latch group transparent; generating an LBIST pattern and passing the LBIST pattern through the FIFO buffer; and After a given number of bits of the LBIST pattern have passed through the FIFO buffer, the enable signal is de-asserted such that the FIFO buffer continues to pass through the LBIST pattern when the FIFO buffer experiences a stuck-on-1 fault at the enable input of one or more of the latch groups, but stops passing through the LBIST pattern when the FIFO buffer does not experience the stuck-on-1 fault at the enable input of one or more of the latch groups.

5. The system of claim 1 , wherein when the control circuitry and the glue logic cooperate to operate the system in the test mode when the test mode is an automatic test pattern generation (ATPG) mode in which the clock signal is provided by a phase-locked loop (PLL), the circuitry used within the glue logic comprises a first glue logic circuit, the first glue logic circuit comprising: A first flip-flop having a data input for receiving a scan enable signal, an output, and a clock input for receiving the clock signal; a second flip-flop having a data input for receiving the output of the first flip-flop, an output for generating an internal scan enable signal, and a clock input for receiving the clock signal; as well as An AND gate has a first inverting input receiving the scan enable signal, a second inverting input receiving the output of the first flip-flop, and a third non-inverting input receiving the internal scan enable signal, wherein the AND gate generates a gated scan enable signal at its output.

6. The system of claim 5 , wherein when the control circuitry and the glue logic cooperate to operate the system in the test mode when the test mode is the ATPG mode in which the clock signal is provided by a phase-locked loop, the circuitry used within the glue logic comprises a second glue logic circuit, the second glue logic circuit comprising: an AND gate having a first input receiving the write request signal and a second input receiving the gated scan enable signal, and having an output; a first multiplexer having a first data input for receiving a pad enable signal, a second data input for receiving an output of the AND gate, a select input for receiving a conversion mode signal, and an output; as well as A second multiplexer has a first data input receiving the write request signal, a second data input receiving the output of the first multiplexer, a select input receiving a scan control signal, and an output generating the internal write enable signal.

7. The system of claim 6 , wherein when the control circuitry and the glue logic cooperate to operate the system in the test mode when the test mode is the ATPG mode in which the clock signal is provided by a phase-locked loop, the circuitry used within the glue logic comprises a third glue logic circuit, the third glue logic circuit comprising: an AND gate having a first non-inverting input receiving a read valid signal, a second inverting input receiving the internal scan enable signal, a third inverting input receiving the scan enable signal, and an output; as well as A multiplexer has a first data input receiving the read valid signal, a second data input receiving the output of the AND gate of the third glue logic circuit, a select input receiving the conversion mode signal, and an output generating an internal read valid signal.

8. The system of claim 7 , wherein when the control circuitry and the glue logic cooperate to operate the system in the test mode when the test mode is the ATPG mode in which the clock signal is provided by a phase-locked loop, the circuitry used within the glue logic comprises a fourth glue logic circuit, the fourth glue logic circuit comprising: an AND gate having a first non-inverting input receiving the read enable signal, a second inverting input receiving the internal scan enable signal, a third inverting input receiving the scan enable signal, and an output; as well as A multiplexer has a first data input receiving the read enable signal, a second data input receiving the output of the AND gate of the fourth glue logic circuit, a select input receiving the conversion mode signal, and an output generating the internal read enable signal.

9. The system of claim 1 , wherein when the control circuitry and the glue logic cooperate to operate the system in the test mode when the test mode is an automatic test pattern generation (ATPG) mode in which the clock signal is externally provided, the circuitry used within the glue logic comprises a fifth glue logic circuit, the fifth glue logic circuit comprising: a first AND gate having a first input for receiving the write request signal, a second input for receiving a pad enable signal, and an output; a second AND gate having a first non-inverting input receiving a conversion mode signal, a second inverting input receiving a scan enable signal, and an output; a first multiplexer having a first data input receiving the pad enable signal, a second data input receiving the output of the first AND gate, a select input receiving the output of the second AND gate, and an output; as well as A second multiplexer has a first data input receiving the write request signal, a second data input receiving the output of the first multiplexer, a select input receiving a scan control signal, and an output generating the internal write enable signal.

10. The system of claim 9 , wherein when the control circuitry and the glue logic cooperate to operate the system in the test mode when the test mode is the ATPG mode in which the clock signal is externally provided, the circuitry used within the glue logic further comprises a sixth logic circuit, the sixth logic circuit comprising: a first AND gate having a first non-inverting input receiving a read valid signal, a second inverting input receiving the pad enable signal, and an output; a second AND gate having a first non-inverting input receiving the conversion mode signal, a second inverting input receiving the scan enable signal, and an output; as well as A multiplexer has a first data input receiving the read valid signal, a second data input receiving the output from the first AND gate, a select input receiving the output of the second AND gate, and an output generating an internal read valid signal.

11. The system of claim 10 , wherein when the control circuitry and the glue logic cooperate to operate the system in the test mode when the test mode is the ATPG mode in which the clock signal is externally provided, the circuitry used within the glue logic further includes a seventh logic circuit, the seventh logic circuit comprising: a first AND gate having a first non-inverting input receiving a read enable signal, a second inverting input receiving the pad enable signal, and an output; a second AND gate having a first non-inverting input receiving the conversion mode signal, a second inverting input receiving the scan enable signal, and an output; as well as a multiplexer having a first data input receiving the read enable signal, a second data input receiving the output of the first AND gate from the seventh logic circuit, a select input receiving the output of the second AND gate of the seventh logic circuit, and an output generating the internal read enable signal.

12. A system operable in a functional mode and a test mode, the system comprising: a write data register, timed by the clock signal and configured to store data to be written; a read data register, clocked by the clock signal and configured to store read data; a first-in-first-out (FIFO) buffer, comprising a latch group, the latch group being enabled by an enable signal and arranged to store a plurality of words, wherein a word is selected at a time by a write address signal to write the data from the write data register to the latch group, and a word is selected at a time by a read address signal to read the data stored in the latch group to the read data register; a control circuit device configured to receive a write request signal and the write address signal and generate a write enable signal; wherein the control circuit device is further configured to receive a read request signal and the read address signal, and generate a read enable signal; Glue logic is configured to generate an internal write enable signal from at least the write enable signal and to generate an internal read enable signal from at least the read enable signal.

13. The system of claim 12, wherein the glue logic comprises a first glue logic circuit, the first glue logic circuit comprising: a first flip-flop having a data input for receiving a scan enable signal, an output, and a clock input for receiving the clock signal; a second flip-flop having a data input for receiving the output of the first flip-flop, an output for generating an internal scan enable signal, and a clock input for receiving the clock signal; as well as An AND gate has a first inverting input receiving the scan enable signal, a second inverting input receiving the output of the first flip-flop, and a third non-inverting input receiving the internal scan enable signal, wherein the AND gate generates a gated scan enable signal at its output.

14. The system of claim 13, wherein the glue logic further comprises a second glue logic circuit, the second glue logic circuit comprising: an AND gate having a first input receiving the write request signal and a second input receiving the gated scan enable signal, and having an output; a first multiplexer having a first data input for receiving a pad enable signal, a second data input for receiving an output of the AND gate, a select input for receiving a conversion mode signal, and an output; as well as A second multiplexer has a first data input receiving the write request signal, a second data input receiving the output of the first multiplexer, a select input receiving a scan control signal, and an output generating the internal write enable signal.

15. The system of claim 14, wherein the glue logic further comprises a third glue logic circuit, the third glue logic circuit comprising: an AND gate having a first non-inverting input receiving a read valid signal, a second inverting input receiving the internal scan enable signal, a third inverting input receiving the scan enable signal, and an output; as well as A multiplexer has a first data input receiving the read valid signal, a second data input receiving the output of the AND gate of the third glue logic circuit, a select input receiving the conversion mode signal, and an output generating an internal read valid signal.

16. The system of claim 15, wherein the glue logic further comprises a fourth glue logic circuit, the fourth glue logic circuit comprising: an AND gate having a first non-inverting input receiving the read enable signal, a second inverting input receiving the internal scan enable signal, a third inverting input receiving the scan enable signal, and an output; as well as A multiplexer has a first data input receiving the read enable signal, a second data input receiving the output of the AND gate of the fourth glue logic circuit, a select input receiving the conversion mode signal, and an output generating the internal read enable signal.

17. The system of claim 12, wherein the glue logic comprises a fifth glue logic circuit, the fifth glue logic circuit comprising: a first AND gate having a first input for receiving the write request signal, a second input for receiving a pad enable signal, and an output; a second AND gate having a first non-inverting input receiving a conversion mode signal, a second inverting input receiving a scan enable signal, and an output; a first multiplexer having a first data input receiving the pad enable signal, a second data input receiving the output of the first AND gate, a select input receiving the output of the second AND gate, and an output; as well as A second multiplexer has a first data input receiving the write request signal, a second data input receiving the output of the first multiplexer, a select input receiving a scan control signal, and an output generating the internal write enable signal.

18. The system of claim 17, wherein the glue logic further comprises a sixth logic circuit, the sixth logic circuit comprising: a first AND gate having a first non-inverting input receiving a read valid signal, a second inverting input receiving the pad enable signal, and an output; a second AND gate having a first non-inverting input receiving the conversion mode signal, a second inverting input receiving the scan enable signal, and an output; as well as A multiplexer has a first data input receiving the read valid signal, a second data input receiving the output from the first AND gate, a select input receiving the output of the second AND gate, and an output generating an internal read valid signal.

19. The system of claim 18, wherein the glue logic further comprises a seventh logic circuit, the seventh logic circuit comprising: a first AND gate having a first non-inverting input receiving a read enable signal, a second inverting input receiving the pad enable signal, and an output; a second AND gate having a first non-inverting input receiving the conversion mode signal, a second inverting input receiving the scan enable signal, and an output; as well as a multiplexer having a first data input receiving the read enable signal, a second data input receiving the output of the first AND gate from the seventh logic circuit, a select input receiving the output of the second AND gate of the seventh logic circuit, and an output generating the internal read enable signal.

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