Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device includes a semiconductor element, and first and second conductors joined to first and second surfaces of the semiconductor element via Sn-based solders. In the semiconductor device, a Ni-based plating layer is formed on surfaces of the first and second conductors opposite the Sn-based solders, and the first and second surfaces of the semiconductor element. An interface reaction suppression layer composed of (Cu, Ni)6Sn5 having a layer thickness of 1.2 to 4.0 μm is formed on an interface between the Ni-based plating layer and the Sn-based solder.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] Semiconductor devices are used in inverters that convert AC power to DC power. For example, in automotive inverters, the use of lead-free solders, primarily Sn-3Ag-0.5Cu (mass%), is being promoted due to the restrictions on lead use imposed by the RoHS or ELV directives.

[0003] In semiconductor devices used in inverters, the trend is towards miniaturization and lightweighting with high power density. This requires bonding the two sides of the semiconductor element with conductor solder to improve heat dissipation from both sides of the semiconductor element, or ensuring that the junction of the semiconductor element and the conductor is at a high temperature to allow a large amount of current to flow.

[0004] On the other hand, automotive semiconductor components have an area exceeding 10mm × 10mm and a thickness as thin as approximately 100μm. Therefore, if solder is applied to both sides, stress relief cannot be achieved compared to soldering only one side of the semiconductor component, making the semiconductor component prone to breakage. Furthermore, while Sn-3Ag-0.5Cu solder can ensure reliability at temperatures below 150°C at the junction of the semiconductor component, the interface reaction between the solder and conductor accelerates at 175°C, leading to deterioration at the junction interface.

[0005] Figure 1 (A) Figure 1 (C) is a schematic diagram illustrating the degradation of Sn-based solder at high temperatures. For example... Figure 1 As shown in (A), as an example, Sn-based solder 1 is placed on a conductor (Cu) 2 with a Ni plating layer 3. At high temperature, as the interfacial reaction between the Sn-based solder 1 and the Ni plating layer 3 progresses, as... Figure 1 As shown in (B), the Ni coating 3 becomes thinner, forming a brittle intermetallic compound like Ni-Sn compound 4 at the interface. Further, as... Figure 1 As shown in (C), the Ni plating layer 3 disappears, and brittle intermetallic compounds such as Ni-Sn compound 4 and Cu-Sn compound 5 further thicken at the joint interface, generating voids 6 and causing volume changes. This leads to deterioration of the joint interface, which is associated with a decrease in joint strength or an increase in thermal resistance.

[0006] As a connection method with a heat resistance of 200°C, Patent Document 1 describes a semiconductor device with a heat resistance of over 200°C by combining a Sn-based solder containing a Cu6Sn5 phase and a Ni-based plating layer at room temperature to 200°C to suppress interfacial reactions.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent document: Japanese Patent Application Publication No. 2014-123745 Summary of the Invention

[0010] The problem the invention aims to solve

[0011] In the device described in Patent Document 1, when the structure is made to increase the bonding area of ​​the semiconductor element and bond both sides of the semiconductor element, the stress generated on the semiconductor element increases, and a thick intermetallic compound is formed at the interface between the semiconductor element and the solder, making the semiconductor element prone to breakage.

[0012] Technical means to solve the problem

[0013] The semiconductor device according to a first aspect of the present invention comprises: a semiconductor element; and a first conductor and a second conductor, which are bonded to a first surface and a second surface of the semiconductor element respectively through a Sn-based solder. Preferably, a Ni-based plating layer is formed on the surfaces of the first conductor and the second conductor opposite to the Sn-based solder, and on the first surface and the second surface of the semiconductor element. An interface reaction suppression layer with a thickness of 1.2 to 4.0 μm, composed of (Cu, Ni)6Sn5, is formed at the interface between the Ni-based plating layer and the Sn-based solder.

[0014] The semiconductor device manufacturing method of the second aspect of the present invention preferably involves forming a Ni plating layer on a lead frame on the collector side, supplying a Sn-Ag-Cu based solder with a Cu content of 1.5 mass% or more to the Ni plating layer to bond a semiconductor element, supplying a Sn-Cu based solder with a Cu content of 1.5 mass% or more to the semiconductor element, and bonding a lead frame on the emitter side for which a Cu plating layer has been applied on the Ni plating layer.

[0015] The semiconductor device manufacturing method of the third aspect of the present invention preferably involves forming a Ni plating layer on a lead frame on the collector side, forming a Cu plating layer on the Ni plating layer, supplying a Sn-Ag-Cu based solder with a Cu content of 1.5 mass% or more on the Cu plating layer to bond a semiconductor element, supplying a Sn-Cu based solder with a Cu content of 1.5 mass% or more on the semiconductor element, and bonding a lead frame on the emitter side on which a Cu plating layer has been applied on the Ni plating layer.

[0016] The effects of the invention

[0017] According to the present invention, it is possible to suppress the deterioration of the interface at the solder joint and prevent the semiconductor device from cracking. Attached Figure Description

[0018] Figure 1 (A) to (C) are schematic diagrams of the degradation of Sn-based solder at high temperatures.

[0019] Figure 2 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0020] Figure 3 This is a table representing the setting values ​​of the semiconductor device in the first embodiment.

[0021] Figure 4 (A) and (B) are schematic diagrams of cracks generated on the Al electrode of a semiconductor device.

[0022] Figure 5 This is a cross-sectional diagram illustrating the definition of the thickness of the interfacial reaction inhibition layer.

[0023] Figure 6 This is a graph showing the relationship between the thickness of the interfacial reaction inhibition layer and the thickness of the vanished Ni coating.

[0024] Figure 7 This is a schematic diagram of a semiconductor element breaking on a cross-section of a semiconductor device.

[0025] Figure 8 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0026] Figure 9 This is a table representing the setting values ​​of the semiconductor device in the second embodiment.

[0027] Figure 10 This is a table showing the tests of the semiconductor devices used as comparative examples. Detailed Implementation

[0028] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following description and drawings are examples for illustrating the present invention; for clarity of explanation, appropriate omissions and simplifications have been made. The present invention may also be implemented in various other ways. Unless otherwise specified, each constituent element may be one or more.

[0029] To facilitate understanding of the present invention, the positions, sizes, shapes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, shapes, or extents. Therefore, the present invention is not limited to the positions, sizes, shapes, and extents disclosed in the accompanying drawings.

[0030] [First Implementation]

[0031] Figure 2 This is a cross-sectional view of the semiconductor device according to this embodiment.

[0032] like Figure 2 As shown, a Ni plating layer 17 is formed on the lead frame 12, which serves as the collector side conductor. Furthermore, the Ni plating layer 17 is formed by laser processing the solder mounting surface of the Cu lead frame 12, which has a roughened Ni plating layer 16, to create a smooth Ni plating surface. Sn-Ag-Cu solder 15 is supplied to the solder mounting surface of the Ni plating layer 17 to bond one side of a semiconductor element 13 having electrodes including a Ni-P plating layer 18. Sn-Cu solder 14 is supplied to the other side of the semiconductor element 13 having electrodes including the Ni-P plating layer 18 to bond the lead frame 11, which serves as the emitter side conductor on which the Ni plating layer 17 is applied.

[0033] Furthermore, the lead frame 11 on the emitter side is pre-oxidized, and only the solder joint surface is laser-treated to remove the oxide film. The solder mounting surface of the Ni plating 17 is also smoothed. This prevents the wetting of the Sn-Cu solder 14. After bonding to the lead frame 11 on the emitter side, the gate electrode of the semiconductor element 13 is wire-bonded and sealed with molding resin 19. Although not shown in the figures below, after sealing with molding resin 19, heat sinks for cooling are bonded to the exposed lead frame 11 and lead frame 12 via insulating resin. That is, this embodiment is a two-sided cooling type semiconductor device.

[0034] exist Figure 2 In the semiconductor device shown, as described above, the Ni plating 17 on the solder mounting surface to be soldered is a smooth Ni plating that easily ensures solder wetting. On the other hand, the Ni plating on the portion of the lead frames 11, 12 that contacts the molding resin 19 is a roughened Ni plating 16. This improves the adhesion strength between the lead frames 11, 12 and the molding resin 19, ensuring reliability. Furthermore, by pre-forcing oxidation of the Ni plating 17 on the emitter side of the lead frame 11, Sn-based solder 14 can be prevented from wetting onto the lead frame 11 during solder bonding on the emitter side, making it easy to control the desired solder thickness. Since wetting can be prevented, the contact area between the roughened Ni plating 16 on the lead frame 11 and the molding resin 19 increases, thus achieving higher reliability.

[0035] If a semiconductor device manufactured as described above is assembled and powered as an inverter, it becomes a high-temperature process. At high temperatures, such as... Figure 2As shown, an interface reaction suppression layer 8, composed of (Cu, Ni)6Sn5, with a thickness of 1.2 to 4.0 μm, is formed at the interface between the Ni-based plating layer 17 and the Sn-Cu-based solder 14 and Sn-Ag-Cu-based solder 15 (collectively referred to as Sn-based solder). Furthermore, the thickness of the interface reaction suppression layer 8 is more preferably 1.4 to 3.2 μm.

[0036] The solder joint 30 on the emitter side is composed of Sn-Cu solder 14 and an interface reaction suppression layer 8. The solder joint 31 on the collector side is composed of Sn-Ag-Cu solder 15 and an interface reaction suppression layer 8.

[0037] Figure 3 This is a table showing test examples of the semiconductor device according to this embodiment.

[0038] like Figure 3 As shown, the set values ​​for the composition 301, thickness 302, and thickness 303 of the Sn-Cu solder 14 in the solder joint 30 on the emitter side were recorded for Test Examples 1 to 6. Furthermore, the set values ​​for the composition 311, thickness 312, and thickness 313 of the Sn-Ag-Cu solder 15 in the solder joint 31 on the collector side were recorded for Test Examples 1 to 6. Furthermore, the results of the 175°C high-temperature holding test 321 and power cycling test 322 for bonding reliability were recorded for Test Examples 1 to 6.

[0039] For example, in Test Example 1, the Sn-Cu solder 14 has a composition 301 of Sn-2Cu, a solder joint 30 thickness 302 of 120-200 μm, and an interface reaction inhibition layer 8 thickness 303 of 1.2 μm. The Sn-Ag-Cu solder 15 has a composition 311 of Sn-3Ag-2Cu, a solder joint 31 thickness 312 of 70-100 μm, an interface reaction inhibition layer 8 thickness 313 of 1.2 μm, a high temperature holding test 321 of 175°C is good (○), and a power cycling test 322 is good (○).

[0040] The 175°C high-temperature holding test 321 is a test that maintains the temperature at 175°C for 1000 hours. The power cycling test 322 is a test that performs 50,000 cycles at temperatures ranging from 175°C to 75°C. The results show that if the desired electrical characteristics are maintained despite voltage changes between the emitter and collector after the test, it is rated ○; if the electrical characteristics deteriorate, it is rated ×. The evaluation assesses three semiconductor devices for each of Test Examples 1 to 6. The results are as follows: Figure 3As shown, the electrical characteristics of the semiconductor element 13 did not deteriorate in any of Test Examples 1 to 6.

[0041] As Figure 3 shown in Test Examples 1 to 6, the thickness 302 of the solder joint 30 on the emitter side of the semiconductor device is 120 to 200 μm, and the thickness 312 of the solder joint 31 on the collector side is 70 to 100 μm. That is, the solder joint 30 on the emitter side is thicker than the solder joint 31 on the collector side. Thereby, it is possible to suppress cracking of the semiconductor element 13, cracks generated in the solder layer, and creep voids caused by the difference between heat generation and cooling when the semiconductor element 13 is repeatedly turned on and off.

[0042] [[ID=URL8]]In addition, as Figure 3 shown in Test Examples 1 to 6, the Cu content rate of the Sn-Cu-based solder 14 on the emitter side is 2 mass% or more and does not contain Ag. The Cu content rate of the Sn-Ag-Cu-based solder 15 on the collector side is 2 mass% or more and contains Ag of 2 to 4 mass%. By making the Cu content rate of the Sn-Ag-Cu-based solder 15 on the collector side 2 mass% or more and containing Ag of 2 to 4 mass%, the strength of the Sn-Ag-Cu-based solder 15 can be increased, and crack propagation to the Sn-Ag-Cu-based solder 15 can be suppressed. When the Cu content rate of the Sn-Ag-Cu-based solder 15 is 5 mass% or more, stability of the joint interface can be obtained even at a higher temperature.

[0043] Figure 4 of (A), Figure 4 of (B) is a schematic diagram of cracks generated on the Al electrode 22 of the semiconductor element 13. Figure 4 of (A) and its magnification Figure 1 together represent cracks generated on the Al electrode 22 of the semiconductor element 13 when reliability cannot be obtained. Figure 4 of (B) and its magnification Figure 1 together represent that no cracks are generated on the Al electrode 22 of the semiconductor element 13 when reliability is obtained.

[0044] As Figure 4 shown in (A), in the structure of the semiconductor element 13 in which both sides of the semiconductor element 13 are joined to the lead frames 11 and 12 by the Sn-based solder 14, cracks C sometimes occur on the Al electrode 22 of the semiconductor element 13. As described above, in Figure 3 Test Examples 1 to 6, the Cu content rate of the composition 301 of the Sn-Cu-based solder 14 on the emitter side is 2 mass% or more and does not contain Ag. Thereby, as Figure 4As shown in (B), it is possible to suppress the formation of cracks on the Al electrode 22 formed on the upper surface of the semiconductor element 13.

[0045] Figure 5 This is a cross-sectional view illustrating the definition of the thickness of the interface reaction inhibition layer 8.

[0046] Sn-based solder 1 is applied to a conductor (Cu) 2 with a Ni plating layer 3. As described above, at high temperature, the interfacial reaction between the Sn-based solder 1 and the Ni plating layer 3 is advanced, forming an interfacial reaction suppression layer 8 composed of (Cu, Ni)6Sn5. Here, since the interfacial reaction suppression layer 8 has unevenness, therefore... Figure 5 As shown, the thickness of the interface reaction inhibition layer 8 is defined as the average thickness that makes the (Cu, Ni)6Sn5 formed on the Ni coating layer 3 smooth. Figure 3 The thicknesses 303 and 313 of the interface reaction inhibition layer 8 shown are based on this definition.

[0047] Figure 6 This is a graph showing the relationship between the thickness of the interfacial reaction inhibition layer 8 and the thickness of the disappeared Ni coating 17. Figure 6 The horizontal axis represents the thickness of the interface reaction inhibition layer 8 composed of (Cu, Ni)6Sn5, and the vertical axis represents the thickness of the Ni coating 17 that disappears after being kept at 175°C for 1000 hours.

[0048] By applying a Ni-based plating to the semiconductor element 13 and the bonded lead frames (conductors) 11 and 12, the interface reaction is delayed even when maintained at a high temperature of 175°C, compared to a pure Cu lead frame. Furthermore, as... Figure 6 As shown, if the thickness of the interface reaction suppression layer 8 is about 1.2 μm or less, the Ni plating layer 17 that disappears after being kept at 175°C for 1000 hours becomes larger, and the possibility of the Ni plating layer 17 disappearing increases. On the other hand, by forming an interface reaction suppression layer 8 composed of (Cu, Ni)6Sn5 with a thickness of 1.2 to 4.0 μm, more preferably 1.4 to 3.2 μm, on the Ni plating layer 17, such as... Figure 6 As shown, the disappearing Ni coating 17 is small, and the interfacial reaction can be effectively suppressed at a high temperature of 175℃.

[0049] Figure 7 This is a schematic diagram of the fracture of semiconductor element 13 in the cross-section of a semiconductor device.

[0050] If the interfacial reaction inhibition layer 8 is 4.0 μm or larger, the interfacial reaction can be suppressed more effectively, but if... Figure 7As shown, in a structure where the two sides of the semiconductor element 13 are bonded to the lead frames 11 and 12 by Sn-based solder 14, cracking 7 of the semiconductor element 13 may occur. Therefore, by making the thickness of the interface reaction suppression layer 8 1.2 to 4.0 μm, more preferably 1.4 to 3.2 μm, cracking 7 of the semiconductor element 13 can be prevented and interface reactions can be suppressed.

[0051] [Second Implementation]

[0052] Figure 8 This is a cross-sectional view of the semiconductor device according to the second embodiment. (Regarding...) Figure 2 The same parts shown in the first embodiment are marked with the same symbols, and their descriptions are omitted.

[0053] In this embodiment, a Cu component 20 is incorporated in at least one of the Sn-Cu solder 14 or the Sn-Ag-Cu solder 15. The Cu component 20 is, for example, a Cu powder paste, a mixture of Cu powder and solder powder, or a Cu wire. As a result, Cu can diffuse into the Sn-Cu solder 14 or the Sn-Ag-Cu solder 15 during bonding, and an interface reaction suppression layer 8 composed of (Cu, Ni)6Sn5 can be easily formed on the solder joint 30 on the emitter side or the solder joint 31 on the collector side at a desired thickness.

[0054] like Figure 8 As shown, the solder mounting surface of the lead frame 12, which is a Cu conductor having a roughened Ni plating layer 16, is laser-treated to form a smooth Ni plating layer 17. A desired amount of paste, which is a Cu component 20, is supplied to the Ni plating layer 17. The paste is composed of Cu powder, Sn powder, and solvent with a diameter of 15 μm. Then, Sn-based solder 15 on the collector side is supplied to the solder mounting position. A semiconductor element 13 having an electrode containing a Ni-P plating layer 18 is mounted and bonded thereon. As a result, Cu diffuses from the Cu powder into the solder, and the formation of the interface reaction suppression layer 8 composed of (Cu, Ni)6Sn5 at the bonding interface becomes easier. In addition, a (Cu, Ni)6Sn5 compound 21 is formed around the Cu component 20. Furthermore, Sn-based solder 14 is supplied to the electrode containing the Ni-P plating layer 18 on the upper surface of the bonded semiconductor element 13. Alternatively, before the solder is supplied, a desired amount of paste for the Cu component 20 is supplied in advance, the paste consisting of Cu powder, Sn powder, and solvent with a diameter of 15 μm. A Cu lead frame 11 with a roughened Ni plating 16 is then bonded there.

[0055] The emitter-side lead frame 11 is pre-oxidized, and only the solder joint surface is laser-treated to remove the oxide film. Simultaneously, the surface of the Ni plating layer 17 is smoothed. This prevents solder wetting. After mounting the emitter-side lead frame 11, the gate electrode of the semiconductor element 13 is wire-bonded, and then sealed with molding resin 19. Although not shown in the figures below, after sealing with molding resin 19, heat sinks for cooling are bonded to the exposed lead frames 11 and 12 via insulating resin. That is, this embodiment is a two-sided cooling type semiconductor device.

[0056] exist Figure 8 In this example, a Ni plating layer 17 is formed on the lead frame 12 on the collector side, and a Sn-Ag-Cu based solder 15 with a Cu content of 1.5 mass% or more, which incorporates the Cu component 20, is supplied to the Ni plating layer 17 to bond the semiconductor element 13. Then, a Sn-Cu based solder 14 with a Cu content of 1.5 mass% or more is supplied to the semiconductor element 13, and the lead frame 11 on the emitter side, on which a Cu plating layer is applied, is bonded. Furthermore, an example using a Sn-Ag-Cu based solder 15 with a Cu content of 1.5 mass% or more, which incorporates the Cu component 20, has been described, but it is also possible to omit the Cu component 20. In this case, a Cu plating layer is formed on the Ni plating layer 17 instead of the Cu component 20.

[0057] If a semiconductor device manufactured as described above is assembled and powered as an inverter, it will generate high temperatures. For example... Figure 8 As shown, at high temperature, an interface reaction suppression layer 8 with a thickness of 1.2 to 4.0 μm is formed at the interface between the Ni-based plating layer 17 and the Sn-Cu-based solder 14 and Sn-Ag-Cu-based solder 15 (collectively referred to as Sn-based solder). The layer is composed of (Cu, Ni)6Sn5. Furthermore, the thickness of the interface reaction suppression layer 8 is more preferably 1.4 to 3.2 μm.

[0058] Figure 9 This is a table showing test examples of the semiconductor device according to this embodiment.

[0059] like Figure 9 As shown, with Figure 3Similarly, for Test Examples 7 and 8, the set values ​​for the composition 301, thickness 302, and interface reaction suppression layer 8 of the Sn-Cu solder 14 in the emitter-side solder joint 30, the composition 311, thickness 312, and interface reaction suppression layer 8 of the Sn-Ag-Cu solder 15 in the collector-side solder joint 31, respectively, were recorded. Furthermore, the results of the 175°C high-temperature holding test 321 and power cycling test 322 for bonding reliability were recorded for Test Examples 7 and 8, respectively.

[0060] For example, in Test Example 7, the Sn-Cu solder 14 has a composition 301 of Sn-2Cu, a solder joint 30 thickness 302 of 120-200 μm, and an interface reaction inhibition layer 8 thickness 303 of 1.8 μm. The Sn-Ag-Cu solder 15 has a composition 311 of Sn-3Ag-2Cu+Cu, a solder joint 31 thickness 312 of 70-100 μm, an interface reaction inhibition layer 8 thickness 313 of 2.5 μm, and a high temperature holding test 321 of 175°C is good (○), and a power cycling test 322 is good (○).

[0061] In Test Example 8, the Sn-Cu solder 14 had a Sn-2Cu+Cu component in composition 301, a solder joint 30 thickness 302 of 120-200 μm, and an interface reaction inhibition layer 8 thickness 303 of 2.8 μm. The Sn-Ag-Cu solder 15 had a Sn-3Ag-2Cu+Cu component in composition 311, a solder joint 31 thickness 312 of 70-100 μm, and an interface reaction inhibition layer 8 thickness 313 of 2.5 μm. The high temperature holding test 321 at 175°C was good (○), and the power cycling test 322 was good (○).

[0062] The 175°C high-temperature holding test 321 is a test that maintains the temperature at 175°C for 1000 hours. The power cycling test 322 is a test that performs 50,000 cycles at temperatures ranging from 175°C to 75°C. The results show that if the desired electrical characteristics are maintained despite voltage changes between the emitter and collector after the test, it is rated ○; if the electrical characteristics deteriorate, it is rated ×. The evaluation assesses three semiconductor devices for each of Test Examples 7 and 8. The results are as follows: Figure 9 As shown, the electrical characteristics of semiconductor element 13 did not deteriorate in either Test Example 7 or Test Example 8.

[0063] By attaching a Cu component 20 to the lead frame 12 on the collector side, Cu diffuses into the solder when the semiconductor element 13 is bonded by supplying Sn-Ag-Cu based solder 15. This allows for the easy formation of an interface reaction suppression layer 8 of desired thickness, composed of (Cu, Ni)6Sn5, on the Ni-based plating 17 of the semiconductor element 13 and the lead frame 12. Furthermore, by bonding the emitter-side lead frame 11, to which the Cu component 20 is attached, to the semiconductor element 13 using Sn-Cu based solder 14, an interface reaction suppression layer 8 of desired thickness can be easily formed on the Ni-based plating 17 of the semiconductor element 13 and the lead frame 11. If the Cu component 20 is a paste containing Cu particles, Cu can diffuse effectively into the solder, enabling rapid formation of the interface reaction suppression layer 8.

[0064] Furthermore, instead of using Cu component 20, Cu plating is performed on the Ni plating 17 of the lead frames 12, 11 on the collector and emitter sides, thereby allowing the Cu plating to fully react with the solder. That is, during solder bonding, Cu diffuses from the Cu plating into the solder, making it easy to form an interface reaction suppression layer 8 of the desired thickness on the Ni plating 17 of the semiconductor element 13.

[0065] [Comparative Example]

[0066] Figure 10 This is a table showing the tests of the semiconductor devices used in comparative examples. The comparative examples are semiconductor devices that do not rely on this embodiment.

[0067] like Figure 10 As shown, with Figure 3 Similarly, for Comparative Examples 1 to 5, the set values ​​for the composition 301 of the Sn-Cu solder 14 in the emitter-side solder joint 30, the thickness 302 of the solder joint 30, the thickness 303 of the interface reaction suppression layer 8, the composition 311 of the Sn-Ag-Cu solder 15 in the collector-side solder joint 31, the thickness 312 of the solder joint 31, and the thickness 313 of the interface reaction suppression layer 8 are described respectively. Furthermore, for Comparative Examples 1 to 5, the results of the high-temperature holding test 321 at 175°C and the power cycling test 322 in terms of bonding reliability are described respectively.

[0068] For example, in Comparative Example 1, the Sn-Cu solder 14 has a composition 301 of Sn-3Ag-0.5Cu, a solder joint 30 thickness 302 of 120-200 μm, and an interface reaction inhibition layer 8 thickness 303 of 1.0 μm. The Sn-Ag-Cu solder 15 has a composition 311 of Sn-3Ag-0.5Cu, a solder joint 31 thickness 312 of 70-100 μm, an interface reaction inhibition layer 8 thickness 313 of 0.8 μm, a high temperature holding test 321 of 175°C is not possible (×), and a power cycling test 322 is not possible (×).

[0069] Comparative Examples 1 and 2 both showed × in both the high-temperature holding test and the power cycling test. This is because the interfacial reaction inhibition layer composed of (Cu, Ni)6Sn5 formed at the joint interface did not reach a sufficient thickness, thus causing the joint interface to deteriorate.

[0070] Comparative Example 3 achieved a power cycling test score of ○, but a high-temperature holding test score of ×. This is because, compared to Comparative Examples 1 and 2, although the interfacial reaction suppression layer composed of (Cu, Ni)6Sn5 formed at the joint interface was thick, it was not thick enough, thus the joint interface deteriorated.

[0071] Comparative Examples 4 and 5 sufficiently formed an interface reaction suppression layer composed of (Cu, Ni)6Sn5 at the junction interface, thus achieving a zero result in the high-temperature holding test. However, both failed the power cycling test. In Comparative Example 4, the interface reaction suppression layer was thick, resulting in higher stress on the semiconductor element 13 and subsequent cracking. In Comparative Example 5, the Sn-based solder on the emitter side contained Ag, making the solder harder, which caused crack propagation on the Al electrode 22 of the semiconductor element 13.

[0072] Prior to this embodiment, it was considered to use a binary solder to bond Sn-Cu solder with a Cu content of 3 to 7% to a component having a Ni-based metallization layer. However, it was found that in the case of bonding the upper and lower surfaces of a semiconductor element 13 with a thickness of about 100 μm in an area of ​​more than 10 mm × 10 mm, it was not possible to simultaneously suppress the degradation of the bonding interface at high temperatures and suppress the cracking of the semiconductor element 13 in a semiconductor device without relying on this embodiment.

[0073] Generally, if the bonding area of ​​the semiconductor element 13 increases, the stress generated on the semiconductor element 13 increases. In addition, since the intermetallic compound composed of (Cu, Ni)6Sn5 is formed thickly at the interface between the semiconductor element 13 and the solder, the semiconductor element 13 is more prone to cracking.

[0074] According to this embodiment, in order to both suppress the degradation of the junction interface at high temperatures and suppress the cracking of the semiconductor element 13, the thickness of the interface reaction suppression layer formed at the junction interface, which is composed of (Cu, Ni)6Sn5, can be set to an appropriate thickness. As a result, in a semiconductor device in which the two sides of a semiconductor element 13 with a thickness of about 100 μm are bonded with Sn-based solder in an area of ​​more than 10 mm × 10 mm, the degradation of the junction interface and the cracking of the semiconductor element 13 can be suppressed even at a high temperature of 175°C.

[0075] The following effects can be obtained by implementing the methods described above.

[0076] (1) A semiconductor device includes: a semiconductor element 13; a first conductor (lead frame 11 on the emitter side) and a second conductor (lead frame 12 on the collector side), which are bonded to a first surface and a second surface of the semiconductor element 13 respectively, separated by Sn-based solders 15 and 16. In this semiconductor device, a Ni-based plating layer 17 is formed on the surfaces of the first conductor and the second conductor opposite to the Sn-based solders 15 and 16, and on the first surface and the second surface of the semiconductor element 13. An interface reaction suppression layer 8 composed of (Cu, Ni)6Sn5 and having a thickness of 1.2 to 4.0 μm is formed at the interface between the Ni-based plating layer 17 and the Sn-based solders 15 and 16. As a result, the degradation of the interface at the solder joint can be suppressed, and the breakage of the semiconductor element can be prevented.

[0077] (2) The method for manufacturing a semiconductor device involves forming a Ni plating layer 17 on the collector-side lead frame 12, supplying a Sn-Ag-Cu based solder with a Cu content of 1.5 mass% or more, incorporating a Cu component 20, to the Ni plating layer 17 to bond a semiconductor element 13, supplying a Sn-Cu based solder with a Cu content of 1.5 mass% or more to the semiconductor element 13, and bonding the emitter-side lead frame 11, on which a Cu plating layer has been applied, to the Ni plating layer 17. This method suppresses the degradation of the interface at the solder joint and prevents the semiconductor element from cracking.

[0078] (3) The semiconductor device is manufactured by forming a Ni plating layer 17 on the collector-side lead frame 12, forming a Cu plating layer on the Ni plating layer 17, supplying a Sn-Ag-Cu based solder with a Cu content of 1.5 mass% or more onto the Cu plating layer to bond the semiconductor element 13, supplying a Sn-Cu based solder with a Cu content of 1.5 mass% or more onto the semiconductor element 13, and bonding the emitter-side lead frame 11 on which the Cu plating layer is applied on the Ni plating layer 17. This suppresses the degradation of the interface at the solder joint and prevents the semiconductor element from cracking.

[0079] This invention is not limited to the embodiments described above. Other methods that can be considered within the scope of the technical concept of this invention, as long as they do not impair the characteristics of this invention, are also included within the scope of this invention. Additionally, it may be a combination of the structures described above.

[0080] Symbol Explanation

[0081] 1…Sn-based solder, 2…Conductor (Cu), 3…Ni plating, 4…Ni-Sn compound, 5…Cu-Sn compound, 6…Void, 7…Semiconductor element fracture, 8…Interface reaction suppression layer, 11…Emitter-side lead frame, 12…Collector-side lead frame, 13…Semiconductor element, 14…Sn-based solder on the emitter side, 15…Sn-based solder on the collector side, 16…Roughened Ni plating, 17…Ni plating, 18…Ni-P plating, 19…Molding resin, 20…Cu component, 21…(Cu,Ni)6Sn5 compound, 22…Al electrode, 30…Solder joint on the emitter side, 31…Solder joint on the collector side.

Claims

1. A semiconductor device comprising: a semiconductor element; a first conductor joined to a first face of the semiconductor element via a Sn-Cu based solder; and a second conductor joined to a second face of the semiconductor element via a Sn-Ag-Cu based solder, the semiconductor device being characterized in that: a Ni based plating layer is formed on a face of the first conductor opposite to the Sn-Cu based solder, a face of the second conductor opposite to the Sn-Ag-Cu based solder, and the first face and the second face of the semiconductor element, respectively, an interface reaction suppressing layer composed of (Cu, Ni)6Sn5 having a layer thickness of 1.2 to 4.0 μm is formed on an interface of the Ni based plating layer and the Sn-Cu based solder, and an interface of the Ni based plating layer and the Sn-Ag-Cu based solder, respectively, the first conductor is an emitter side conductor, the second conductor is a collector side conductor, a solder joint of the emitter side is thicker than a solder joint of the collector side, the solder joint of the emitter side is composed of the Sn-Cu based solder and the interface reaction suppressing layer between the emitter side conductor and the first face of the semiconductor element, and the solder joint of the collector side is composed of the Sn-Ag-Cu based solder and the interface reaction suppressing layer between the collector side conductor and the second face of the semiconductor element.

2. The semiconductor device according to claim 1, characterized in that: the layer thickness of the interface reaction suppressing layer is 1.4 to 3.2 μm.

3. The semiconductor device according to claim 1, characterized in that: a Cu member is incorporated in at least one of the Sn-Cu based solder and the Sn-Ag-Cu based solder.

4. The semiconductor device according to claim 1, characterized in that: the thickness of the solder joint of the emitter side is 120 to 200 μm, and the thickness of the solder joint of the collector side is 70 to 100 μm.

5. The semiconductor device according to claim 1, characterized in that: the Cu content of the Sn-Cu based solder of the emitter side is 2 mass% or more, and Ag is not contained.

6. The semiconductor device according to claim 1, characterized in that: the Cu content of the Sn-Ag-Cu based solder of the collector side is 2 mass% or more, and Ag is contained at 2 to 4 mass%.

7. A method of manufacturing a semiconductor device, characterized by: forming a Ni plating layer on a collector side lead frame, supplying a Sn-Ag-Cu based solder having a Cu content of 1.5 mass% or more with a Cu member incorporated to the Ni plating layer to join a semiconductor element, and supplying a Sn-Cu based solder having a Cu content of 1.5 mass% or more to the semiconductor element to join an emitter side lead frame on which a Cu plating layer is implemented.

8. A method of manufacturing a semiconductor device, characterized by: forming a Ni plating layer on a collector side lead frame, forming a Cu plating layer on the Ni plating layer, and ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A Sn-Ag-Cu solder having a Cu content of 1.5 mass% or more is supplied to the Cu plating layer to join the semiconductor element, A Sn-Cu solder having a Cu content of 1.5 mass% or more is supplied to the semiconductor element, and the lead frame whose emitter side on which the Cu plating layer is formed is joined.

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