Memory system

Abstract

An embodiment of the present application provides a memory system capable of appropriately controlling access to a nonvolatile memory. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes at least a memory chip. The controller is electrically connected to the nonvolatile memory, and in a case where a sequence including a first instruction and a second instruction is sent to the nonvolatile memory, the first instruction is sent to the nonvolatile memory when the nonvolatile memory satisfies a condition, the second instruction is sent to the nonvolatile memory after a first period elapses, the first instruction is sent to the nonvolatile memory in a case where the nonvolatile memory does not satisfy the condition, and the second instruction is sent to the nonvolatile memory after a second period different from the first period elapses.

Description

[0001] This application claims priority to Japanese Patent Application No. 2021-129985 (Filing date: August 6, 2021). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present embodiment relates to a memory system. BACKGROUND

[0003] In a memory system including a memory controller and a nonvolatile memory, sometimes the nonvolatile memory includes an interface chip. The time required for the memory controller to access the nonvolatile memory varies depending on whether the nonvolatile memory includes the interface chip. SUMMARY

[0004] An object of one embodiment of the present application is to provide a memory system capable of appropriately controlling access to a nonvolatile memory.

[0005] According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes at least a memory chip. The controller is electrically connected to the nonvolatile memory. In a case where a sequence including a first instruction and a second instruction is sent to the nonvolatile memory, the first instruction is sent to the nonvolatile memory when the nonvolatile memory satisfies a condition, the second instruction is sent to the nonvolatile memory after a first period elapses, the first instruction is sent to the nonvolatile memory in a case where the nonvolatile memory does not satisfy the condition, and the second instruction is sent to the nonvolatile memory after a second period different from the first period elapses. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 FIG. 1 is a diagram showing one example of the configuration of a memory system to which the present embodiment relates.

[0007] Figure 2A FIG. 2 is a diagram showing one example of the configuration of a NAND package including an interface chip to which the present embodiment relates.

[0008] Figure 2B FIG. 3 is a diagram showing one example of the configuration of a NAND package not including an interface chip to which the present embodiment relates.

[0009] Figure 3 FIG. 4 is a diagram showing one example of the configuration of a memory chip to which the present embodiment relates.

[0010] Figure 4 FIG. 5 is a diagram showing one example of the configuration of a memory cell array to which the present embodiment relates.

[0011] Figure 5is a timing chart showing one example of signals transmitted and received between the NAND controller and the NAND package at the time of the read operation of the present embodiment.

[0012] Figure 6 is a flowchart showing steps of the process of acquiring the state of the NAND package, to which the present embodiment is directed.

[0013] Figure 7 is a flowchart showing steps of the data output process of the read operation, to which the present embodiment is directed.

[0014] Figure 8 is a flowchart showing steps of the generation process of the command information, to which the present embodiment is directed.

[0015] Figure 9 is a flowchart showing steps of the data output process of the read operation, to which the present embodiment is directed.

[0016] Figure 10 is a timing chart of the state read, to which the present embodiment is directed.

[0017] Figure 11 is a timing chart showing one example of signals transmitted and received between the NAND controller and the NAND package at the time of the read operation of the present embodiment.

[0018] Figure 12 is a timing chart showing one example of signals transmitted and received between the NAND controller and the NAND package at the time of the write operation of the present embodiment.

[0019] Explanation of Reference Numerals

[0020] 1 memory system, 2 host, 10 memory controller, 11 CPU, 12 host I / F controller, 13 RAM, 14 NAND controller, 20 NAND memory, 21 NAND package, 141 register, 142 command sequencer, 143 timer, 144 NAND I / F. DETAILED DESCRIPTION

[0021] The memory system to which the present embodiment is directed will be described in detail below with reference to the accompanying drawings. The constituent elements in the following embodiments include those that can be easily conceived by those skilled in the art or substantially the same ones. The present application is not limited by this embodiment.

[0022] (Example of Configuration of Memory System)

[0023] Figure 1 is a diagram showing one example of the configuration of the memory system 1 to which the present embodiment is directed. As shown in the diagram, the memory system 1 includes a host 2, a memory controller 10, and a NAND memory 20. Figure 1As shown, the memory system 1 is provided with a memory controller 10 and a NAND-type flash memory 20 (hereinafter referred to as "NAND memory 20"). The memory system 1 is connectable with a host 2.

[0024] The NAND memory 20 is a nonvolatile memory. The NAND memory 20 has a plurality of NAND packages 21. Each NAND package 21 is provided with a plurality of memory chips. Here, in Figure 2A and Figure 2B , an example of the NAND package 21 is shown. In one example, as shown in Figure 2A , the NAND package 21 includes a plurality of memory chips 100 and an interface chip 211. In other examples, as shown in Figure 2B , the NAND package 21 does not include the interface chip 211 but includes a plurality of memory chips 100.

[0025] The interface chip 211 is connected between the memory controller 10 and several memory chips 100. The interface chip 211 is capable of performing various commands (including a read command, a write command, an erase command described later) for the memory chips 100 which are the control objects of the memory controller 10 and relaying of transfer data. In addition, the interface chip 211 has a cache inside, in which various commands and transfer data and the like are held.

[0026] Returning to Figure 1 . In the memory system 1, the number of the NAND packages 21 which the NAND memory 20 has is arbitrary. In addition, the number of the memory chips 100 which the NAND package 21 has is arbitrary.

[0027] The kind of the nonvolatile memory which the memory system 1 has is not limited to the NAND-type flash memory. The memory system 1 can be provided with, for example, other kinds of memories such as MRAM (Magnetoresistive Random Access Memory), PCRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory) instead of the NAND-type flash memory.

[0028] The memory controller 10 can be configured as an SoC (System on a Chip), for example. The memory controller 10 can also be configured by two or more chips. The memory controller 10 can also be configured by an IC (Integrated Circuit) such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). The memory controller 10 is electrically connected to the NAND memory 20. The memory controller 10 can command various actions to the NAND memory 20. The memory controller 10 performs actions based on a request from the host 2 and actions that are not directly dependent on a request from the host 2. Each function of the memory controller 10 can be implemented by a CPU (Central Processing Unit) that executes a program or by dedicated hardware.

[0029] The memory controller 10 includes a CPU 11, a host interface (I / F) controller 12, a RAM 13, a plurality of NAND controllers 14, and a ROM 15.

[0030] The CPU 11 controls the overall operation of the memory controller 10. The CPU 11 receives and interprets various requests from the host 2, updates and maintains a mapping between a logical address and a physical address, generates various commands, and the like based on firmware, thereby implementing data transfer between the host 2 and the NAND memory 20.

[0031] The RAM 13 is a storage area used as a work area of the CPU 11. In the RAM 13, for example, parameters for managing the NAND memory 20, various management tables, and the like are stored. The RAM 13 stores a waiting queue (command queue) of requests received from the host 2, for example. In addition, the RAM 13 stores a logical-physical address conversion table for converting a logical address associated with data stored in the NAND memory 20 to a physical address of the NAND memory 20. This logical-physical address conversion table is stored in the NAND memory 20, for example, and is read out at the start of the memory system 1 and stored in the RAM 13. The RAM 13 can be configured by an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), or a combination of these. The configuration of the RAM 13 is not limited to this.

[0032] The host I / F controller 12 is connected to the host 2, and manages communication between the memory system 1 and the host 2. The host I / F controller 12 controls, for example, transfer of data, requests, and addresses between the memory system 1 and the host 2. The communication standard supported by the host I / F controller 12 can also be any standard. The host I / F controller 12 supports, for example, communication interface standards of SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), PCIe (PCI Express), NVMe (Non-Volatile Memory Express) (registered trademark), and the like. That is, the host 2 connected to the memory system 1 is, for example, a computer or the like that complies with SATA, SAS, PCIe, NVMe, and the like.

[0033] The plurality of NAND controllers 14 are respectively connected to the different NAND packages 21 via different channels Ch.0 to Ch.3. Each channel Ch.0 to Ch.3 is configured of a wiring group including an IO (input output) signal line and a control signal line. The IO signal line is, for example, a signal line for transmitting and receiving data, addresses, and commands. The control signal line is, for example, a signal line for transmitting and receiving a control signal that controls the NAND memory 20.

[0034] Each channel includes a chip enable signal line CEn, a command latch enable signal line CLE, an address latch enable signal line ALE, a write enable signal line WEn, a pair of read enable signal lines RE / REn, a pair of data strobe signal lines DQS / DQSn, and an IO (input output) signal line DQ.

[0035] The chip enable signal line CEn is a signal line used for transfer of a chip enable signal CEn. The chip enable signal CEn is a signal for bringing a memory chip 100 that is an access target to an enabled state. In a case where the NAND package 21 includes a plurality of memory chips 100, each channel can also include a plurality of chip enable signals CEn.

[0036] The IO signal line DQ is a signal line used for transfer of a signal DQ. The signal DQ is a command, an address, or data. The IO signal line DQ has, for example, a bit width of 8 bits. The bit width of the IO signal line DQ is not limited thereto.

[0037] The command latch enable signal line CLE is a signal line used for transfer of the command latch enable signal CLE. The command latch enable signal CLE indicates that the signal DQ transferred in the IO signal line DQ is a command. The NAND controller 14 transfers the command latch enable signal CLE when a command is transferred as the signal DQ.

[0038] The address latch enable signal line ALE is a signal line used for transfer of the address latch enable signal ALE. The address latch enable signal ALE indicates that the signal DQ transferred in the IO signal line DQ is an address. The NAND controller 14 transfers the address latch enable signal ALE when an address is transferred as the signal DQ.

[0039] The write enable signal line WEn is a signal line that transfers the write enable signal WEn. The write enable signal WEn is a timing signal that indicates the timing of taking in a command or an address transferred as the signal DQ. Thus, the command and the address are transferred in synchronization with the write enable signal WEn. The NAND controller 14 transfers the write enable signal WEn when a command or an address is transferred as the signal DQ.

[0040] The pair of read enable signal lines RE / REn is a pair of signal lines used for transfer of the pair of read enable signals RE / REn. The pair of read enable signals RE / REn is constituted as a differential signal. The pair of read enable signals RE / REn is a timing signal used by the NAND controller 14 in order to indicate the output timing of data to the memory chip 100 included in the NAND package 21.

[0041] The pair of data strobe signal lines DQS / DQSn is a pair of signal lines that transfer the pair of strobe signals DQS / DQSn. The pair of strobe signals DQS / DQSn is constituted as a differential signal. The pair of strobe signals DQS / DQSn is a timing signal that indicates the timing of taking in data to the transfer destination at the time of data transfer. At the time of write operation, the NAND controller 14 transmits the pair of strobe signals DQS / DQSn. That is, at the time of write operation, data is transferred in synchronization with the pair of strobe signals DQS / DQSn transmitted by the NAND controller 14.

[0042] The plurality of NAND controllers 14 respectively control different channels Ch.0 to Ch.3. In addition, the plurality of NAND controllers 14 respectively cause each memory chip 100 in the corresponding NAND package 21 to execute a command indicated by the CPU 11.

[0043] Each of the NAND controllers 14 has a register 141, a command sequencer 142, a timer 143, and a NAND I / F 144. The register 141 stores an operation time associated with various operations of the memory system 1. The register 141 stores, for example, information on an operation time of the memory chip 100. The information on the operation time of the memory chip 100 is, for example, a design value determined as an AC (alternating current) specification. The AC specification is a timing constraint determined in advance in order to satisfy a timing relationship among a plurality of signals or a timing relationship between an assertion and a negation of a certain signal.

[0044] The command sequencer 142 sends a command set and various control signals to the NAND package 21 in accordance with command information generated by the CPU 11. Here, the command information contains an operation content of the NAND package 21. The command sequencer 142 sends the command set and the various control signals by executing a sequencer code stored in the NAND controller 14.

[0045] The timer 143 measures an operation time associated with various operations of the memory system 1. The timer 143 measures, for example, information on an operation time of the memory chip 100. The NAND controller 14 can have a plurality of timers 143.

[0046] The NAND I / F 144 connects the NAND controller 14 and the NAND package 21 and manages communication between the NAND controller 14 and the NAND package 21. The NAND I / F 144 is configured based on a NAND interface standard.

[0047] The ROM 15 holds firmware and various information and the like.

[0048] Figure 3 is a diagram showing a configuration example of each of the memory chips 100 of the present embodiment.

[0049] The memory chip 100 has an IO signal processing circuit 101, a control signal processing circuit 102, a control circuit 103, a command register 104, an address register 105, a status register 106, a voltage generating circuit 107, a RyBy generating circuit 108, a column buffer 109, a column decoder 110, a data register 111, a sense amplifier 112, a memory cell array 113, a row address buffer decoder 114, and a row address decoder 115.

[0050] In addition, the memory chip 100 has a Vcc terminal to which power is input from a not-illustrated power IC (integrated circuit) provided in the memory system 1, and a Vss terminal to which a ground potential is connected. The power input to the Vcc terminal is supplied to each circuit within the memory chip 100.

[0051] The control signal processing circuit 102 receives a control signal, judges which of a command, an address, and data the IO signal DQ transmitted to the IO signal processing circuit 101 is, based on the received control signal, and notifies the IO signal processing circuit 101 of the result of the judgment. In addition, the control signal processing circuit 102 relays the received control signal to the control circuit 103.

[0052] The IO signal processing circuit 101 is a buffer circuit for transmitting and receiving the IO signal DQ[7:0] with the memory controller 10. The IO signal processing circuit 101 can take in a command or an address transmitted as the IO signal DQ[7:0] based on a write enable signal WEn. The IO signal processing circuit 101 can take in data transmitted as the IO signal DQ[7:0] based on a pair of DQS / DQSn. The IO signal processing circuit 101 saves the command, the address, and the data transmitted as the IO signal DQ[7:0] in the command register 104, the address register 105, and the data register 111, respectively.

[0053] The address saved in the address register 105 includes a row address and a column address. The row address is transmitted to the row address buffer decoder 114, and the column address is transmitted to the column buffer 109.

[0054] The control circuit 103 is a state transition circuit (state machine) whose state transitions based on various control signals received via the control signal processing circuit 102. The control circuit 103 controls the operation of the entire memory chip 100 based on the various control signals and the command saved in the command register 104.

[0055] In addition, the control circuit 103 generates state information indicating a state of operation control or a result of operation control, and saves the state information in the state register 106. The control circuit 103 can output the state information saved in the state register 106 via the IO signal processing circuit 101 in accordance with a state read command from the memory controller 10.

[0056] The RyBy generation circuit 108 transitions the state of the ready / busy signal RyBy between a ready state (Ry) and a busy state (By) under the control of the control circuit 103.

[0057] The memory cell array 113 has a structure in which a plurality of memory cell transistors are arranged. Each of the plurality of memory cell transistors is connected to a bit line BL and a word line WL. In the memory cell array 113, for example, data received from the host 2 is stored.

[0058] The voltage generation circuit 107 generates various voltages required for access (write processing, read processing, and erase processing) to the memory cell array 113, based on power input to the Vcc terminal. Also, the voltage generation circuit 107 supplies the generated voltages to the sense amplifier 112, the memory cell array 113, and the row address decoder 115, respectively.

[0059] The row address decoder 115 and the column decoder 110, the sense amplifier 112 perform access (write processing, read processing, and erase processing) to the memory cell array 113, based on control by the control circuit 103.

[0060] In the write processing, data sent from the NAND controller 14 as an IO signal DQ[7:0] is stored in the data register 111. The storage processing of data into the data register 111 is referred to as data input processing. The data stored in the data register 111 is stored in the memory cell transistor of the memory cell array 113 through the program processing.

[0061] In the program processing, the column decoder 110 selects a bit line BL corresponding to the column address stored in the column buffer 109. The control circuit 103 makes the voltage of the selected bit line zero. The row address decoder 115 selects a word line corresponding to the row address stored in the row address buffer decoder 114, and applies a pulse of a high voltage generated by the voltage generation circuit 107 to the selected word line. As a result, electrons are injected into the charge accumulation layer of the memory cell transistor located at the intersection of the selected bit line and the selected word line, and as a result, the threshold voltage of the memory cell transistor rises. The control circuit 103 causes the row address decoder 115 to continue the application of the pulse until the threshold voltage of the memory cell transistor reaches the target threshold voltage corresponding to the data stored in the data register 111.

[0062] During the read processing, the sense amplifier 112 precharges the bit line BL with the voltage Vcc. The row address decoder 115 selects the word line corresponding to the row address held in the row address buffer decoder 114. The row address decoder 115 brings each memory cell transistor connected to the non-selected word line into the on state by applying the predetermined voltage Vread generated by the voltage generation circuit 107 to the word line. Also, the row address decoder 115 applies to the selected word line in order the plurality of kinds of voltages corresponding to the kind of the page of the read target generated by the voltage generation circuit 107. The sense amplifier 112 determines the voltage that causes the flow of the electric charge accumulated in the memory cell transistor by the precharge to the source line, thereby determining the threshold voltage of the memory cell transistor of the target, and obtains the data corresponding to the determined threshold voltage. The sense amplifier 112 holds the obtained data in the data register 111. The processing of obtaining the data from the memory cell array 113 by the sense amplifier 112 and holding the data in the data register 111 is described as sensing processing. The data held in the data register 111 by the sensing processing is transmitted to the IO signal processing circuit 101 through the data line, and is forwarded from the IO signal processing circuit 101 to the NAND controller 14. The processing of forwarding the data held in the data register 111 to the NAND controller 14 is described as data output processing.

[0063] (Example of configuration of memory cell array)

[0064] Figure 4 is a diagram showing one example of the configuration of the memory cell array 113 to which the present embodiment is applied. Figure 4 shows the detailed circuit structure with respect to one block BLK in the memory cell array 113. As shown in Figure 4 , the block BLK has, for example, a plurality of string units SU (SU0 to SU3). In Figure 4 the example, the block BLK includes four string units SU0 to SU3, but the number thereof is arbitrary.

[0065] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer of one or more). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. The number of memory cell transistors MT and selection transistors ST included in one NAND string NS is arbitrary.

[0066] The memory cell transistor MT, for example, has a control gate and a charge storage layer to store data in a non-volatile manner. The memory cell transistors MT0 to MT7 of the NAND string NS are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. The control gate of the memory cell transistor MT0 of each NAND string NS included in the same BLK is connected to the word line WL0. Similarly, the control gates of the memory cell transistors MT1 to MT7 of multiple NAND strings NS included in the same BLK are respectively connected to the word lines WL1 to WL7.

[0067] Furthermore, in the following explanation, multiple memory cell transistors MT connected to a common word line WL within each string unit SU will be referred to as a cell unit CU. Additionally, the collection of 1-bit data stored by each memory cell transistor MT within a cell unit CU is called a page. Therefore, when one memory cell transistor stores 1 bit of data, the cell unit CU stores 1 page of data. Conversely, when one memory cell transistor stores 2 bits of data, the cell unit CU stores 2 pages of data.

[0068] Select transistors ST1 and ST2 are used to select the serial cell SU during various operations such as read and write. The drains of the select transistors ST1 included in the NAND string NS corresponding to the same column address are connected to the corresponding bit line BL. The gates of the multiple select transistors ST1 included in the serial cell SU0 are connected to the select gate line SGD0. Similarly, the gates of the multiple select transistors ST1 included in the serial cells SU1 to SU3 are connected to the select gate lines SGD1 to SGD3 respectively. In the same BLK, the sources of multiple select transistors ST2 are connected to a source line SL. The gates of multiple select transistors ST2 are connected to a select gate line SGS.

[0069] In this circuit structure of the memory cell array 113, word lines WL0 to WL7 are set according to each BLK block. Bit lines BL0 to BLm are shared among multiple BLK blocks. Source line SL is shared among multiple BLK blocks. Furthermore, the number of word lines WL and select gate lines SGD and SGS varies based on the number of memory cell transistors MT and select transistors ST1 and ST2.

[0070] Figure 5This is a timing diagram illustrating an example of the signals transmitted and received between the NAND controller 14 and the NAND package 21 during a read operation according to this embodiment. Furthermore, this diagram depicts the states of each of the signal lines constituting the channel connecting the NAND controller 14 and the NAND package 21: the chip enable signal line CEn, the command latch enable signal line CLE, the address latch enable signal line ALE, the write enable signal line WEn, a pair of read enable signal lines RE / REn, a pair of strobe signals DQS / DQSn, the IO signal lines DQ[7:0], and the ready / busy signal line RyBy.

[0071] Figure 5 This is a timing diagram of the data output processing during the read operation. Data output processing is the process of transferring part or all of the data read from the memory cell array 113 and stored in the data register 111 through prior sensing processing from the memory chip 100 to the NAND controller 14. In order for the memory chip 100 to perform data output processing, the NAND controller 14 sends the data output command C0, address information ADD, and preparation command C1 in this order via the IO signal lines DQ[7:0]. The set of data output command C0, address information ADD, and preparation command C1 is recorded as the data output command set.

[0072] When sending a data output command set, the NAND controller 14 keeps the chip enable signal CEn active (low level). When sending data output command C0 and preparation command C1, the NAND controller 14 keeps the command latch enable signal CLE active (high level). When sending address information ADD, the NAND controller 14 keeps the address latch enable signal ALE active (high level). When sending a data output command set, the NAND controller 14 triggers the write enable signal WEn.

[0073] The data output command C0 is a command that instructs data output processing. The address information ADD includes column and row addresses. The column address indicates the beginning position of the data in the object being processed. The row address uses the same value as the row address specified during sensing processing.

[0074] The preparation command C1 is a command that instructs the preparation of data output processing. According to the preparation command C1, the memory chip 100 prepares the output of the first 8 bits of data (header data) in the object data of the data output processing specified by the column address.

[0075] The NAND controller 14 elapses a time t, which is determined as a timing constraint, from the time the prepare command C1 is sent (more precisely, from the time the write enable signal WEn corresponding to the sending of the prepare command C1 is triggered). WHR2At this time, the triggering of a pair of read enable signals RE / REn begins. The read preparation command C1, triggered by the write enable signal WEn, and the data output timing indication, triggered by the pair of read enable signals RE / REn, form a series of sequences.

[0076] The memory chip 100 generates a pair of strobe signals DQS / DQSn by delaying a pair of read enable signals RE / REn. The memory chip 100 outputs the generated pair of strobe signals DQS / DQSn. The memory chip 100 outputs data of the data output object, which begins at the position specified by the column address, to the IO signal lines DQ[7:0] synchronously with the pair of strobe signals DQS / DQSn. The NAND controller 14 fetches the data output from the NAND package 21 at a timing synchronized with the pair of strobe signals DQS / DQSn. Thus, the data of the object to be processed for data output is transferred from the memory chip 100 to the NAND controller 14. That is, data output processing is performed.

[0077] like Figure 2A and Figure 2B As shown, the NAND package 21 has a package including an interface chip 211 and a package not including an interface chip 211. When the NAND controller 14 accesses the NAND package 21 including the interface chip 211 and when it accesses the NAND package 21 not including the interface chip 211, the time from sending the preparation command C1 to being able to start triggering a pair of read enable signals RE / REn is different.

[0078] Specifically, when the NAND package 21 includes an interface chip 211, after the memory controller 10 sends the preparation command C1, the control circuit 103 of the memory chip 100 sends the header data from the data stored in the data register 111 to the interface chip 211 via the I / O signal processing circuit 101. On the other hand, when the NAND package 21 does not include an interface chip 211, after the memory controller 10 sends the preparation command C1, the control circuit 103 of the memory chip 100 sends the header data from the data stored in the data register 111 to the I / O signal processing circuit 101.

[0079] Thus, when the NAND package 21 includes the interface chip 211, it is necessary to send the header data to the interface chip 211. Compared with the NAND package 21 that does not include the interface chip 211, the preparation time for the output of the read object data will take longer.

[0080] Therefore, when time t is taken independently of whether the NAND package 21 includes the interface chip 211 WHR2When a certain time is set, that is, a long time corresponding to the case where the NAND package 21 includes the interface chip 211, a waiting time exceeding the necessary will occur when the memory controller 10 accesses the NAND package 21 which does not include the interface chip 211.

[0081] Therefore, in the memory system 1 according to this embodiment, the timing constraint varies depending on whether the NAND package 21 includes an interface chip 211.

[0082] In the memory system 1 of this embodiment, register 141 stores design values ​​related to different timing constraints, corresponding to whether the NAND package 21 includes an interface chip 211. Command sequencer 142, by executing sequencer code, sends command sets and various control signals to the NAND package 21 based on command information from the CPU 11. Command sequencer 142 uses the timing constraint-related design values ​​stored in register 141 for timing control between multiple indications in the transmission of command sets and various control signals.

[0083] The memory system 1 stores the NAND package 21, including the interface chip 211, for a time t. WHR2 Time t when NAND package 21 does not include interface chip 211 WHR2 This is used as the design value stored in register 141. The time t in the NAND package 21 excluding the interface chip 211. WHR2 Time t when NAND package 21 includes interface chip 211 WHR2 Short. Therefore, when the memory controller 10 accesses the NAND package 21 excluding the interface chip 211, it can avoid the unnecessary waiting time.

[0084] Consider the following scenario: the NAND controller 14 pre-stores different sequencer codes for NAND package 21 including interface chip 211 and NAND package 21 excluding interface chip 211, and instructs sequencer 142 to switch between these sequencer codes for execution. In this case, the number of sequencer codes managed by memory system 1 increases, leading to increased management costs. By instructing sequencer 142 to execute sequencer codes, the system references design values ​​stored in register 141 and performs timing control between multiple instructions based on these design values, thereby preventing an increase in the management costs of sequencer codes.

[0085] (An example of control processing in a memory system)

[0086] Here, use Figure 6 and Figure 7An example of control processing in the memory system 1 of this embodiment will be described. Figure 6 This is a flowchart illustrating the steps of the NAND controller 14 in obtaining information related to whether the NAND package 21 includes an interface chip 211.

[0087] When the NAND controller 14 receives a command message from the CPU 11 requesting whether the NAND package 21 includes the interface chip 211, it sends the command to the NAND package 21 (step S1). The CPU 11 obtains information indicating whether the NAND package 21 includes the interface chip 211 as a response to the request command and stores the information in register 141 (step S2).

[0088] Next, use Figure 7 The steps for data output processing of the read action involved in this embodiment will be explained.

[0089] The command sequencer 142 of the NAND controller 14 retrieves a timer setting value from register 141 based on information indicating whether the NAND package 21 includes the interface chip 211 (step S11). For example, if the NAND package 21 to which the command is executed includes the interface chip 211, the time t for the case where the interface chip 211 is included is retrieved. WHR2 Used as the timer setting value.

[0090] Thus, when the first condition that the NAND package 21 of the command execution object includes the interface chip 211 is met, the command sequencer 142 obtains the time t when the interface chip 211 is included. WHR2 This is used as the timer setting value. Additionally, if the second condition is met—that the NAND package 21 of the command execution object does not include the interface chip 211—the command sequencer 142 obtains the time t when the interface chip 211 is not included. WHR2 Used as the timer setting value.

[0091] Command sequencer 142 sends data output command C0 (step S12). Command sequencer 142 sends address information ADD (step S13). Command sequencer 142 sends preparation command C1 (step S14). Command sequencer 142 sets the timer setting value obtained in step S11 onto timer 143 (step S15). Command sequencer 142 refers to timer 143 to determine whether time t has elapsed. WHR2 (Step S16). After time t... WHR2 In the case of (step S16: Yes), the sequencer 142 is commanded to begin triggering a pair of read enable signals RE / REn (step S17).

[0092] In the above embodiment, the command sequencer 142 of the NAND controller 14 measures the time based on information indicating the state of the NAND package 21 after sending the preparation command C1. The command sequencer 142 measures different times depending on whether the NAND package 21 includes the interface chip 211 or not. Thus, the command sequencer 142 starts triggering a pair of read enable signals RE / REn after different time intervals depending on whether the NAND package 21 includes the interface chip 211 or not.

[0093] In this way, the NAND controller 14 controls the timing of a specific instruction in a series of multiple instructions based on the state of the NAND package 21, thereby enabling appropriate control of the memory chip 100 based on the configuration of the NAND package 21.

[0094] Register 141 stores information indicating whether the NAND package 21 includes an interface chip 211. The command sequencer 142 of the NAND controller 14 refers to register 141 and sets the timer setting value to timer 143. Thus, by referring to the information indicating whether the NAND package 21 includes an interface chip 211, the command sequencer 142 can appropriately control the memory chip 100 based on the configuration of the NAND package 21.

[0095] Additionally, the NAND controller 14 performs actions such as Figure 5 Before the data output processing shown, a process for obtaining the state of the NAND package 21 is performed. Therefore, the NAND controller 14 can determine whether the NAND package 21 includes the interface chip 211 while executing a sequence of data output processing, and can appropriately control the memory chip 100 based on the configuration of the NAND package 21.

[0096] Additionally, in the NAND controller 14, register 141 stores the time t in the case of interface chip 211. WHR2 And the time t without the interface chip 211 WHR2 The command sequencer 142 obtains the time t, including the interface chip 211, via the reference register 141. WHR2 Or time t excluding interface chip 211 WHR2 Thus, the command sequencer 142 obtains the time t stored in register 141. WHR2 Therefore, there is no need to prepare multiple sequencer codes, which can prevent the increase in the management cost of sequencer codes.

[0097] (Modified Example)

[0098] In the above embodiment, the process of obtaining information indicating whether the NAND package 21 includes the interface chip 211 is described as performed by the memory controller 10 (more specifically, the command sequencer 142 of the NAND controller 14). However, it is also possible that when manufacturing the memory system 1, the manufacturer of the memory system 1 stores the information indicating whether the NAND package 21 includes the interface chip 211 in the register 141 or the ROM 15.

[0099] In this case, the memory controller 10 does not perform the process of obtaining information indicating whether the NAND package 21 includes the interface chip 211, but can control the memory chip 100 at appropriate timing based on information indicating the state of the NAND package 21.

[0100] In the above embodiment, the case where the memory controller 10 sends a command to the NAND package 21 to query information indicating whether the NAND package 21 includes the interface chip 211, and stores the result in the register 141, has been described. However, it is also possible that the CPU 11 includes the information indicating whether the NAND package 21 to be targeted includes the interface chip 211 in the command information.

[0101] Here, use Figure 8 The steps for generating and processing command information are explained. Figure 8 This is a flowchart illustrating the steps involved in generating command information. Here, it is assumed that a mapping table relating information indicating whether the NAND package 21 includes an interface chip 211 and the physical address of the NAND package 21 is stored in the ROM 15 of the memory controller 10. Additionally, it is assumed that a logical-physical address translation table relating logical addresses and physical addresses is stored in RAM 13 (step S21).

[0102] Furthermore, when sending command information to the NAND controller 14, the CPU 11 refers to the RAM 13 to obtain the physical address of the NAND package 21 corresponding to the logical address of the action object. In order to execute the command based on the command information, the CPU 11 determines whether the NAND package 21 includes the interface chip 211 based on the physical address stored in the ROM 15. The CPU 11 then generates command information containing information indicating whether the NAND package 21 includes the interface chip 211 and sends the generated command information to the NAND controller 14 (step S22).

[0103] The processing steps of the NAND controller 14 in this case are shown in Figure 9 . Figure 9 This is a flowchart illustrating the data output processing steps involved in the read action in this variation.

[0104] The command sequencer 142 of the NAND controller 14, based on the command information of the data output command set generated by the CPU 11, obtains the timer setting value corresponding to the information indicating whether the NAND package 21 includes the interface chip 211 from the register 141 (step S31). The command sequencer 142 sends the data output command C0 (step S32). The command sequencer 142 sends the address information ADD (step S33). The command sequencer 142 sends the preparation command C1 (step S34). The command sequencer 142 sets the timer setting value obtained in step S31 to the timer 143 (step S35). The command sequencer 142 refers to the timer 143 to determine whether time t has elapsed. WHR2 (Step S36). After time t... WHR2 In the case of (step S36: Yes), the sequencer 142 is commanded to begin triggering a pair of read enable signals RE / REn (step S37).

[0105] As described above, the command information corresponding to the command set includes information indicating whether the NAND package 21 includes the interface chip 211. Therefore, the NAND controller 14 can control the memory chip 100 at appropriate timing based on the configuration of the NAND package 21 without performing the processing of obtaining information indicating whether the NAND package 21 includes the interface chip 211.

[0106] In the example above, the time t for storing data in register 141, including interface chip 211, is... WHR2 And the time t without the interface chip 211 WHR2 The situation has been described. However, it can also be set such that register 141 only stores the time t in the case of interface chip 211. WHR2 And the time t without the interface chip 211 WHR2 Either of the parties.

[0107] In the example above, the time t in data output processing is determined based on whether the NAND package 21 includes an interface chip 211. WHR2 The circumstances under which changes are made are described, but it can also be set to make changes at other times as well.

[0108] For example, it can also be set to the time t for reading the state. RPP Make changes. Figure 10This is a timing diagram illustrating an example of signals transmitted and received between the NAND controller 14 and the NAND package 21 during state reads according to this embodiment. Furthermore, this diagram depicts the states of each signal line in the signal line group constituting the channel connecting the NAND controller 14 and the NAND package 21: the chip enable signal line CEn, the command latch enable signal line CLE, the write enable signal line WEn, the read enable signal REn in a pair of read enable signal lines RE / REn, and the IO signal lines DQ[7:0].

[0109] To read status information from memory chip 100, NAND controller 14 sends a status read command C2 via IO signal lines DQ[7:0]. NAND controller 14 activates the read enable signal REn. Corresponding to the activation of the read enable signal REn, control circuit 103 outputs the status information stored in status register 106 via IO signal processing circuit 101. NAND controller 14 then executes the read enable signal REn for a period of time t. RPP Then, the read enable signal REn is disabled. The NAND controller 14 can also adjust the time t based on whether the NAND package 21 includes an interface chip 211. RPP Make changes.

[0110] The NAND controller 14 acquires status information along with the invalidation of the read enable signal REn. The indication of output status information achieved by activating the read enable signal REn and the indication of acquired status information achieved by deactivating the read enable signal REn form a series of sequences.

[0111] Alternatively, it can be set to time t in the sequence of data output processing. RPST and t RPSTH Make changes. Figure 11 This is a timing diagram illustrating an example of the signals transmitted and received between the NAND controller 14 and the NAND package 21 during a read operation according to this embodiment. Furthermore, this diagram depicts the states of each signal line in the signal line group constituting the channel connecting the NAND controller 14 and the NAND package 21: the chip enable signal line CEn, the pair of read enable signal lines RE / REn, the pair of strobe signals DQS / DQSn, and the IO signal lines DQ[7:0].

[0112] NAND controller 14 triggers a pair of read enable signals RE / REn an amount corresponding to the size of the data being processed for data output. NAND controller 14 then triggers the signal after a time t elapses from the last trigger corresponding to the data size. RPST Then, the chip enable signal line CEn is disabled. The NAND controller 14 can also adjust the time t based on whether the NAND package 21 includes an interface chip 211.RPST Make changes.

[0113] The NAND controller 14 counts the time elapsed since the chip enable signal line CEn became invalid. RPSTH Then, the pair of read enable signals RE / REn are triggered again. The NAND controller 14 can also adjust the time t based on whether the NAND package 21 includes an interface chip 211. RPSTH Make changes.

[0114] The final triggering of the pair of read enable signals RE / REn and the invalidation of the chip enable signal line CEn form a series of sequences. The invalidation of the chip enable signal line CEn and the re-triggering of the pair of read enable signals RE / REn form a series of sequences.

[0115] Alternatively, it can be set to time t in the sequence of data input processing. WPST Make changes. Figure 12 This is a timing diagram illustrating an example of the signals transmitted and received between the NAND controller 14 and the NAND package 21 during a write operation according to this embodiment. Furthermore, this diagram depicts the states of each signal line in the signal line group constituting the channel connecting the NAND controller 14 and the NAND package 21: the chip enable signal line CEn, the pair of strobe signals DQS / DQSn, and the IO signal lines DQ[7:0].

[0116] NAND controller 14 triggers a pair of strobe signals DQS / DQSn an amount corresponding to the size of the data being processed. NAND controller 14 then triggers the signal after a time t elapses from the last trigger corresponding to the data size. WPST Then, the chip enable signal line CEn is disabled. The NAND controller 14 can also adjust the time t based on whether the NAND package 21 includes an interface chip 211. WPST Make changes.

[0117] The final triggering of a pair of strobe signals DQS / DQSn and the invalidation of the chip enable signal line CEn form a series of sequences.

[0118] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A memory system comprising: Non-volatile memory, which includes at least a memory chip; and The controller, which is electrically connected to the non-volatile memory, The controller is configured as follows: In the case of sending a sequence including the first instruction and the second instruction to the non-volatile memory, When the non-volatile memory meets the condition, the first instruction is sent to the non-volatile memory; after the first period has elapsed, the second instruction is sent to the non-volatile memory. When the non-volatile memory does not meet the condition, the first instruction is sent to the non-volatile memory. After a second period different from the first period, the second instruction is sent to the non-volatile memory. The condition is that the non-volatile memory includes an interface chip. The controller determines whether the non-volatile memory includes the interface chip, and based on the determination result, decides on either the first period or the second period.

2. The memory system according to claim 1, The controller stores data indicating whether the conditions are met.

3. The memory system according to claim 2, The controller is configured to: send a third instruction to the non-volatile memory before sending the sequence to the non-volatile memory, and store data indicating whether the condition is met based on the result of sending the third instruction.

4. The memory system according to claim 2, Data indicating whether the conditions are met is generated during manufacturing.

5. The memory system according to claim 4, The controller determines either the first period or the second period based on a mapping table between data indicating whether the condition is met and the physical address of the non-volatile memory.

6. The memory system according to claim 1, The controller and the non-volatile memory are electrically connected via the first signal line. The first indication is either an active or inactive first signal sent from the controller to the non-volatile memory via the first signal line. The second indication is the other of the first signal being valid or invalid.

7. The memory system according to claim 1, The controller and the non-volatile memory are electrically connected via a first signal line and a second signal line. The first indication is the validity of a first signal sent from the controller to the non-volatile memory via the first signal line. The second indication is the validity of a second signal sent from the controller to the non-volatile memory via the second signal line.

8. The memory system according to claim 1, The controller As the first indication, a fetch timing is indicated for the non-volatile memory, the fetch timing being a fetch timing of a command requesting data to be output from the non-volatile memory. As the second indication, the timing for outputting data from the non-volatile memory is indicated.

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