Quantum computer operating system and quantum computer

Abstract

The present invention discloses a quantum computer operating system and a quantum computer. The quantum computer operating system includes a quantum computing task receiving module, a quantum computing task priority processing module, a quantum computing task merging module, a quantum chip resource allocation service module, and a quantum computing task scheduling and mapping module. Among them, the quantum computing task priority processing module divides the quantum computing tasks in the quantum computing task queue into respective priorities according to the depth of the quantum computing tasks, the number of quantum bits required, and the waiting time in the quantum computing task queue. When the quantum chip resources cannot meet the simultaneous execution of all tasks, by preferentially executing the quantum computing tasks with higher priorities, the utilization rate of quantum bits in the quantum chip is improved, and the overall waiting time of the quantum computing tasks in the quantum computing task queue is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing, and more particularly to a quantum computer operating system and a quantum computer. Background Art

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores, and processes quantum information in accordance with the laws of quantum mechanics. The characteristics of quantum computers mainly include relatively fast operating speed, relatively strong information processing ability, and relatively wide application range, etc. Compared with general computers, the more information is processed, the more beneficial it is to perform operations on quantum computers, and the more accurate the operations can be ensured.

[0003] The importance of an operating system to a computer is self-evident, which is true for classical computers and even more so for the still nascent quantum computer technology. The quantum computer operating system determines the functions, computing efficiency, and stability of the quantum computer, and thus determines the practicality of the quantum computer. The quantum computer operating system is a tool for connecting the terminal and the quantum chip, the core component of the quantum computer. On the one hand, the quantum computer operating system receives quantum computing tasks sent by users, and on the other hand, it needs to map these quantum computing tasks to the specific qubit topological structure in the quantum chip to complete the execution of these quantum computing tasks. In the prior art, this solution of the quantum computer operating system greatly limits the utilization rate of qubits in the quantum chip, resulting in a waste of quantum chip resources.

[0004] Therefore, how to improve the utilization rate of qubits in the quantum chip has become an urgent technical problem in this field. Summary of the Invention

[0005] The purpose of the present invention is to provide a quantum computer operating system and a quantum computer, which are used to solve the problem that the quantum computer operating system in the prior art limits the utilization rate of qubits in the quantum chip.

[0006] To solve the above technical problem, the present invention proposes a quantum computer operating system, including:

[0007] A quantum computing task receiving module, which is configured to receive a quantum computing task queue, wherein the quantum computing task queue includes a plurality of quantum computing tasks;

[0008] A quantum computing task priority processing module, which is configured to obtain the respective priorities of each quantum computing task in the quantum computing task queue based on the depth of the quantum computing task, the number of qubits required, and the time already waiting in the quantum computing task queue, wherein the quantum computing task with a higher priority is executed first;

[0009] A quantum computing task merging module, which is configured to merge several quantum computing tasks in the quantum computing task queue into an overall quantum computing task in descending order of priority, and update the quantum computing task queue;

[0010] A quantum chip resource allocation service module, which is configured to obtain a qualified qubit topology from the idle qubits of the quantum chip based on the updated quantum computing task queue by using the community discovery algorithm and the greedy algorithm, where the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks;

[0011] A quantum computing task scheduling and mapping module, which is configured to schedule the quantum computing tasks to be executed based on the updated quantum computing task queue, and map the quantum computing tasks to be executed to the qubit topology in descending order of priority.

[0012] Optionally, the quantum computing task priority processing module includes:

[0013] A quantum computing task status acquisition unit, which is configured to acquire the depth, the required number of qubits, and the waiting time in the quantum computing task queue of each quantum computing task in the quantum computing task queue;

[0014] A quantum computing task priority acquisition unit, which is configured to acquire the priority of each quantum computing task, and the priority of each quantum computing task is R, R = (W + 1) / (n * d), where W is the waiting time of the quantum computing task in the quantum computing task queue, n is the number of qubits required for the quantum computing task, and d is the depth of the quantum computing task.

[0015] Optionally, the compliance includes: the number of qubits in the qubit topology is equal to the number of qubits required for the currently pending quantum computing task, and the tightness of the qubit topology, the read fidelity of all qubits in the qubit topology, the reliability parameter of performing two-qubit quantum logic gates in the qubit topology, and the number of feeders in the qubit topology all meet the preset thresholds.

[0016] Optionally, it further includes:

[0017] A coherence time acquisition and judgment module, which is configured to acquire the coherence time of the idle qubits in the quantum chip, and judge whether the coherence time of each idle qubit is greater than a first threshold, where the first threshold is determined according to the execution time of the currently pending quantum computing task;

[0018] A quantum chip resource discrimination module, which is configured to set the corresponding quantum bits as unavailable quantum bits when the judgment result is no, and the quantum chip resource allocation service module will not divide the unavailable quantum bits into the quantum bit topology.

[0019] Based on the same inventive concept, the present invention also provides a method for processing quantum computing tasks in a quantum computer, including:

[0020] Receiving a quantum computing task queue, where the quantum computing task queue includes multiple quantum computing tasks;

[0021] Based on the depth of the quantum computing task, the number of required quantum bits, and the time already waiting in the quantum computing task queue, obtaining the respective priorities of each quantum computing task in the quantum computing task queue, where the quantum computing task with a higher priority is executed first;

[0022] Combining several quantum computing tasks in the quantum computing task queue into an overall quantum computing task in the order from high to low priority, and updating the quantum computing task queue;

[0023] Based on the updated quantum computing task queue, using the community discovery algorithm and the greedy algorithm to obtain a quantum bit topology that meets the requirements among the idle quantum bits of the quantum chip, where the idle quantum bits are the quantum bits in the quantum chip that have not been assigned quantum computing tasks;

[0024] Based on the updated quantum computing task queue, scheduling the quantum computing tasks to be executed, and mapping the quantum computing tasks to be executed to the quantum bit topology in the order from high to low priority.

[0025] Optionally, the obtaining the respective priorities of each quantum computing task in the quantum computing task queue based on the depth of the quantum computing task, the number of required quantum bits, and the time already waiting in the quantum computing task queue includes:

[0026] Obtaining the depth, the number of required quantum bits, and the time waiting in the quantum computing task queue of each quantum computing task in the quantum computing task queue;

[0027] Obtaining the priority of each quantum computing task, and the priority R of each quantum computing task is R = (W + 1) / (n * d), where W is the time waiting in the quantum computing task queue of the quantum computing task, n is the number of quantum bits required by the quantum computing task, and d is the depth of the quantum computing task.

[0028] Optionally, the compliance requirements include: the number of qubits in the qubit topology is equal to the number of qubits required for the currently pending quantum computing task, and the tightness of the qubit topology, the read fidelity of all qubits in the qubit topology, the reliability parameter for performing two-qubit quantum logic gates in the qubit topology, and the number of feedlines in the qubit topology all meet preset thresholds.

[0029] Optionally, the processing method further includes:

[0030] Obtain the coherence time of the idle qubits in the quantum chip, and determine whether the coherence time of each idle qubit is greater than a first threshold, where the first threshold is determined according to the execution time of the currently pending quantum computing task;

[0031] When the judgment result is negative, set the corresponding qubit as an unavailable qubit, and the quantum chip resource configuration service module will not allocate the unavailable qubit to the qubit topology.

[0032] Based on the same inventive concept, the present invention also provides a quantum computer, including the quantum computer operating system described in any one of the above characteristic descriptions.

[0033] Based on the same inventive concept, the present invention also provides a readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it can implement the processing method described in any one of the above characteristic descriptions.

[0034] Based on the same inventive concept, the present invention also provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the processing method described in any one of the above characteristic descriptions.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The quantum computer operating system proposed by the present invention includes a quantum computing task receiving module, a quantum computing task priority processing module, a quantum computing task merging module, a quantum chip resource allocation service module, and a quantum computing task scheduling and mapping module. Among them, the quantum computing task priority processing module divides the quantum computing tasks in the quantum computing task queue into their respective priorities according to the depth of the quantum computing tasks, the number of required qubits, and the time already waiting in the quantum computing task queue. When the quantum chip resources cannot meet the simultaneous execution of all tasks, by preferentially executing the quantum computing tasks with higher priorities, the utilization rate of qubits in the quantum chip is improved, and the overall waiting time of the quantum computing tasks in the quantum computing task queue is effectively reduced.

[0037] 2. Since the execution timings of two isolated quantum computing tasks are unknown to each other, in the mapping process, to avoid crosstalk, the qubit topologies to which these two quantum computing tasks are mapped will be spaced far enough apart on the quantum chip. In the present application, the quantum computing task merging module can merge several quantum computing tasks into an overall quantum computing task in descending order of priority. Since the timings of the individual quantum computing tasks in the overall quantum computing task are known after merging, therefore, in the mapping process, these timings can be fully utilized, and two quantum computing tasks that originally needed to be mapped separately can be mapped in a complete topology, further improving the utilization rate of qubits in the quantum chip.

[0038] 3. The quantum chip resource allocation service module in the present application uses the community discovery algorithm and the greedy algorithm to obtain a qubit topology that meets the requirements among the idle qubits of the quantum chip. It uses the idea of "from bottom to top" to perform high-quality real-time dynamic partitioning on the idle qubits of a certain quantum chip in the quantum chip cluster of the system that meets the requirements for the number of idle qubits according to the actual needs of the quantum computing tasks to be processed. The obtained qubit topology can achieve a unique match with the quantum computing tasks to be processed, with no matching waiting time and a high matching degree. While greatly improving the resource utilization rate of the quantum chip, it also effectively improves the execution timeliness of the quantum computing tasks in the program waiting queue; using this method can quickly find the optimal partition area for each quantum computing task in the program waiting queue to perform mapping on the idle qubits of a certain quantum chip in the quantum chip cluster of the system that meets the requirements. Description of the Drawings

[0039] Figure 1 It is a schematic structural diagram of a quantum computer operating system proposed in this embodiment;

[0040] Figure 2 It is a schematic diagram of overall mapping after merging quantum computing tasks P1 and P2 using the quantum computing task merging module;

[0041] Figure 3 It is a schematic structural diagram of a quantum chip;

[0042] Figure 4 It is a schematic flowchart of a method for processing quantum computing tasks in a quantum computer proposed in this embodiment. Detailed Embodiment

[0043] The specific embodiments of the present invention will be described in more detail below in conjunction with the schematic diagrams. The advantages and features of the present invention will become clearer according to the following description and the claims. It should be noted that the attached drawings are all in a very simplified form and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the attached drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0045] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0046] Please refer to Figure 1 , an embodiment of the present invention provides a quantum computer operating system, including a quantum computing task receiving module 10, a quantum computing task priority processing module 20, a quantum computing task merging module 30, a quantum chip resource allocation service module 40, and a quantum computing task scheduling and mapping module 50.

[0047] The quantum computing task receiving module 10 is configured to receive a quantum computing task queue, where the quantum computing task queue includes a plurality of quantum computing tasks.

[0048] Those skilled in the art can understand that the quantum computing tasks are uploaded in real time by users. In this embodiment, the uploading method of the quantum computing tasks can be that the user submits corresponding tasks on the quantum cloud platform. As users' research interest in the field of quantum computing becomes increasingly strong, more and more quantum computing tasks will be submitted to the quantum cloud platform. However, due to the limited coherence time of the qubits of the NISQ (Noisy Intermediate-Scale Quantum) devices currently used in the quantum chip cluster and the error-prone quantum logic gates, as the number of quantum computing tasks submitted by users increases during the use of the quantum cloud platform, there will be a quantum computing task queue. Generally, the demand for the number of qubits in the quantum chip cluster by quantum computing tasks is greater than the processing capacity of the quantum chip cluster. How to schedule quantum computing tasks to ensure the execution of tasks based on the full utilization of the quantum chip cluster needs to be studied.

[0049] This application schedules quantum computing tasks through a unique method for determining the scheduling priority of quantum computing tasks to ensure this effect. To achieve this effect, the quantum computing task priority processing module 20 described in this application is configured to obtain the respective priorities of each quantum computing task in the quantum computing task queue based on the depth of the quantum computing task, the number of qubits required, and the time already waiting in the quantum computing task queue. Among them, the quantum computing task with a higher priority is executed first.

[0050] Specifically, the priority values of all currently unprocessed quantum computing tasks can be calculated based on the following sorting index formula: R = (W + 1) / S; where R is the priority value, W is the queuing waiting time of the quantum computing task in the quantum computing task queue after submission, and S is the size of the quantum computing task, which can be expressed as S = n * d, where n is the number of qubits required to execute the quantum computing task, and d is the depth of the quantum computing task. The depth represents the depth of the quantum circuit corresponding to the quantum computing task and is also the length of the quantum circuit.

[0051] Through the above scheduling priority of quantum computing tasks, not only the waiting time of quantum computing tasks is considered, but also the size of quantum computing tasks based on the number of qubits and the depth of quantum computing tasks is considered. The consideration of the number of qubits and the depth of quantum computing tasks ensures the full utilization of the quantum chip cluster, thereby improving the execution efficiency of the quantum computing task queue.

[0052] It can be understood that the layer is the unit of the depth of the quantum circuit. One layer refers to one (layer) time sequence. One layer of quantum logic gates are quantum logic gates that can be executed simultaneously within one time sequence, and the same layer of quantum logic gates are quantum logic gates of the same time sequence that can be executed simultaneously.

[0053] In addition, it can be seen from the sorting index formula of the priority that there are the following rules for the priority: the larger R is, the higher the priority of the corresponding quantum computing task. Therefore, W can ensure the principle of first come, first served for the quantum computing task; and when the queuing waiting times are similar, the quantum computing task with a smaller S has a higher priority, which ensures the maximization of quantum resource utilization. For quantum computing tasks with similar S values, among them, the quantum computing task with a smaller number of qubits required has a higher priority. Therefore, in the quantum computing task queue, the quantum computing task with the highest R value is the quantum computing task with the highest priority.

[0054] According to the previous priority rules, the first task and the second task are the two quantum computing tasks with the highest priorities in the quantum computing task queue. Similarly, the quantum computing task scheduling module 40 can schedule the several short tasks in order of decreasing priority. The quantum computing task priority processing module 20 divides the quantum computing tasks in the quantum computing task queue into their respective priorities according to the depth of the quantum computing tasks, the number of qubits required, and the time already waiting in the quantum computing task queue. When the quantum chip resources cannot meet the simultaneous execution of all tasks, by preferentially executing the quantum computing tasks with higher priorities, the utilization rate of qubits in the quantum chip is improved, and the overall waiting time of the quantum computing tasks in the quantum computing task queue is effectively reduced.

[0055] The quantum computing task priority processing module 20 includes a quantum computing task status acquisition unit and a quantum computing task priority acquisition unit. The quantum computing task status acquisition unit is configured to acquire the depth of each quantum computing task in the quantum computing task queue, the number of qubits required, and the time waiting in the quantum computing task queue. The quantum computing task priority acquisition unit is configured to acquire the priority of each quantum computing task. The priority of each quantum computing task is R, and R = (W + 1) / (n * d), where W is the time the quantum computing task has waited in the quantum computing task queue, n is the number of qubits required for the quantum computing task, and d is the depth of the quantum computing task.

[0056] The inventors also found in practical applications that when two quantum computing tasks both require two-qubit quantum logic gates to participate, if these two quantum computing tasks are mapped to two relatively close qubit topologies, crosstalk effects will inevitably occur, resulting in a sharp increase in the error rate of the two-qubit quantum logic gates. To avoid the occurrence of crosstalk, in the prior art, when mapping two quantum computing tasks in the quantum computer operating system, when both of these two quantum computing tasks require two-qubit quantum logic gates to participate, the qubit topologies to which these two quantum computing tasks are mapped will be spaced far enough apart on the quantum chip to reduce crosstalk effects. This solution in the prior art greatly limits the utilization rate of qubits in the quantum chip and causes waste of quantum chip resources.

[0057] To solve the above problems, a quantum computing task merging module 30 is provided in the quantum computer operating system of the present application. The quantum computing task merging module 30 is configured to merge several quantum computing tasks into an overall quantum computing task in the order of decreasing priority in the quantum computing task queue, and update the quantum computing task queue. Those skilled in the art should understand that, for the convenience of understanding the technical solution of the present application, in this embodiment, the merging of two quantum computing tasks is taken as an example, and the merging of other larger numbers of quantum computing tasks can be deduced from the merging process of two quantum computing tasks.

[0058] Since two isolated quantum computing tasks do not know the execution timings of each other, in order to avoid crosstalk during the mapping process, the quantum bit topologies to which these two quantum computing tasks are mapped will be spaced as far apart as possible on the quantum chip. In the present application, the quantum computing task merging module 30 can merge several quantum computing tasks into an overall quantum computing task in the order of decreasing priority. Since the timings of the individual quantum computing tasks in the overall quantum computing task are known after merging, these timings can be fully utilized during the mapping process. Two quantum computing tasks that originally needed to be mapped separately can be mapped in a complete topology, further improving the utilization rate of quantum bits in the quantum chip.

[0059] In addition, when two quantum computing tasks are independently mapped onto the quantum chip, the number of SWAP gate operations between quantum bits in the quantum chip will increase significantly. Please refer to Figure 2 , Figure 2 FIG. is a schematic diagram of overall mapping after merging quantum computing tasks P1 and P2 using the quantum computing task merging module 30. Figure 2 In FIG., P1 allocation represents the mapping partition of a quantum computing task P1, and P2 allocation represents the mapping partition of another quantum computing task P2 adjacent to the mapping partition of the P1 quantum computing task. The two mapping partitions are respectively allocated in two dashed boxes. qi and qj are the quantum bits in the executable quantum circuit corresponding to the P1 quantum computing task that need to immediately execute two-bit quantum logic gates, and they are both in the mapped but unexecuted state.

[0060] In the mapping partition of the quantum computing task P1, there are three other qubits with connection relationships between qi and qj. During the execution of qi and qj, these three qubits are needed as routes for the layer-by-layer transformation operation of the SWAP gate. Therefore, the execution of qi and qj requires three routes. However, since there are errors in the gate operations of any two qubits with direct connection relationships, that is, the gate operation errors between qi and qj executed through the three routes will accumulate and increase, which reduces the fidelity of the quantum computing task P1 to a certain extent. By observing Figure 2 the topological structure of the quantum chip in it, it can be seen that there is a qubit qn in the mapping partition of the quantum computing task P2 that has connection relationships with the qubits qi and qj respectively. If the quantum computing task P1 and the quantum computing task P2 are merged, then the swap operation when the qubits qi and qj execute the two-qubit quantum logic gate may take a shortcut. After merging the quantum computing task P1 and the quantum computing task P2, all the qubits of the quantum computing task P1 and the quantum computing task P2 will share the merged mapping partition. At this time, the qubits qi and qj will choose to execute the two-qubit quantum logic gate through a swap path that is shorter than the internal swap path in the mapping area of the quantum computing task P1, that is, the qubits qi and qj will choose the qubit qn that has a direct connection with both of them and exists in the mapping area of the quantum computing task P2 for the SWAP gate operation, so as to realize the operation of the two-qubit quantum logic gate between the qubits qi and qj through one route and one SWAP gate operation. This can effectively reduce the gate operation error and improve the fidelity of the quantum computing task to a certain extent.

[0061] Through the above analysis, it can be seen that after merging two quantum computing tasks by using the quantum computing task merging module 30 of the present application and then performing the overall mapping, it helps to reduce the SWAP gate overhead, and can also make full use of the powerful qubits and the links on the quantum chip, thereby reducing the SWAP gate cost during the mapping and reducing the interference between multiple concurrent quantum computing tasks and improving the overall fidelity.

[0062] Furthermore, since the qubits of a quantum chip are fragile and extremely vulnerable to noise interference, when two-bit quantum logic gates are required in both of two quantum computing tasks, if these two quantum computing tasks are mapped to two relatively close qubit topologies, crosstalk effects will inevitably occur, which will also cause a sharp increase in the operation error of the two-bit quantum logic gate and seriously affect the fidelity of the quantum computing task to a certain extent. And in the optimal mapping partitions of the two quantum computing tasks, some qubits affected by crosstalk will have to be idle, which also causes a waste of qubit resources to a certain extent and reduces the utilization rate of qubit resources. After using the quantum computing task merging module 30 in this application, since the timing of each quantum computing task in the overall quantum computing task is known after merging, crosstalk effects can be effectively avoided during the mapping process by using the timing. Please refer to Figure 3 , Figure 3 which is a schematic diagram of a quantum chip. Suppose there are quantum computing tasks, namely the first quantum computing task and the second quantum computing task. Among them, the first quantum computing task requires 9 qubits, and the second quantum computing task requires 7 qubits. After being merged by the quantum computing task merging module 30 and mapped to Figure 3 the quantum chip, where the mapping area of the first quantum computing task is Q 12 ,Q 13 ,Q 14 ,Q 22 ,Q 23 ,Q 24 ,Q 32 ,Q 33 and Q 34 , and the mapping area of the second quantum computing task is Q 15 ,Q 25 ,Q 35 ,Q 42 ,Q 43 ,Q 44 and Q 45 . If there is a moment when two-bit quantum logic gates need to be executed simultaneously in the execution timings of the first quantum computing task and the second quantum computing task, then when mapping, the four bits used to execute these two quantum logic gates are spaced apart in their respective mapping areas. For example, Q 12 and Q 13 can be selected in the execution area of the first quantum computing task to execute the two-bit quantum logic gate, and Q 44 and Q 45To execute a two-bit quantum logic gate, in this way, crosstalk can be effectively avoided during mapping. It should be noted that the above chip structure and the division of the quantum computing task execution area are only examples for facilitating the understanding of the solution of this application and should not be regarded as any limitation to this application. Those skilled in the art should understand that the above example is intended to express a solution on how to effectively avoid crosstalk. There are many other examples, which will not be elaborated here one by one.

[0063] After the quantum computer operating system combines several quantum computing tasks into the overall quantum computing task, it needs to allocate a corresponding topological structure in the quantum chip according to the number of qubits required for the overall quantum computing task. In the prior art, the quantum computer operating system generally first divides all the qubits on the quantum chip into several executable quantum circuit blocks (i.e., qubit topological structures) according to the multi-layer segmentation processing method, and then selects available executable quantum circuit blocks from them to perform mapping according to the number of qubits in the quantum computing task to be run. The number of qubits in the available executable quantum circuit block is the same as the number of qubits in the quantum program to be run. However, with the continuous increase of quantum computing requirements in the quantum computer operating system, the number of quantum computing tasks to be processed will continue to increase, and the number of qubits required for each quantum computing task varies greatly. Using this kind of executable quantum circuit block for mapping the quantum computing task to be run will have problems such as unreasonable segmentation of the executable quantum circuit block, long processing time for finding an executable quantum circuit block that matches the quantum computing task to be run, resulting in low utilization rate of qubit resources in the quantum chip, long waiting time for the quantum computing task to run, and low timeliness of program operation, leading to a poor user experience.

[0064] To solve this problem, in the quantum computer operating system proposed in this embodiment, the quantum chip resource allocation service module 40 is configured to obtain a qubit topological structure that meets the requirements from the idle qubits in the quantum chip by using the community discovery algorithm and the greedy algorithm based on the updated quantum computing task queue, where the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks.

[0065] The reward function can be obtained through the community discovery algorithm and the greedy algorithm. Since the value of the reward function is determined by the read fidelity of the qubits near an idle qubit, the reliability parameter of performing two-qubit quantum logic gate operations between any two directly connected qubits among the qubits near this qubit, and the number of feedlines. Therefore, the qubits whose read fidelity of the qubits near this qubit, the reliability parameter of performing two-qubit quantum logic gate operations between any two directly connected qubits among the qubits near this qubit, and the number of feedlines are all within the preset range can be set as the qubit topology structure. Those skilled in the art can understand that whether the value of the reward function meets the requirements can be determined according to the quality requirements of the qubit topology structure, which is not limited here.

[0066] The reward function is:

[0067]

[0068] where F is the value of the reward function, Q m is the tightness of the qubit topology structure after adding another qubit, Q o is the tightness of the qubit topology structure before adding another qubit. E is the average value of the fidelities of performing two-qubit quantum logic gate operations between any two directly connected qubits in the qubit topology structure after adding another qubit. The fidelity of performing two-qubit quantum logic gate operations between the two directly connected qubits is the reliability of the link between the two directly connected qubits. V is the average value of the read fidelities of all qubits in the qubit topology structure after adding another qubit. ω and β are pre-configured weight coefficients, and is an empirical constant. L is the total number of feedlines in the qubit topology structure after adding another qubit. Those skilled in the art can understand that for a specific quantum chip cluster, appropriate ω and β can be used to adjust the physical topology of the qubit topology structure, the operation error rate of two-qubit quantum logic gates, and the weights of the feedline structure in a certain quantum chip to maximize the value of the reward function. Exemplarily, if the third term of the calculation formula of the reward function is very large, it indicates that the resulting community structure after merging will cover some feedlines, and these feedlines need to be filled as much as possible.

[0069] It should be noted that the reward function is obtained by using the community detection algorithm and the greedy algorithm. Among them, the community detection algorithm is used to discover the community structure in the network structure and belongs to a clustering algorithm. These divided community structures are subgraphs, including vertices and edges. The connections between vertices within the same community are tight, while the connections between communities are relatively sparse. The modularity is selected as a metric to evaluate the quality of the division of a community structure. The modularity is the degree of edges within the community structure minus the total degree of vertices within the community structure, and its calculation formula is

[0070]

[0071] where Q is the modularity of a community structure C. The higher the value of the modularity Q, the more appropriate the division of the community structure C. m is the total number of edges of the community structure C, Ic is the number of all internal edges in the community structure C, and Dc is the sum of the degrees of all vertices in the community structure C.

[0072] Quantum programs create entanglement by using two-qubit quantum logic gates, and two-qubit quantum logic gates can only be executed between two physical qubits coupled on a quantum chip. Therefore, the qubits on the quantum chip required for executing a single quantum computing task should be closely allocated, and crosstalk and other mutual interferences should be avoided between different quantum computing tasks. The qubit topology structure is equivalent to the community structure formed by the aggregation of idle physical qubits on the quantum chip. Therefore, the tightness Q m and Q o of the qubit topology structure can be obtained by using the modularity Q calculation formula of the community detection algorithm, where each qubit in the grid structure of the quantum chip is equivalent to a vertex of the community structure, and the link between two qubits is equivalent to an edge of the community structure.

[0073] The idea of the greedy algorithm is to take an idle qubit of the quantum chip as a community structure, and continuously merge the idle qubits near this qubit with this community structure to form a new community structure, so as to maximize the value of the reward function until a final community structure containing the number of qubits required for the quantum computing task is obtained. The final community structure is the required qubit topology structure.

[0074] Furthermore, since the coherence time of each qubit in a quantum chip is finite and different, where the qubit with a larger coherence time has better reliability. If there is a qubit with a short coherence time in the qubit topology where a quantum computing task is located, then the fidelity of the quantum computing task will be greatly affected. The decoherence error of qubits grows exponentially with respect to the length of the quantum program. Therefore, a quantum computing task should be executed on qubits whose coherence time is longer than its own execution time. Before obtaining the qubit topology, qubits with a coherence time that is too short compared to the execution time of the quantum computing task need to be excluded from the available qubits for partitioning.

[0075] Specifically, the quantum computer operating system further includes a coherence time acquisition and judgment module and a quantum chip resource discrimination module. The coherence time acquisition and judgment module is configured to acquire the coherence time of the idle qubits in the quantum chip and judge whether the coherence time of each idle qubit is greater than a first threshold, where the first threshold is determined according to the execution time of the currently pending quantum computing task. The quantum chip resource discrimination module is configured to, when the judgment result is negative, set the corresponding qubit as an unavailable qubit, and the quantum chip resource allocation service module 40 will not partition the unavailable qubit into the qubit topology.

[0076] After finding the qubit topology, the quantum computing task scheduling and mapping module schedules the pending quantum computing tasks based on the updated quantum computing task queue and maps the pending quantum computing tasks to the qubit topology in order from highest to lowest priority. Thus, the quantum computer operating system completes the processing process of the quantum computing task, and the subsequent process is the execution process of executing the corresponding quantum computing task in the quantum chip.

[0077] Please refer to Figure 4 , based on the same inventive concept, this embodiment also proposes a method for processing quantum computing tasks in a quantum computer, including:

[0078] S1: Receive a quantum computing task queue, where the quantum computing task queue includes multiple quantum computing tasks;

[0079] S2: Based on the depth of the quantum computing task, the number of required qubits, and the time already waiting in the quantum computing task queue, obtain the respective priorities of the quantum computing tasks in the quantum computing task queue, where the quantum computing task with a higher priority is executed first;

[0080] S3: Merge several quantum computing tasks in the quantum computing task queue into an overall quantum computing task in order of decreasing priority, and update the quantum computing task queue;

[0081] S4: Based on the updated quantum computing task queue, use the community discovery algorithm and the greedy algorithm to obtain a qualified qubit topology structure among the idle qubits of the quantum chip, where the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks;

[0082] S5: Schedule the quantum computing tasks to be executed based on the updated quantum computing task queue, and map the quantum computing tasks to be executed to the qubit topology structure in order of decreasing priority.

[0083] Optionally, obtaining the respective priorities of the quantum computing tasks in the quantum computing task queue based on the depth of the quantum computing tasks, the number of qubits required, and the time already waited in the quantum computing task queue includes:

[0084] Obtain the depth, the number of qubits required, and the time waited in the quantum computing task queue for each quantum computing task in the quantum computing task queue;

[0085] Obtain the priority of each quantum computing task. The priority of each quantum computing task is R, where R = (W + 1) / (n * d), W is the time waited by the quantum computing task in the quantum computing task queue, n is the number of qubits required for the quantum computing task, and d is the depth of the quantum computing task.

[0086] Optionally, the qualification includes: the number of qubits in the qubit topology structure is equal to the number of qubits required for the currently pending quantum computing task, and the tightness of the qubit topology structure, the readout fidelity of all qubits in the qubit topology structure, the reliability parameter for executing two-qubit quantum logic gates in the qubit topology structure, and the number of feeders in the qubit topology structure all meet the preset thresholds.

[0087] Optionally, the processing method further includes:

[0088] Obtain the coherence time of the idle qubits in the quantum chip, and determine whether the coherence time of each idle qubit is greater than a first threshold, where the first threshold is determined according to the execution time of the currently pending quantum computing task;

[0089] When the judgment result is negative, the corresponding qubit is set as an unavailable qubit, and the quantum chip resource configuration service module will not allocate the unavailable qubit to the qubit topology structure.

[0090] Based on the same inventive concept, this embodiment also provides a quantum computer, including the quantum computer operating system described in any one of the above feature descriptions.

[0091] Based on the same inventive concept, this embodiment also provides a readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it can implement the processing method described in any one of the above feature descriptions.

[0092] The readable storage medium may be a tangible device that can hold and store instructions used by the instruction execution device, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punched card or raised structures in grooves storing instructions thereon, and any suitable combination of the above. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter or network interface in each computing / processing device receives the computer program from the network and forwards the computer program for storage in the readable storage medium in each computing / processing device. The computer program for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages - such as Smalltalk, C++, etc., and conventional procedural programming languages - such as the "C" language or similar programming languages. The computer program may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., by using an Internet service provider to connect through the Internet). In some embodiments, by using the status information of the computer program to customize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute computer-readable program instructions to implement various aspects of the present invention.

[0093] Aspects of the present invention are described herein with reference to the flowcharts and / or block diagrams of methods, systems, and computer program products according to embodiments of the present invention. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer programs. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, thereby producing a machine, such that the programs, when executed by the processor of the computer or other programmable data processing apparatus, generate a device for implementing the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams. These computer programs can also be stored in a readable storage medium, which causes a computer, a programmable data processing apparatus, and / or other devices to operate in a specific manner, so that the readable storage medium storing the computer programs includes a manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams.

[0094] The computer programs can also be loaded onto a computer, other programmable data processing apparatus, or other devices, such that a series of operation steps are executed on the computer, other programmable data processing apparatus, or other devices to generate a computer-implemented process, so that the computer programs executed on the computer, other programmable data processing apparatus, or other devices implement the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams.

[0095] Based on the same inventive concept, this embodiment also provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the processing method described in any one of the above feature descriptions.

[0096] In the description of this specification, the descriptions with reference to terms such as "one embodiment", "some embodiments", "example", or "specific example", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0097] The above are only the preferred embodiments of the present invention and do not impose any restrictive effect on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A quantum computer operating system, characterized in that, it includes: A quantum computing task receiving module, configured to receive a quantum computing task queue, where the quantum computing task queue includes multiple quantum computing tasks; A quantum computing task priority processing module, configured to obtain the depth of a quantum computing task, the number of required qubits, and the waiting time in the quantum computing task queue to calculate the priority of each quantum computing task, and the calculation formula is: R = (W + 1) / (n * d); where R is the priority of the quantum computing task, W is the waiting time of the quantum computing task in the quantum computing task queue, n is the number of qubits required for the quantum computing task, d is the depth of the quantum computing task, and the quantum computing task with a higher priority is executed first; A quantum computing task merging module, configured to merge several quantum computing tasks in the quantum computing task queue into an overall quantum computing task in order from highest to lowest priority, and update the quantum computing task queue; A quantum chip resource allocation service module, configured to obtain a qualified qubit topology from the idle qubits of the quantum chip based on the updated quantum computing task queue by using the community discovery algorithm and the greedy algorithm, where the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks; A quantum computing task scheduling and mapping module, configured to schedule the quantum computing tasks to be executed based on the updated quantum computing task queue, and map the quantum computing tasks to be executed to the qubit topology in order from highest to lowest priority.

2. The quantum computer operating system according to claim 1, characterized in that, the qualification includes: the number of qubits in the qubit topology is equal to the number of qubits required for the currently to-be-executed quantum computing task, and the tightness of the qubit topology, the readout fidelity of all qubits in the qubit topology, the reliability parameter of performing two-qubit quantum logic gates in the qubit topology, and the number of feeders in the qubit topology all meet the preset thresholds.

3. The quantum computer operating system according to claim 1, characterized in that, it further includes: A coherence time acquisition and judgment module, configured to acquire the coherence time of the idle qubits in the quantum chip, and judge whether the coherence time of each idle qubit is greater than a first threshold, where the first threshold is determined according to the execution time of the currently to-be-processed quantum computing task; A quantum chip resource discrimination module, configured to set the corresponding qubit as an unavailable qubit when the judgment result is negative, and the quantum chip resource allocation service module will not divide the unavailable qubit into the qubit topology.

4. A method for processing quantum computing tasks in a quantum computer, characterized in that, it includes: Receiving a quantum computing task queue, where the quantum computing task queue includes multiple quantum computing tasks; Obtain the depth of the quantum computing task, the number of qubits required, and the time that the quantum computing task has been waiting in the quantum computing task queue to calculate the priority of each quantum computing task. The calculation formula is: R = (W + 1) / (n * d); where R is the priority of the quantum computing task, W is the time that the quantum computing task has been waiting in the quantum computing task queue, n is the number of qubits required for the quantum computing task, and d is the depth of the quantum computing task. The quantum computing task with a higher priority is executed first; Merge several quantum computing tasks in the quantum computing task queue into an overall quantum computing task in descending order of priority, and update the quantum computing task queue; Based on the updated quantum computing task queue, use the community discovery algorithm and the greedy algorithm to obtain a qubit topology structure that meets the requirements among the idle qubits of the quantum chip, where the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks; Schedule the quantum computing tasks to be executed based on the updated quantum computing task queue, and map the quantum computing tasks to be executed to the qubit topology structure in descending order of priority.

5. The method for processing quantum computing tasks in a quantum computer according to claim 4, characterized in that, The meeting the requirements includes: the number of qubits in the qubit topology structure is equal to the number of qubits required for the currently pending quantum computing task, and the tightness of the qubit topology structure, the read fidelity of all qubits in the qubit topology structure, the reliability parameter for executing two-qubit quantum logic gates in the qubit topology structure, and the number of feeders in the qubit topology structure all meet the preset thresholds.

6. The method for processing quantum computing tasks in a quantum computer according to claim 4, characterized in that, The processing method further includes: Obtain the coherence time of the idle qubits in the quantum chip, and determine whether the coherence time of each idle qubit is greater than a first threshold, where the first threshold is determined according to the execution time of the currently pending quantum computing task; When the judgment result is negative, set the corresponding qubit as an unavailable qubit, and the quantum chip resource configuration service module will not allocate the unavailable qubit to the qubit topology structure.

7. A quantum computer, characterized in that, It includes the quantum computer operating system according to any one of claims 1-3.

8. A readable storage medium, on which a computer program is stored, characterized in that, When the computer program is executed by a processor, it can implement the processing method according to any one of claims 4 to 6.

9. An electronic device, including a memory and a processor, characterized in that, A computer program is stored in the memory, and the processor is set to run the computer program to execute the processing method according to any one of claims 4 to 6.

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