Independent plane architecture in memory devices

Abstract

The present disclosure relates to independent plane architecture in a memory device. The memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to an independent plane architecture in a memory device of a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. SUMMARY

[0003] In one aspect, the present disclosure provides a memory device comprising: a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes; a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups; a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups; and a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

[0004] In another aspect, the present disclosure further provides a memory device comprising: a memory array comprising a plurality of memory planes, wherein a first subset of the plurality of memory planes is associated with a first independent plane group and a second subset of the plurality of memory planes is associated with a second independent plane group; a first independent analog driver circuit associated with the first independent plane group and a second independent analog driver circuit associated with the second independent plane group; a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the first and second independent analog driver circuits and the first and second independent plane groups; and a first control logic element associated with the first independent analog driver circuit and the first independent plane group, and a second control logic element associated with the second independent analog driver circuit and the second independent plane group.

[0005] In yet another aspect, the disclosure further provides a method comprising: receiving, at a memory device, a plurality of requests for the memory device to perform memory access operations on a memory array of the memory device, the memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes; determining whether the memory device is configured to utilize independent plane groups; responsive to determining that the memory device is configured to utilize independent plane groups, enabling a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent plane groups; and causing the plurality of control logic elements to perform the memory access operations on the memory planes of two or more of the plurality of independent plane groups in parallel using a respective one of a plurality of independent analog driver circuits. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, with the various embodiments of the disclosure being illustrated by the reference characters noted in the drawings. It is to be understood that similar or like reference characters are denoted throughout the drawing figures by like reference characters, and that

[0007] Figure 1 An example computing system including a memory sub-system according to some embodiments of the disclosure is described.

[0008] Figure 2 is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system according to embodiments.

[0009] Figure 3 is a block diagram of a multi-plane memory device configured for parallel page cache resource access according to some embodiments of the disclosure.

[0010] Figure 4 is a block diagram of an independent plane architecture in a memory device according to some embodiments of the disclosure.

[0011] Figure 5 is a diagram illustrating parallel execution of memory access operations in a memory device having an independent plane architecture according to some embodiments of the disclosure.

[0012] Figure 6 is a flow diagram of an example method of power saving operations in a memory device having an independent plane architecture according to some embodiments of the disclosure.

[0013] Figure 7 is a block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to independent plane architecture in memory devices of a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Below, examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system, and can request data to be retrieved from the memory sub-system. Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system, and can request data to be retrieved from the memory sub-system.

[0015] The memory sub-system can include high-density non-volatile memory devices, where data needs to be retained when no power is supplied to the memory devices. One example of a non-volatile memory device is a NAND memory device. Below, examples of non-volatile memory devices are described. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a collection of physical blocks. Each block consists of a collection of pages. Each page consists of a collection of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states related to the number of bits being stored. The logic states can be represented by binary values (e.g., “0” and “1”), or combinations of such values.

[0016] A memory device can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. Below, a block refers to a unit of a memory device for storing data, and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks can be grouped together to form a plane of a memory device in order to allow for parallel operations on each plane. A memory device can include circuitry that performs parallel memory page accesses of two or more memory planes. For example, a memory device can include multiple access line driver circuits and power circuits that can be shared by the planes of the memory device to facilitate parallel accesses of pages, including pages of different page types, of two or more memory planes. For ease of description, these circuits can be generally referred to as independent plane driver circuits.

[0017] In certain multi-plane memory devices, a given memory die is limited to performing a single programming operation at any time. Different types of programming operations can be performed (e.g., single page programming operations, multi-page programming operations), but only one operation can be performed at a time, regardless of type. In a single page programming operation, a page of data to be programmed is received (e.g., from a memory sub-system controller or host system), and a programming operation is performed on a single plane of the multi-plane memory device. During the single page programming operation, the remaining planes of the memory device are inaccessible to the memory sub-system controller and host system (i.e., all planes appear “busy” even though only a single plane is actually utilized). In a multi-page programming operation, multiple pages of data are received, and a programming operation is performed on multiple planes of the multi-plane memory device once all of the multiple pages are received. Thus, for both single page programming operations and multi-plane programming operations, no other memory access operations (e.g., program, read, or erase operations) can be performed on the memory device in parallel.

[0018] Certain memory devices attempt to improve performance by enabling parallel memory access operations to be performed asynchronously. Doing so can improve quality of service in mixed workloads (e.g., a mix of program operations and read operations), increase write throughput of the memory device, increase write granularity (e.g., smaller block sizes), and reduce buffer requirements (i.e., due to smaller amounts of data for performing program operations). To enable parallel memory access operations, certain memory devices utilize multiple memory dies in a memory sub-system, such that a separate memory access operation can be performed on each memory die asynchronously. Such an approach increases the area of the memory device (thereby increasing cost), has a higher power utilization on multiple required circuit elements, and is subject to packaging limitations. Other memory devices attempt to implement separate memory devices within a single die, but this approach also suffers from increased power utilization.

[0019] Aspects of the disclosure address the above and other deficiencies by providing an independent plane architecture in a memory device of a memory sub-system. In one embodiment, the memory device is a multi-plane memory device that includes a plurality of memory planes. In one embodiment, the plurality of memory planes is logically and physically divided into two or more independent plane groups, each independent plane group including a separate set of one or more memory planes. In one embodiment, each independent plane group has a corresponding respective analog driver circuit (or set of analog driver circuits) for applying voltage signals to the memory planes in the corresponding independent plane group. In one embodiment, the two or more independent plane groups also share a common analog circuit (or set of common analog circuits) in order to reduce power consumption and area usage in the memory device. In one embodiment, each of the independent plane groups has a corresponding respective media controller. Each controller is configured to perform memory access operations on the memory planes in the corresponding independent plane group (e.g., cause the corresponding respective analog driver circuit to apply voltage signals received from the common analog circuit to a certain memory plane or memory planes of the corresponding independent plane group). In one embodiment, the media controller associated with one independent plane group is designated as a "primary" controller, while the media controllers associated with the other independent plane groups are designated as "secondary" controllers. In certain situations, the secondary controllers can be disabled for power consumption purposes, and the primary controller can perform operations on the memory planes of the multiple independent plane groups. For example, in mobile devices where power saving is more important, and when sequential write workloads are being performed, the benefits of accessing independent plane groups in parallel can not be meaningful, so the secondary controllers can be disabled and the memory device can operate in a traditional mode. However, when the secondary controllers are enabled, the memory device featuring the independent plane architecture described herein can perform asynchronous memory access operations on the memory planes of each independent plane group in parallel (e.g., at least partially overlapping in time).

[0020] Advantages of this approach include, but are not limited to, improved performance in a memory sub-system. The independent plane architecture provides improved quality of service in mixed write and read workloads, improves write throughput by allowing parallel write operations to be performed on separate plane groups, increases write granularity (i.e., by using smaller block sizes), and reduces buffer requirements for the memory sub-system controller due to the smaller amount of data that needs to be held during write operations. The ability to disable the secondary controllers in the memory device when only a single media controller is active reduces power consumption for traditional operations. Additionally, the independent plane architecture reduces interference caused by parallel noisy and sensitive operations by providing proper power delivery isolation.

[0021] Figure 1An example computing system 100 including a memory sub-system 110 is described in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of these.

[0022] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, secure digital (SD), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including memory and a processing device.

[0024] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 An example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0025] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and to read data from the memory sub-system 110.

[0026] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface, an open NAND flash interface (ONFI) interface, or some other interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs) such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0028] Some examples of non-volatile memory devices (e.g., the memory devices 130) include negative-and (NAND) type flash memories and in-place writeable memories such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. Additionally, cross-point non-volatile memories can perform in-place write operations, where a non-volatile memory cell can be programmed without being previously erased, as compared to many flash-based memories. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit of data per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a penta-level cell (PLC), can store multiple bits of data per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device that can be used to store data. In the case of some types of memory, such as NAND, pages can be grouped to form blocks.

[0030] Although non-volatile memory components are described, such as 3D cross point non-volatile memory cell arrays and NAND type flash memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory, such as read only memory (ROM), phase change memory (PCM), self- select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non (NOR) flash memory, electrically erasable programmable read only memory (EEPROM).

[0031] The memory sub-system controller 115 (or simply controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory sub-system controller 115 can be a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0033] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the local memory 119 is illustrated as being included in the memory sub-system controller 115, in another embodiment of the present disclosure, the memory sub-system 110 does not include a memory sub-system controller 115, but can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system). Figure 1

[0034] Generally, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), name space) and a physical address (e.g., physical block address) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory devices 130, as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0035] The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive and decode an address from the memory sub-system controller 115 to access the memory devices 130.

[0036] ​In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory sub-system controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory sub-system 110 is a managed memory device that includes a raw memory device 130 with control logic on-die (e.g., the local media controller 135) and a controller for media management (e.g., the memory sub-system controller 115) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] In one embodiment, the memory sub-system 110 includes a memory interface component 113. The memory interface component 113 is responsible for handling the interaction of the memory sub-system controller 115 with the memory devices (e.g., memory device 130) of the memory sub-system 110. For example, the memory interface component 113 can send memory access commands corresponding to requests received from the host system 120 to the memory device 130, such as program commands, read commands, or other commands. Additionally, the memory interface component 113 can receive data from the memory device 130, such as data retrieved in response to a read command or confirmation of successful execution of a program command. In some embodiments, the memory sub-system controller 115 includes at least a portion of the memory interface 113. For example, the memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the memory interface component 113 is part of the host system 110, an application, or an operating system.

[0038] In one embodiment, the memory device 130 is a memory array (not shown) having a plurality of planes arranged into a plurality of independent plane groups. The memory device 130 further includes a local media controller 135 and independent plane architecture (IPA) circuitry 150. In one embodiment, the circuitry 150 includes: a plurality of independent analog driver circuits coupled to the memory array, where each respective independent analog driver circuit is associated with (i.e., a one-to-one relationship) a corresponding independent plane group; and a common analog circuit coupled to the memory array, where the common analog circuit is shared by all of the independent analog driver circuits and independent plane groups. In one embodiment, the independent analog driver circuits are configured to provide a selected analog voltage reference received from the common analog circuit to the memory planes of the independent plane group in order to perform memory access operations at the direction of the local media controller 135.

[0039] In one embodiment, the local media controller 135 may represent multiple individual media controllers. For example, each independent plane group of the memory array may contain a corresponding media controller. Each media controller is configured to perform memory access operations on memory planes in the corresponding independent plane group (e.g., causing a voltage signal received from a common analog circuit from a corresponding analog driver circuit to one or more memory planes in the corresponding independent plane group). In one embodiment, the media controller associated with one independent plane group is designated as the "master" controller, while the media controllers associated with other independent plane groups are designated as "secondary" controllers. In some cases, secondary controllers may be disabled for power consumption purposes, and the master controller may perform operations on memory planes of multiple independent plane groups. Further details regarding the operation of the local media controller 135 and the independent plane architecture (IPA) circuitry 150 are described below.

[0040] Figure 2 The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1 A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0041] Memory device 130 includes an array 250 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 250 ( Figure 2 (Not shown in the text) can be programmed as one of at least two target data states.

[0042] Row decode circuitry 208 and column decode circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 250. Memory device 130 also includes input / output (I / O) control circuitry 212 to manage the input of commands, addresses, and data to memory device 130 and the output of data and status information from memory device 130. Address registers 214 are in communication with I / O control circuitry 212, as well as row decode circuitry 208 and column decode circuitry 210 to latch address signals prior to decoding. Command registers 224 are in communication with I / O control circuitry 212 and local media controller 135 to latch incoming commands.

[0043] A controller, such as local media controller 135 internal to memory device 130, controls access to memory cell array 250 in response to commands and generates status information for external memory sub-system controller 115, i.e., local media controller 135 is configured to perform access operations, such as read operations, program operations, and / or erase operations, on memory cell array 250. Local media controller 135 is in communication with row decode circuitry 208 and column decode circuitry 210 to control row decode circuitry 208 and column decode circuitry 210 in response to addresses.

[0044] Local media controller 135 is also in communication with page cache 240, which includes cache registers 242 and data registers 244. Cache registers 242 latch incoming or outgoing data as directed by local media controller 135 to temporarily store data while memory cell array 250 is busy writing or reading other data, respectively. During a program operation, such as a write operation, data can be transferred from cache registers 242 to data registers 244 for delivery to memory cell array 250; new data can then be latched in cache registers 242 from I / O control circuitry 212. During a read operation, data can be transferred from cache registers 242 to I / O control circuitry 212 for output to memory sub-system controller 115; new data can then be transferred from data registers 244 to cache registers 242. Cache registers 242 and / or data registers 244 can form (e.g., can form a portion of) page cache 240 of memory device 130. Page cache 240 can further include sensing devices (not shown) to sense data states of memory cells of memory cell array 250, such as by sensing the state of a data line connected to the memory cells. Figure 2 Status registers 222 can be in communication with I / O control circuitry 212 and local memory controller 135 to latch status information for output to memory sub-system controller 115.

[0045] Memory device 130 further includes independent plane architecture (IPA) circuitry 150. In one embodiment, IPA circuitry 150 includes a plurality of independent analog driver circuits coupled to memory array 250, where each respective independent analog driver circuit is associated with a corresponding independent plane group, and a common analog circuit coupled to the memory array, where the common analog circuit is shared by all of the independent analog driver circuits and independent plane groups. In one embodiment, the independent analog driver circuits are configured to provide a selected analog voltage reference received from the common analog circuit to the memory planes of an independent plane group in order to perform memory access operations in the direction of local media controller 135. Additional details regarding IPA circuitry 150 are provided below with respect to Figure 4 Additional details regarding IPA circuitry 150 are provided below with respect to

[0046] Memory device 130 receives control signals at memory subsystem controller 115 via control link 232 from local media controller 135. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can further be received via control link 232 depending on the nature of memory device 130. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory subsystem controller 115 via a multiplexed input / output (I / O) bus 234 and outputs data to memory subsystem controller 115 over I / O bus 234.

[0047] For example, a command can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then can be written into command register 224. An address can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then can be written into address register 214. Data can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices of I / O bus 234 and then can be written into cache register 242. The data can then be written into data register 244 for programming memory cell array 250.

[0048] In this embodiment, cache register 242 may be omitted, and data may be written directly to data register 244. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0049] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 2 The memory device 130. It should be understood that, reference Figure 2 The functions of the various block components described need not be divided into different components or component parts of the integrated circuit device. For example, a single component or component part of the integrated circuit device may be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The function of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that combinations of other I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0050] Figure 3 This is a block diagram illustrating a multi-plane memory device 130 configured for parallel page cache resource access according to some embodiments of the present disclosure. Memory planes 372(0)-372(3) can each be divided into data blocks, wherein different relative data blocks from two or more of memory planes 372(0)-372(3) can be accessed in parallel during memory access operations. For example, during memory access operations, data block 382 of memory plane 372(0), data block 383 of memory plane 372(1), data block 384 of memory plane 372(2), and data block 385 of memory plane 372(3) can each be accessed in parallel.

[0051] Memory device 130 includes memory array 250 divided into memory planes 372(0)-372(3), each including a respective number of memory cells. Multi-plane memory device 130 can further include local media controllers 135(0)-135(1) coupled to memory array 250. The memory cells can be non-volatile memory cells, such as NAND flash cells, or can be generally any type of memory cell. In one embodiment, each of memory planes 372(0)-372(3) includes a respective memory array of memory cells. In one embodiment, each of memory planes 372(0)-372(3) can include two or more independent memory arrays of memory cells.

[0052] Each of memory planes 372(0)-372(3) can be coupled to a respective page buffer 240(0)-240(3). Each page buffer 240(0)-240(3) can be configured to provide data to or receive data from the respective memory plane 372(0)-372(3). Page buffers 240(0)-240(3) can be controlled by local media controllers 135(0)-135(1). Data received from the respective memory plane 372(0)-372(3) can be locked at page buffers 240(0)-240(3), respectively, and retrieved by local media controllers 135(0)-135(1) and provided to memory subsystem controller 115 via the NVMe interface.

[0053] In one embodiment, memory planes 372(0)-372(3) of memory array 250 can be arranged in multiple independent plane groups. For example, memory planes 372(0)-372(1) can be part of a first independent plane group, and memory planes 372(2)-372(3) can be part of a second independent plane group. This is merely one example, and it should be understood that other arrangements are possible, including different numbers of groups and / or different numbers of planes in each group. In one embodiment, the memory planes of each independent plane group are coupled to respective access driver circuitry 374(0)-374(1), such as access line driver circuitry. In one embodiment, driver circuitry 374(0)-374(1) is part of independent plane access circuitry 150. Driver circuitry 374(0)-374(1) can be configured to regulate pages of respective blocks of associated memory planes 372(0)-372(3) for memory access operations, such as programming (i.e., writing) data, reading data, or erasing data. Each of driver circuitry 374(0)-374(1) can be coupled to a respective global access line associated with respective memory planes 372(0)-372(3). Each of the global access lines can be selectively coupled to respective local access lines within blocks of a plane during memory access operations associated with pages within the blocks. Driver circuitry 374(0)-374(1) can be controlled based on signals from local media controllers 135(0)-135(1). Each of driver circuitry 374(0)-374(1) can include or be coupled to respective power circuitry, and can provide voltages to respective access lines based on voltages provided by the respective power circuitry. The voltages provided by the power circuitry can be based on signals received from local media controllers 135(0)-135(1). In one embodiment, independent plane access circuitry further includes common analog circuitry 375, which is shared by all of independent analog driver circuitry 374(0)-374(1) and independent plane groups.

[0054] The local media controllers 135(0)-135(1) can control the driver circuits 374(0)-374(1) and the page buffers 240(0)-240(3) to perform memory access operations associated with each of a group of memory command and address pairs (e.g., received from the memory sub-system controller 115) in parallel. For example, the local media controller 135(0) can control the driver circuit 374(0) and the local media controller 135(1) can control the driver circuit 374(1) to perform parallel memory access operations. The local media controllers 135(0)-135(1) can include power control circuits that serially configure two or more of the driver circuits 374(0)-374(3) for parallel memory access operations and access control circuits configured to control two or more of the buffers 240(0)-240(3) to sense and latch data from or program data to the respective memory planes 372(0)-372(3) to perform the parallel memory access operations.

[0055] In operation, the local media controllers 135(0)-135(1) can receive a group of memory command and address pairs via the ONFI bus, where each pair arrives in parallel or serially. In some examples, the group of memory command and address pairs can each be associated with a different respective memory plane 372(0)-372(3) of the memory array 250. The local media controllers 135 can be configured to perform parallel memory access operations (e.g., read operations or program operations) for different memory planes 372(0)-372(3) of the memory array 250 in response to the group of memory command and address pairs. For example, the power control circuitry of the local media controllers 135(0)-135(1) can serially configure the driver circuitry 374(0)-374(1) for two or more memory planes 372(0)-372(3) associated with the group of memory command and address pairs for a parallel memory access operation based on respective page types (e.g., UP, MP, LP, XP, SLC / MLC / TLC / QLC pages). After the access line driver circuitry 374(0)-374(1) has been configured, the access control circuitry of the local media controllers 135 can control the page caches 240(0)-240(3) to access respective pages of each of the two or more memory planes 372(0)-372(3) associated with the group of memory command and address pairs during the parallel memory access operation, e.g., retrieve data or write data, in parallel. For example, the access control circuitry can control the page caches 240(0)-240(3) to charge / discharge bit lines, sense data from the two or more memory planes 372(0)-372(3), and / or latch the data in parallel (e.g., in parallel and / or simultaneously).

[0056] Based on signals received from local media controllers 135(0)-135(1), driver circuits 374(0)-374(1) coupled to memory planes 372(0)-372(3) associated with a group of memory command and address command pairs can select memory blocks or memory cells from the associated memory planes 372(0)-372(3) for memory operations, such as read, program, and / or erase operations. Driver circuits 374(0)-374(1) can drive different respective global access lines associated with respective memory planes 372(0)-372(3). As an example, driver circuit 374(0) can drive a first voltage on a first global access line associated with memory planes 372(0) and / or 372(1), and driver circuit 374(1) can drive a second voltage on a third global access line associated with memory planes 372(2) and / or 372(3). In some examples, a pass voltage can be provided on all access lines in addition to the access lines associated with pages of memory planes 372(0)-372(3) to be accessed. Local media controllers 135(0)-135(1), driver circuits 374(0)-374(1) can allow different respective pages and page caches 240(0)-240(3) within different respective blocks of memory cells to be accessed in parallel. For example, a first page of a first block of a first memory plane and a second page of a second block of a second memory plane can be accessed in parallel, regardless of page type.

[0057] Page caches 240(0)-240(3) can provide data to or receive data from local media controllers 135(0)-135(1) during memory access operations in response to signals from the local media controllers 135(0)-135(1) and respective memory planes 372(0)-372(3). Local media controllers 135(0)-135(1) can provide received data to memory sub-system controller 115.

[0058] It should be appreciated that memory device 130 can include more or less than four memory planes, driver circuits, and page caches. It should also be appreciated that respective global access lines can include 8, 16, 32, 64, 128, etc. global access lines. Local media controllers 135(0)-135(1) and driver circuits 374(0)-374(1) can access different respective pages within different respective blocks of different memory planes in parallel when different respective pages have different page types.

[0059] Figure 4is a block diagram illustrating an independent plane architecture in a memory device 130 in accordance with some embodiments of the present disclosure. As illustrated, the memory device 130 includes a plurality of memory planes (i.e., planes 0-5) arranged in two independent plane groups (IPGs) 450 and 452. In other embodiments, there can be any number of memory planes and / or any other number of independent plane groups. Each of the memory planes can include an array of memory cells formed at the intersection of word lines and bit lines. In one embodiment, for example, the memory cells are grouped into blocks, which can be further divided into sub-blocks, with a given word line shared across multiple sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. A group of memory cells associated with a word line within a sub-block is referred to as a physical page. Each physical page in one of the sub-blocks can include multiple page types. For example, a physical page formed of single level cells (SLC) has a single page type referred to as a lower logical page (LP). A multi-level cell (MLC) physical page type can include an LP and an upper logical page (UP), a TLC physical page type is an LP, an UP, and an extra logical page (XP), and a QLC physical page type is an LP, an UP, an XP, and a top logical page (TP). For example, a physical page formed of memory cells of a QLC memory type can have a total of four logical pages, where each logical page can store data different from the data stored in the other logical pages associated with the physical page. Depending on the programming scheme used, each logical page of a memory cell can be programmed in a separate programming pass, or multiple logical pages can be programmed together. For example, in a QLC physical page, the LP can be programmed on one pass, and the UP, XP, and TP can be programmed on a second pass. Other programming schemes are possible.

[0060] In one embodiment, each of the independent plane groups 450 and 452 has an associated independent analog driver circuit 460 and 462. The independent analog driver circuits 460 and 462 can represent the drivers 374(0)-374(1) of Figure 3 In one embodiment, there is a shared common analog circuit 470. The common analog circuit 470 can represent the common analog circuit 370 of Figure 3common circuitry 375. Independent analog driver circuits 460 and 462 and common analog circuitry 470 together form independent planar architecture circuitry 150. Depending on the embodiment, independent planar architecture circuitry 150 can include additional and / or different components. In one embodiment, the memory device further includes common data paths 490 shared by independent planar groups 450 and 452, and a common command interface 495. In one embodiment, independent analog driver circuits 460 and 462 are configured to provide selected analog voltage references received from common analog circuitry 470 to memory planes of independent planar groups 450 and 452 in order to perform memory access operations. For example, common analog circuitry 470 can include a plurality of analog references representing first order references (e.g., bandgap, page buffer reference, temperature meter) and other second order references for the individual analog driver circuits 460 and 462. Common analog circuitry 470 can further include a power on / off detector for resolving when a memory die will be powered on or when there is a power loss, and any other components that can be shared (e.g., performed only once to save power). However, independent analog driver circuits 460 and 462 can include other components (e.g., DC converters, X and Y pad drivers) that operate independently without regard to the other independent planar groups.

[0061] In one embodiment, each independent planar group 450 and 460 of memory device 130 can have a corresponding respective media controller. For example, primary control logic 480 can be associated with independent planar group 450, and secondary control logic 482 can be associated with independent planar group 452. Primary control logic 480 and secondary control logic 482 can represent media controllers 135(0)-135(1) of Figure 3 Each media controller is configured to perform memory access operations on memory planes in the corresponding independent planar group (e.g., cause the corresponding respective analog driver circuit to apply voltage signals received from the common analog circuitry to a certain memory plane or memory planes of the corresponding independent planar group). In certain scenarios, secondary control logic 482 can be disabled for power consumption purposes, and primary control logic 480 can perform operations on memory planes of multiple independent planar groups (i.e., group 450 and group 452). However, when both are active, primary control logic 480 and secondary control logic 482 can perform asynchronous memory access operations on memory planes of each respective independent planar group in parallel (e.g., at least partially overlapping in time), as explained in Figure 5

[0062] Figure 5 ​is a diagram illustrating parallel execution of memory access operations in a memory device having an independent plane architecture in accordance with some embodiments of the present disclosure. When the memory device 130 includes independent plane architecture circuitry 150, the primary control logic 480 and the secondary control logic 482 can perform asynchronous memory access operations on respective independent plane groups as described above. For example, if the primary control logic 480 is performing a program (pgm) operation on the memory planes of the independent plane group 450 (IPG0), the secondary control logic 482 can perform any of a program operation, an erase operation, a read operation, or one or more independent word line (IWL) read operations on the memory planes of the independent plane group 452 (IPG1), as shown at 502. Similarly, if the primary control logic 480 is performing an erase operation on the memory planes of the independent plane group 450 (IPG0), the secondary control logic 482 can perform any of a program operation, an erase operation, a read operation, or one or more independent word line (IWL) read operations on the memory planes of the independent plane group 452 (IPG1), as shown at 504. Additionally, if the primary control logic 480 is performing a read operation on the memory planes of the independent plane group 450 (IPG0), the secondary control logic 482 can perform any of a program operation, an erase operation, a read operation, or one or more independent word line (IWL) read operations on the memory planes of the independent plane group 452 (IPG1), as shown at 506. Furthermore, if the primary control logic 480 is performing one or more independent word line (IWL) read operations on the memory planes of the independent plane group 450 (IPG0), the secondary control logic 482 can perform any of a program operation, an erase operation, a read operation, or one or more independent word line (IWL) read operations on the memory planes of the independent plane group 452 (IPG1), as shown at 508.

[0063] Referring again to Figure 4The memory device 130 incorporates certain design features to reduce noise during concurrent asynchronous memory access operations. In one embodiment, components of the memory device 130 are physically segregated into certain sections. For example, because each of the independent plane groups 450 and 452 and their corresponding analog driver circuits 460 and 462 utilize high current and have low margins, they can each be in separate sections. Additionally, because the data path 490, common analog circuit 470, main control logic 480, secondary control logic 482, and command interface 495 utilize lower current and have higher margins, these components can be disposed together in a section separate from the independent plane groups. The segregation can be achieved by using different voltage sources / regulators, different metal routing, and different UI pads within different sections of the memory device 130. Additionally, there can also be a physical barrier in the substrate between sections (e.g., n-doped regions between p-doped regions where the circuitry is located). The segregation prevents negative side effects associated with cross noise during sensitive phases of asynchronous memory access operations (e.g., when a noisy operation is occurring on the independent plane group 450 and a sensitive operation is occurring concurrently on the independent plane group 452).

[0064] Figure 6 is a flow diagram of an example method of power saving operations in a memory device with independent plane architecture in accordance with some embodiments of the present disclosure. The method 600 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the local media controller 135 of the memory device 130. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the processes illustrated can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. Figure 1

[0065] At operation 605, a request is received. For example, the memory device 130 can receive a plurality of memory access commands / requests to perform corresponding memory access operations. The requests can include respective addresses that identify corresponding locations in a memory array of the memory device 130. Depending on the embodiment, the memory access operations can include read operations, program operations, erase operations, or some other type of operation. In one embodiment, the requests are received at the command interface 495 from a requestor such as the memory interface 113 of the memory sub-system controller 115 or the host system 120.

[0066] ​At operation 610, a determination is made. For example, control logic can determine whether the memory device 130 is configured to utilize independent plane groups. In one embodiment, the memory device 130 can be configured for either of two modes of operation, such as a first mode of operation or a second mode of operation. In the first mode of operation, one or more control logic elements can be enabled in parallel. In one embodiment, both the primary control logic 480 and the secondary control logic 482 are enabled (i.e., activated) to perform respective asynchronous memory access operations on the corresponding independent plane groups 450 and 452. In another embodiment, only one control logic element (e.g., the secondary control logic 482) is enabled in response to a given request, while the other control logic element (e.g., the primary control logic 480) remains available to handle other requests. In the second mode of operation, only one control logic element is enabled, while the remainder of the control logic elements are disabled. In one embodiment, the primary control logic 480 is enabled, and the secondary control logic 482 is disabled (i.e., de-activated). In one embodiment, the mode of operation is set in response to a command or control signal received at the command interface 495 (e.g., from the memory interface 113 of the memory sub-system controller 115 or the host system 120).

[0067] If it is determined that the memory device is configured to utilize independent plane groups, at operation 615, one or more control logic elements are enabled. In one embodiment, both the primary control logic 480 and the secondary control logic 482 are enabled (i.e., activated) to perform respective asynchronous memory access operations on the corresponding independent plane groups 450 and 452. In one embodiment, the primary control logic 480 sends a signal to the secondary control logic 482 to cause the secondary control logic 482 to be activated. In another embodiment, the primary control logic 480 de-asserts a control signal that would otherwise be provided to the analog driver circuit 462. In another embodiment, only one of the primary control logic 480 or the secondary control logic 482 is enabled in response to a given request, while the other control logic element remains available to handle other requests, which can be received subsequently or in parallel.

[0068] At operation 620, parallel memory access operations are performed. For example, the memory device 130 can cause the primary control logic 480 and the secondary control logic 482 to perform asynchronous memory access operations on the memory planes of the independent plane groups 450 and 452 using respective independent analog driver circuits 460 and 462. In one embodiment, the primary control logic 480 can cause the analog driver circuit 460 to apply a reference voltage signal from the common analog circuit 470 to the memory planes of the independent plane group 450, and in parallel (i.e., at least partially overlapping in time) the secondary control logic 482 causes the analog driver circuit 462 to apply a reference voltage signal from the common analog circuit 470 to the memory planes of the independent plane group 452.

[0069] If it is determined at operation 610 that the memory device is not configured to utilize independent plane groups, then at operation 625 only one control logic element is enabled while the rest of the control logic elements are disabled. In one embodiment, the primary control logic 480 is enabled and the secondary control logic 482 is disabled (i.e., de-activated). In one embodiment, the primary control logic 480 sends a signal to the secondary control logic 482 to cause the secondary control logic 482 to be de-activated. In another embodiment, the primary control logic 480 asserts the control signals provided to the analog driver circuit 462.

[0070] At operation 630, sequential memory access operations are performed. For example, the memory device 130 can cause the primary control logic 480 to perform memory access operations sequentially to the memory planes of either of the independent plane groups 450 and 452 using the respective independent analog driver circuit 460 or 462. In one embodiment, the primary control logic 480 can cause the analog driver circuit 460 to apply the reference voltage signal from the common analog circuit 470 to the memory planes of the independent plane group 450, or can cause the analog driver circuit 462 to apply the reference voltage signal from the common analog circuit 470 to the memory planes of the independent plane group 452. As Figure 5 As explained in the description of the first mode of operation, the second mode of operation functions as a legacy mode in which only one of a program operation, an erase operation, a read operation, or one or more independent word line (IWL) read operations can be performed to the memory planes of either of the independent plane group 450 (IPG0) or the independent plane group 452 (IPG1) at a time, as shown at 500.

[0071] Figure 7 An example machine of a computer system 700, within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed, is described. In some embodiments, the computer system 700 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used in performing operations of a controller. In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a capacity of a server or a client machine in a cloud computing infrastructure or environment. Figure 1 Figure 1

[0072] ​​The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0073] Example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0074] Processing device 702 represents one or more general -purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 702 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate over the network 720.

[0075] The data storage system 718 can include a machine-readable storage medium 724 (also known as a computer-readable medium, e.g., a non-transitory computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 can also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and / or main memory 704 can correspond to memory subsystem 110 of Figure 1

[0076] ​Although the machine-readable storage medium 724 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0077] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These

[0078] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0079] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0080] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the methods. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0081] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as a read only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0082] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory device comprising: A memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes; Multiple independent analog driver circuits coupled to the memory array, wherein a corresponding one of the multiple independent analog driver circuits is associated with a corresponding one of the multiple independent plane groups; A common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups; as well as A plurality of control logic elements, wherein a corresponding one of the plurality of control logic elements is associated with a corresponding one of the plurality of independent analog driver circuits and a corresponding one of the plurality of independent plane groups, wherein when the memory device is configured to be in a first operating mode, the plurality of control logic elements are configured to perform asynchronous memory access operations of different types on the memory planes of at least two of the plurality of independent analog driver circuits in parallel.

2. The memory device of claim 1, wherein a first control logic element of the plurality of control logic elements is selectively coupled to each of the plurality of independent analog driver circuits and each of the plurality of independent plane groups.

3. The memory device of claim 2, wherein when the memory device is configured to be in a second operating mode, the first control logic element of the plurality of control logic elements is enabled and the remaining portions of the plurality of control logic elements are disabled, and wherein the first control logic element is configured to perform memory access operations on one or more memory planes of any of the plurality of independent plane groups using one or more of the plurality of independent analog driver circuits.

4. The memory device according to claim 1, further comprising: A common data path, which is shared by the multiple independent plane groups; as well as A common command interface, which is shared by the multiple control logic elements.

5. The memory device of claim 1, wherein each corresponding pair of one of the plurality of independent plane groups and one of the plurality of independent analog driver circuits is isolated from the other pairs of the plurality of independent plane groups and the plurality of independent analog driver circuits, as well as the plurality of control logic elements, to reduce signal noise.

6. The memory device of claim 1, wherein the common analog circuitry includes a plurality of analog voltage references associated with performing memory access operations in the memory device.

7. The memory device of claim 6, wherein the plurality of independent analog driver circuits are configured to provide a selected one of the plurality of analog voltage references received from the common analog circuit to the memory plane of a corresponding one of the plurality of independent plane groups to perform the memory access operation.

8. A memory device comprising: A memory array comprising a plurality of memory planes, wherein a first subset of the plurality of memory planes is associated with a first independent plane group, and a second subset of the plurality of memory planes is associated with a second independent plane group; A first independent analog driver circuit associated with the first independent plane group and a second independent analog driver circuit associated with the second independent plane group; A common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the first and second independent analog driver circuits and the first and second independent plane groups; as well as A first control logic element associated with the first independent analog driver circuit and the first independent plane group, and a second control logic element associated with the second independent analog driver circuit and the second independent plane group, wherein when the memory device is configured to be in a first operating mode, the first control logic element is configured to perform a first asynchronous memory access operation on the first independent plane group using the first independent analog driver circuit, and in parallel, the second control logic element is configured to perform a second asynchronous memory access operation on the second independent plane group using the second independent analog driver circuit, and wherein the first control logic element is selectively coupled to the second independent analog driver circuit and the second independent plane group.

9. The memory device of claim 8, wherein when the memory device is configured to be in a second operating mode, the first control logic element is enabled and the second control logic element is disabled, and wherein the first control logic element is configured to perform memory access operations on one or more memory planes of either the first or second independent analog driver circuits.

10. The memory device of claim 8, further comprising: A common data path, which is shared by the first and second independent plane groups; as well as A common command interface, which is shared by the first and second control logic elements.

11. The memory device of claim 8, wherein the first independent plane group and the first independent analog driver circuit are isolated from the second independent plane group and the second independent analog driver circuit, as well as the first and second control logic elements, to reduce signal noise.

12. The memory device of claim 8, wherein the common analog circuitry includes a plurality of analog voltage references associated with performing memory access operations in the memory device.

13. The memory device of claim 12, wherein the first and second independent analog driver circuits are configured to provide a selected one of the plurality of analog voltage references received from the common analog circuit to the memory plane of the first and second independent plane groups to perform the memory access operation.

14. A method comprising: Receive multiple requests at the memory device to perform different types of memory access operations on the memory array of the memory device, the memory array including multiple memory planes, wherein the multiple memory planes are arranged in multiple independent plane groups, and wherein each of the multiple independent plane groups includes one or more of the multiple memory planes; Determine whether the memory device is configured to utilize an independent plane group; In response to determining that the memory device is configured to utilize independent plane groups, a plurality of control logic elements are enabled, wherein a corresponding one of the plurality of control logic elements is associated with a corresponding one of the plurality of independent plane groups; as well as The plurality of control logic elements are configured to perform different types of memory access operations on the memory planes of two or more of the plurality of independent plane groups using corresponding elements of a plurality of independent analog driver circuits in parallel.

15. The method of claim 14, further comprising: In response to determining that the memory device is not configured to utilize an independent plane group, the first control logic element of the plurality of control logic elements is enabled and the remaining parts of the plurality of control logic elements are disabled; as well as The first control logic element uses one of the plurality of independent analog driver circuits to sequentially perform the memory access operation on the memory plane of one or more of the plurality of independent plane groups.

16. The method of claim 14, wherein the memory device includes common analog circuitry coupled to the memory array, and wherein the common analog circuitry is shared by the plurality of independent plane groups.

17. The method of claim 14, wherein the plurality of requests to perform the memory access operation are received at a common command interface of the memory device shared by the plurality of control logic elements.

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