Semiconductor Structure and Method for Preparing the Same

Abstract

The present application relates to a semiconductor structure and a method for preparing the same, including a first passivation layer and a stacked structure; the stacked structure is located on the upper surface of the first passivation layer and includes a second passivation layer and a hydrogen absorption layer stacked in sequence from bottom to top; wherein hydrogen elements are generated during the formation of the second passivation layer, and the hydrogen absorption layer adsorbs the hydrogen elements generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment. In the semiconductor structure of the present application, the hydrogen absorption layer adsorbs the hydrogen elements generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment, avoiding the problem of negative bias temperature instability caused by a large number of unstable covalent bonds formed due to the entry of hydrogen elements into the device interface, and improving the stability and reliability of the semiconductor structure performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, many devices need to be assembled on a single crystal substrate, and these devices need to be interconnected by wiring. Moreover, with the increase in integration and the reduction of feature size, the wiring density must be increased. Therefore, the passivation layer used for electrical isolation between devices and between wirings is very important. In addition, due to the differences between the semiconductor surface and the internal structure, the surface and internal properties are different, and the surface condition has an important effect on the performance of the device. As long as there is a small amount of contamination on the surface, it will affect the electrical properties of the device surface. Therefore, to improve the stability and reliability of the device performance, the device must be isolated from the surrounding environmental atmosphere to enhance the device's ability to block foreign ion contamination, control and stabilize the characteristics of the semiconductor surface, protect the internal interconnections of the device, and prevent the device from being damaged mechanically and chemically. For this reason, the requirement for surface passivation of semiconductor devices is proposed. Existing semiconductor devices often use a silicon dioxide layer as the surface passivation layer, but the silicon dioxide layer cannot completely block the diffusion of harmful impurities (such as sodium ions) to the silicon surface, seriously affecting the stability of semiconductor devices.

[0003] In traditional technologies, various manufacturing processes for growing surface passivation films are adopted to solve the above problems, and chemical vapor deposition of silicon nitride (Si3N4) is the most applicable. The silicon nitride structure is dense and has good chemical stability, and can effectively block the diffusion of water vapor and mobile ions.

[0004] However, silicon nitride is formed by the chemical reaction of silane (SiH4) and ammonia (NH3) in an environment of about 400°C, which will release a large amount of hydrogen elements; moreover, the passivation heat treatment after the deposition of silicon nitride will also cause the release of a large amount of hydrogen elements already present in the silicon nitride; these hydrogen elements will enter the device interface, forming a large number of unstable covalent bonds, resulting in a very serious problem of negative bias temperature instability. Summary of the Invention

[0005] Based on this, in view of the problems in the above background art, a semiconductor structure and a method for manufacturing the same that can solve the above problems are provided.

[0006] According to some embodiments, on the one hand, this application provides a semiconductor structure, including:

[0007] A first passivation layer;

[0008] A stacked structure, located on the upper surface of the first passivation layer, including a second passivation layer and a hydrogen absorption layer stacked in sequence from bottom to top; wherein,

[0009] Hydrogen is generated during the formation of the second passivation layer;

[0010] The hydrogen absorption layer adsorbs the hydrogen generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment.

[0011] In one embodiment, both the bottom layer and the top layer of the stacked structure are the second passivation layer.

[0012] In one embodiment, the semiconductor structure further includes a third passivation layer;

[0013] The third passivation layer is located on the upper surface of the stacked structure.

[0014] In one embodiment, the thickness of the second passivation layer is greater than the thickness of the hydrogen absorption layer.

[0015] In one embodiment, the second passivation layer includes a silicon nitride layer; the hydrogen absorption layer includes a titanium layer.

[0016] In one embodiment, the first passivation layer includes a silicon dioxide layer.

[0017] According to some embodiments, another aspect of the present application provides a method for manufacturing a semiconductor structure, which is characterized by including the following steps:

[0018] Provide a first passivation layer;

[0019] Form a stacked structure on the upper surface of the first passivation layer, the stacked structure including a second passivation layer and a hydrogen absorption layer stacked in sequence from bottom to top; wherein,

[0020] Hydrogen is generated during the formation of the second passivation layer, and the hydrogen absorption layer adsorbs the hydrogen generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment.

[0021] In one embodiment, the step of forming a stacked structure on the upper surface of the first passivation layer includes the following steps:

[0022] Form the second passivation layer on the upper surface of the first passivation layer;

[0023] Form the hydrogen absorption layer on the upper surface of the second passivation layer;

[0024] Form the second passivation layer on the upper surface of the hydrogen absorption layer.

[0025] In one embodiment, after the step of forming the second passivation layer on the upper surface of the hydrogen absorption layer, the following steps are further included:

[0026] Form the hydrogen absorption layer on the upper surface of the second passivation layer formed in the previous step;

[0027] Form the second passivation layer on the upper surface of the hydrogen absorption layer formed in the previous step;

[0028] Repeat the above steps at least once.

[0029] In one embodiment, the second passivation layer includes a silicon nitride layer.

[0030] In one embodiment, the second passivation layer is formed by a chemical vapor deposition process; the reaction gases in the chemical vapor deposition process include silane and ammonia, and the reaction temperature is 200°C to 600°C.

[0031] In one embodiment, the hydrogen absorption layer includes a titanium layer.

[0032] In one embodiment, the first passivation layer includes a silicon dioxide layer.

[0033] In one embodiment, in the formed stacked structure, the thickness of the second passivation layer is greater than the thickness of the hydrogen absorption layer.

[0034] In one embodiment, after the step of forming the stacked structure on the upper surface of the first passivation layer, the following steps are further included:

[0035] Form a third passivation layer on the upper surface of the stacked structure.

[0036] The disclosed embodiments provided in this application have at least the following advantages:

[0037] In the semiconductor structure of this application, the hydrogen absorption layer adsorbs hydrogen elements generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment, avoiding the problem of negative bias temperature instability caused by a large number of unstable covalent bonds formed due to the entry of hydrogen elements into the device interface, and improving the stability and reliability of the semiconductor structure performance.

[0038] In the preparation method of the semiconductor structure of this application, by forming a hydrogen absorption layer, hydrogen elements generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment are adsorbed, avoiding the problem of negative bias temperature instability caused by a large number of unstable covalent bonds formed due to the entry of hydrogen elements into the device interface, and improving the stability and reliability of the semiconductor structure performance. Description of the Drawings

[0039] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0040] Figure 1 It is a cross-sectional schematic diagram of a traditional semiconductor structure;

[0041] Figure 2 It is a flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0042] Figure 3 It is a cross-sectional schematic diagram of the structure obtained in step S1 in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0043] Figure 4 It is a flowchart of step S2 in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0044] Figure 5 It is a cross-sectional schematic diagram of the structure obtained in step S201 in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0045] Figure 6 It is a cross-sectional schematic diagram of the structure obtained in step S202 in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0046] Figure 7 It is a cross-sectional schematic diagram of the structure obtained in step S203 in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0047] Figure 8 It is a cross-sectional schematic diagram of the structure obtained in step S2 in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0048] Figure 9 It is a cross-sectional schematic diagram of the structure obtained in step S3 in the method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 9 It is also a cross-sectional schematic diagram of the semiconductor structure provided in some embodiments of the present application.

[0049] Explanation of reference numerals:

[0050] 1', 1, the first passivation layer; 2', the passivation film layer; 2, the stacked structure; 201, the second passivation layer; 202, the hydrogen absorption layer; 3, the third passivation layer. Detailed embodiments

[0051] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0053] It should be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first or second may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or part discussed below can be referred to as the second element, component, region, layer, or part; for example, the first passivation layer can be referred to as the second passivation layer, and similarly, the second passivation layer can be referred to as the first passivation layer; the first passivation layer and the second passivation layer are different passivation layers. For example, the first passivation layer can include a silicon dioxide layer, and the second passivation layer can include a silicon nitride layer; or the first passivation layer can include a silicon nitride layer, and the second passivation layer can include a silicon dioxide layer.

[0054] Spatial relationship terms such as "on" can be used herein to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that in addition to the orientation shown in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both the upper and lower orientations. In addition, the device can also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0055] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0056] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, and such variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Accordingly, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the invention.

[0057] To prevent impurities in the external environment from diffusing into the integrated circuit and affecting the device, and to improve the stability and reliability of the device performance, a surface passivation protection film is usually deposited during the chip manufacturing process to block the diffusion of water vapor and mobile ions; among them, silicon nitride (Si3N4) is most suitable due to its dense structure and good chemical stability. As Figure 1 shown, the conventional semiconductor structure includes a first passivation layer 1' and a surface passivation film layer 2' stacked from bottom to top. However, silicon nitride is formed by the chemical reaction of silane (SiH4) and ammonia (NH3) in an environment of about 400 °C, and it will release a large amount of hydrogen elements; moreover, the passivation heat treatment after the deposition of silicon nitride will also cause the release of a large amount of hydrogen elements already present in the silicon nitride; these hydrogen elements will enter the device interface and form a large number of unstable covalent bonds, resulting in a very serious negative bias temperature instability effect.

[0058] Please refer to Figure 2 , to solve the above problems or other problems, according to some embodiments, the present application provides a method for preparing a semiconductor structure, and the method may include the following steps:

[0059] S1: Provide a first passivation layer;

[0060] S2: Form a stacked structure on the upper surface of the first passivation layer, and the stacked structure includes a second passivation layer and a hydrogen absorption layer stacked in sequence from bottom to top.

[0061] Wherein, hydrogen elements are generated during the formation of the second passivation layer, and the hydrogen absorption layer can adsorb the hydrogen elements generated during the formation of the second passivation layer and / or during the subsequent passivation heat treatment process.

[0062] The method for manufacturing the semiconductor structure provided by the above embodiment forms a hydrogen-absorbing layer to adsorb hydrogen generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment, that is, to adsorb hydrogen generated during the formation of the second passivation layer, hydrogen generated during subsequent passivation heat treatment, or hydrogen generated during the formation of the second passivation layer and during subsequent passivation heat treatment, so as to avoid the negative bias temperature instability effect caused by a large number of unstable covalent bonds formed due to hydrogen entering the device interface, and improve the stability and reliability of the semiconductor structure performance.

[0063] In step S1, refer to Figure 2 S1 in Figure 3 , and provide the first passivation layer 1.

[0064] Among them, the material of the first passivation layer 1 may include but is not limited to any one or several of silicon dioxide (SiO2), aluminum oxide (Al2O3), borosilicate glass, phosphosilicate glass (PSG), semi-insulating polysilicon, etc. The present application does not limit the specific material and structure of the first passivation layer 1; specifically, in this embodiment, the material of the first passivation layer 1 is silicon dioxide. Silicon dioxide can control and stabilize the electrical properties of the semiconductor device surface, control and fix positive charges, and reduce the surface recombination rate, so that the device works stably.

[0065] In one example, the first passivation layer 1 may be formed on the surface of a substrate (not shown); the substrate may include but is not limited to a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium nitride substrate, etc.

[0066] For step S2, refer to Figure 2 S2 in Figures 4 to 7 , in one embodiment, step S2 may include the following steps:

[0067] S201: Form a second passivation layer 201 on the upper surface of the first passivation layer 1, as shown in Figure 5 ; specifically, the second passivation layer 201 may be formed by, but is not limited to, physical vapor deposition process or chemical vapor deposition process;

[0068] S202: Form a hydrogen-absorbing layer 202 on the upper surface of the second passivation layer 201, as shown in Figure 6 ; specifically, the hydrogen-absorbing layer 202 may be formed by, but is not limited to, physical vapor deposition process or chemical vapor deposition process;

[0069] S203: Form a second passivation layer 201 on the upper surface of the hydrogen-absorbing layer 202, as shown in Figure 7 .

[0070] Specifically, the second passivation layer 201 may include, but is not limited to, a silicon nitride (Si3N4) layer. The present application does not limit the material and structure of the second passivation layer 201. More specifically, in one embodiment, the second passivation layer 201 includes a silicon nitride layer. Silicon nitride is an inert medium with good chemical stability, better dielectric properties than silicon dioxide, strong sodium resistance, good thermal stability, and a dense structure. In the above embodiment, the silicon nitride layer can not only effectively block the diffusion of water vapor and mobile ions, but also significantly improve the reliability and stability of the device.

[0071] Specifically, the hydrogen absorption layer 202 may include, but is not limited to, a titanium (Ti) layer. The present application does not limit the material and structure of the hydrogen absorption layer 202, and any material with the property of adsorbing hydrogen elements is applicable. More specifically, in one embodiment, the hydrogen absorption layer 202 includes a titanium layer. Titanium has been proven to be a material that can effectively absorb and accumulate hydrogen elements. In the above embodiment, the titanium layer can effectively adsorb the hydrogen elements generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment.

[0072] Specifically, in one embodiment, the second passivation layer 201 is formed by a chemical vapor deposition process.

[0073] With the chemical vapor deposition process, the film deposition device is simple and the reaction source materials required for film deposition are relatively easy to obtain, which can reduce costs. At the same time, with the chemical vapor deposition process, nitride film layers can be manufactured at deposition temperatures much lower than their melting points or decomposition temperatures. Moreover, with the chemical vapor deposition process, its deposition process can be precisely controlled by gas-phase doping, with greater flexibility.

[0074] Specifically, in one embodiment where the second passivation layer 201 is formed by a chemical vapor deposition process, the reaction gases in the chemical vapor deposition process may include, but are not limited to, silane (SiH4) and ammonia (NH3). The present application does not limit the reaction gases in the chemical vapor deposition process. More specifically, the reaction gases in the chemical vapor deposition process in this embodiment include silane and ammonia.

[0075] Specifically, in one embodiment where the second passivation layer 201 is formed by a chemical vapor deposition process, the reaction temperature is 200°C to 600°C, such as 200°C, 300°C, 400°C, 500°C or 600°C, etc. The present application does not limit the reaction temperature for forming the second passivation layer 201 by the chemical vapor deposition process.

[0076] In one embodiment, as Figure 8As shown, steps S202 and S203 can be sequentially repeated at least once after step S203; that is, after step S203, the following steps can also be repeated at least once: forming a hydrogen absorption layer 202 on the upper surface of the second passivation layer 201 formed in step S203; forming a second passivation layer 201 on the upper surface of the hydrogen absorption layer 202 formed in the previous step.

[0077] The semiconductor manufacturing method provided by the above embodiment can form a multi-layer structure in which multiple second passivation layers 201 and hydrogen absorption layers 202 are stacked in sequence. Among them, the multiple second passivation layers 201 can further improve the reliability and stability of the device, and the multiple hydrogen absorption layers 202 can fully adsorb hydrogen elements generated during the formation of the second passivation layer and / or subsequent passivation heat treatment process up and down, thereby avoiding the situation where the single hydrogen absorption layer 202 cannot fully adsorb too much hydrogen element generated during the reaction process due to the single hydrogen absorption layer 202.

[0078] The specific number of times of sequentially repeating steps S202 and S203 after step S203 can be set as needed, and the present application does not limit this. For example, after step S203, steps S202 and S203 can be sequentially repeated once, twice, five times, ten times, fifty times or even more times.

[0079] In the stacked structure 2 formed in one of the embodiments, the thickness of the second passivation layer 201 is greater than the thickness of the hydrogen absorption layer 202.

[0080] Please refer to Figure 9 , in one of the embodiments, after step S2, the following steps can also be included:

[0081] S3: Forming a third passivation layer 3 on the upper surface of the stacked structure 2.

[0082] It should be understood that although Figure 2 and Figure 4 the steps in the flowcharts are sequentially shown according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 2 and Figure 4 at least a part of the steps in

[0083] Please continue to refer to Figures 8 to 9, this application also provides a semiconductor structure according to some embodiments, including a first passivation layer 1 and a stacked structure 2, where the stacked structure 2 is located on the upper surface of the first passivation layer 1.

[0084] Specifically, the stacked structure 2 includes a second passivation layer 201 and a hydrogen absorption layer 202 stacked in sequence from bottom to top; among them, hydrogen elements are generated during the formation of the second passivation layer 201; the hydrogen absorption layer 202 can adsorb the hydrogen elements generated during the formation of the second passivation layer 201 and / or during subsequent passivation heat treatment.

[0085] The semiconductor structure provided by the above embodiments adsorbs the hydrogen elements generated during the formation of the second passivation layer and / or during subsequent passivation heat treatment through the hydrogen absorption layer, that is, adsorbs the hydrogen elements generated during the formation of the second passivation layer, the hydrogen elements generated during subsequent passivation heat treatment, or the hydrogen elements generated during the formation of the second passivation layer and subsequent passivation heat treatment, avoiding the problem of negative bias temperature instability caused by a large number of unstable covalent bonds formed when hydrogen elements enter the device interface, and improving the stability and reliability of the semiconductor structure performance.

[0086] In one of the embodiments, the material of the first passivation layer 1 may include but is not limited to any one or several of silicon dioxide (SiO2), aluminum oxide (Al2O3), borosilicate glass, phosphosilicate glass (PSG), semi-insulating polysilicon, etc. This application does not limit the specific material and structure of the first passivation layer 1; specifically, in this embodiment, the material of the first passivation layer 1 is silicon dioxide. Silicon dioxide can control and stabilize the electrical properties of the semiconductor device surface, control and fix positive charges, and reduce the surface recombination rate, enabling the device to operate stably.

[0087] In one example, the first passivation layer 1 may be formed on the surface of a substrate (not shown); the substrate may include but is not limited to a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium nitride substrate, etc.

[0088] In one of the embodiments, the second passivation layer 201 may include but is not limited to a silicon nitride layer. This application does not limit the material and structure of the second passivation layer 201; more specifically, in one of the embodiments, the second passivation layer 201 includes a silicon nitride layer. Silicon nitride is an inert medium with good chemical stability, better dielectric properties than silicon dioxide, strong sodium resistance, good thermal stability, and a dense structure. The above embodiments can not only effectively block the diffusion of water vapor and mobile ions through the silicon nitride layer, but also significantly improve the reliability and stability of the device.

[0089] In one embodiment, the hydrogen-absorbing layer 202 may include, but is not limited to, a titanium layer. The present application does not limit the material and structure of the hydrogen-absorbing layer 202. More specifically, in one embodiment, the hydrogen-absorbing layer 202 includes a titanium layer. Titanium has been proven to be a material that can effectively absorb and aggregate hydrogen elements. In the above embodiment, the hydrogen elements generated during the formation of the second passivation layer and / or during the subsequent passivation heat treatment process can be effectively adsorbed through the titanium layer.

[0090] Please continue to refer to Figure 9 , in one embodiment, the stacked structure 2 may include a plurality of hydrogen-absorbing layers 202 and second passivation layers 201 stacked from bottom to top. The plurality of hydrogen-absorbing layers 202 and second passivation layers 201 stacked from bottom to top are located on the upper surface of the second passivation layer 201 close to the first passivation layer 1.

[0091] The semiconductor structure provided by the above embodiment has a multi-layer structure in which a plurality of second passivation layers 201 - hydrogen-absorbing layers 202 are stacked in sequence. Among them, the plurality of second passivation layers 201 can further improve the reliability and stability of the device. The plurality of hydrogen-absorbing layers 202 can fully adsorb the hydrogen elements generated during the formation of the second passivation layer and / or during the subsequent passivation heat treatment process up and down, thereby avoiding the situation where the single hydrogen-absorbing layer 202 cannot fully adsorb too many hydrogen elements generated during the reaction process.

[0092] As Figures 8 to 9 shown, in one embodiment, the bottom layer and the top layer of the stacked structure 2 may both be the second passivation layer 201.

[0093] For the semiconductor structure provided by the above embodiment, using the second passivation layer 201 as the top layer of the stacked structure 2 can further ensure the reliability and stability of the device.

[0094] The thickness of the second passivation layer 201 may be greater than the thickness of the hydrogen-absorbing layer 202, or may be less than or equal to the thickness of the hydrogen-absorbing layer 202. The present application does not limit the size relationship between the thickness of the second passivation layer 201 and the thickness of the hydrogen-absorbing layer 202. Specifically, in one embodiment, the thickness of the second passivation layer 201 may be greater than the thickness of the hydrogen-absorbing layer 202.

[0095] Please continue to refer to Figure 9 , in one embodiment, the semiconductor structure may further include a third passivation layer 3. Specifically, the third passivation layer 3 is located on the upper surface of the stacked structure 2.

[0096] The material of the third passivation layer 3 may include, but is not limited to, any one or several of silicon dioxide (SiO2), aluminum oxide (Al2O3), borosilicate glass, phosphosilicate glass (PSG), semi-insulating polysilicon, etc. The present application does not limit the specific material and structure of the third passivation layer 3.

[0097] In the description of this specification, the description referring to terms such as "one of the embodiments" or "some embodiments" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0098] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0099] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, comprising: a first passivation layer; a stacked structure located on the upper surface of the first passivation layer, including a second passivation layer and a hydrogen-absorbing layer stacked in sequence from bottom to top; wherein, hydrogen elements are generated during the formation process of the second passivation layer; the hydrogen-absorbing layer adsorbs the hydrogen elements generated during the formation process of the second passivation layer and / or during subsequent passivation heat treatment; the bottom layer and the top layer of the stacked structure are both the second passivation layer.

2. The semiconductor structure according to claim 1, characterized in that, further comprising a third passivation layer; the third passivation layer is located on the upper surface of the stacked structure.

3. The semiconductor structure according to claim 1, characterized in that, the thickness of the second passivation layer is greater than the thickness of the hydrogen-absorbing layer.

4. The semiconductor structure according to claim 1, characterized in that, the second passivation layer includes a silicon nitride layer; the hydrogen-absorbing layer includes a titanium layer.

5. The semiconductor structure according to claim 4, characterized in that, the first passivation layer includes a silicon dioxide layer.

6. A method for manufacturing a semiconductor structure, characterized in that, comprising the following steps: providing a first passivation layer; forming a stacked structure on the upper surface of the first passivation layer, the stacked structure including a second passivation layer and a hydrogen-absorbing layer stacked in sequence from bottom to top; wherein, hydrogen elements are generated during the formation process of the second passivation layer, and the hydrogen-absorbing layer adsorbs the hydrogen elements generated during the formation process of the second passivation layer and / or during subsequent passivation heat treatment; the step of forming the stacked structure on the upper surface of the first passivation layer includes the following steps: forming the second passivation layer on the upper surface of the first passivation layer; forming the hydrogen-absorbing layer on the upper surface of the second passivation layer; forming the second passivation layer on the upper surface of the hydrogen-absorbing layer.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, after the step of forming the second passivation layer on the upper surface of the hydrogen-absorbing layer, the following steps are further included: forming the hydrogen-absorbing layer on the upper surface of the second passivation layer formed in the previous step; forming the second passivation layer on the upper surface of the hydrogen-absorbing layer formed in the previous step; repeating the above steps at least once.

8. The method for manufacturing a semiconductor structure according to claim 6 or 7, characterized in that, the second passivation layer includes a silicon nitride layer.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, the second passivation layer is formed by a chemical vapor deposition process; the reaction gases in the chemical vapor deposition process include silane and ammonia, and the reaction temperature is 200°C to 600°C.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, the hydrogen-absorbing layer includes a titanium layer.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, the first passivation layer includes a silicon dioxide layer.

12. The method for manufacturing a semiconductor structure according to claim 6 or 7, characterized in that, in the formed stacked structure, the thickness of the second passivation layer is greater than the thickness of the hydrogen-absorbing layer.

13. The method for manufacturing a semiconductor structure according to claim 6, wherein, after the step of forming a stacked structure on the upper surface of the first passivation layer, the following steps are further included: forming a third passivation layer on the upper surface of the stacked structure.

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