Semiconductor Structure and Method for Preparing the Same

Abstract

The present application provides a semiconductor structure and a method for manufacturing the same, relating to the field of semiconductor technology, and solving the technical problems that during wafer acceptance testing, test probes are easily contaminated or even damaged. The semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, and a redistribution layer disposed on the dielectric layer; the substrate includes a dicing street area, and pads are provided on the substrate corresponding to the dicing street area. The dielectric layer has bumps disposed on the pads and a first opening disposed on the outer periphery of the bumps, and the first opening exposes a part of the pads; the redistribution layer has extensions filled in the first opening and disposed on the bumps, and the extensions are electrically connected to the pads. The test probe abuts against the upper surface of the extensions on the bumps, thereby enabling the acceptance testing of the wafer, avoiding the problems that the test probe is easily contaminated or even damaged, improving the working reliability of the test probe, and prolonging the service life of the test probe.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] A Re-distribution Layer (RDL) is to change the contact positions of the circuit node positions (I / O pads) of an originally designed Integrated Circuit (IC) through a wafer-level metal wiring process and a conductive bump process, so that the IC can be suitable for different packaging forms. The wafer-level metal wiring process is to coat an insulating protective layer on the IC, then define a new wire pattern by exposure and development, and then use electroplating technology to fabricate a new metal line to connect the original aluminum pad and the new conductive bump or copper pad to achieve the purpose of redistributing the circuit nodes. However, in the related art RDL structure, during the wafer acceptance test using test probes, the test probes are prone to contamination and even damage. Summary of the Invention

[0003] In view of the above problems, embodiments of this application provide a semiconductor structure and a method for manufacturing the same, which can avoid the problems of easy contamination and even damage of the test probes, improve the working reliability of the test probes, and extend the service life of the test probes.

[0004] To achieve the above object, embodiments of this application provide the following technical solutions:

[0005] In a first aspect, embodiments of this application provide a semiconductor structure, which includes: a substrate, a dielectric layer disposed on the substrate, and a redistribution layer disposed on the dielectric layer; the substrate includes a dicing street area, and pads are provided in the substrate corresponding to the dicing street area; the dielectric layer has bumps disposed on the pads and a first opening disposed on the outer periphery of the bumps, and the first opening exposes a part of the pads; the redistribution layer has an extension portion filled in the first opening and disposed on the bumps, and the extension portion is electrically connected to the pads.

[0006] For the semiconductor structure as described above, the first opening is an annular opening surrounding the outer periphery of the bump.

[0007] For the semiconductor structure as described above, the cross-sectional shape of the bump along the thickness direction perpendicular to the dielectric layer is one of a circle, a square, and a rectangle.

[0008] For the semiconductor structure as described above, there are at least two first openings, and at least two first openings are spaced along the circumferential direction of the bump.

[0009] The semiconductor structure as described above, wherein the centers of the bumps and the pads lie on the same straight line perpendicular to the substrate.

[0010] The semiconductor structure as described above, wherein the projected area of the extension on the bump on the substrate is larger than the projected area of the extension within the first opening on the substrate.

[0011] The semiconductor structure as described above, wherein the height of the bump is greater than or equal to the height of the dielectric layer.

[0012] The semiconductor structure as described above, wherein the top surface of the bump is flush with the upper surface of the dielectric layer.

[0013] The semiconductor structure as described above, wherein the bump and the dielectric layer are formed by a single patterning process.

[0014] The semiconductor structure as described above, wherein the projections of the first opening and the bump on the substrate cover the projection of the pad on the substrate.

[0015] The semiconductor structure as described above, wherein the redistribution layer is an aluminum wiring layer or a copper wiring layer.

[0016] The semiconductor structure as described above, wherein the dielectric layer includes a passivation layer, a first insulating layer, and a seed layer stacked in sequence, and the redistribution layer is disposed on the seed layer.

[0017] The semiconductor structure as described above, wherein the substrate further includes an array region spaced apart from the dicing lane region, a second insulating layer is disposed on the redistribution layer corresponding to the array region, a second opening penetrating the second insulating layer is formed on the second insulating layer, the second opening exposes a part of the redistribution layer, and a bonding wire is disposed within the second opening, and one end of the bonding wire is electrically connected to the redistribution layer; wherein, the projection of the second opening on the substrate is different in position from the projection of the first opening on the substrate.

[0018] Compared with the related art, the semiconductor structure provided by the embodiments of the present application has at least the following advantages:

[0019] In the semiconductor structure provided by the embodiment of the present application, by providing a redistribution layer on the dielectric layer, the redistribution layer can change the positions of the circuit nodes in the integrated circuit, achieving the purpose of redistributing the circuit nodes, so that the semiconductor structure can adapt to different packaging forms and improve the versatility of the semiconductor structure. Additionally, by providing bumps on the pads of the substrate corresponding to the saw street area, a first opening is provided on the outer periphery of the bumps, and the first opening exposes a part of the pads. The redistribution layer has an extension portion filled in the first opening and disposed on the bumps, and the extension portion is electrically connected to the pads. When performing an acceptance test on the wafer through a test probe, the test probe only needs to contact the extension portion on the bumps to achieve the acceptance test of the wafer. Since the extension portion on the bumps facilitates the probing of the test probe, it can avoid problems such as contamination and even damage of the test probe due to difficult probing, thereby improving the working reliability of the test probe and extending the service life of the test probe.

[0020] In a second aspect, the embodiment of the present application further provides a method for manufacturing a semiconductor structure, which includes: providing a substrate, the substrate includes a saw street area, and pads are provided in the substrate corresponding to the saw street area; forming a dielectric layer on the substrate, the dielectric layer has bumps disposed on the pads and a first opening disposed on the outer periphery of the bumps, and the first opening exposes a part of the pads; forming a redistribution layer on the dielectric layer, the redistribution layer has an extension portion filled in the first opening and disposed on the bumps, and the extension portion is electrically connected to the pads.

[0021] For the method for manufacturing the semiconductor structure as described above, forming a dielectric layer on the substrate specifically includes:

[0022] forming a passivation layer on the substrate; forming a first insulating layer on the passivation layer; forming a first opening that penetrates the first insulating layer, the passivation layer, and a part of the substrate on the first insulating layer, and the first opening exposes a part of the pads; forming a seed layer on the first insulating layer and the pads, and the passivation layer, the first insulating layer, and the seed layer form the dielectric layer, and the dielectric layer located on the pads forms the bumps; forming a redistribution layer on the seed layer, the redistribution layer has an extension portion filled in the first opening and located on the bumps, and the extension portion is electrically connected to the pads.

[0023] The method for manufacturing the semiconductor structure as described above, after forming a redistribution layer on the seed layer, the redistribution layer has a filling portion in the first opening and an extension on the bump, after the extension is electrically connected to the pad, further includes: forming a second insulating layer on the redistribution layer; forming a second opening on the second insulating layer to expose a part of the redistribution layer, a bonding wire is disposed in the second opening, the bonding wire is electrically connected to the redistribution layer, and a projection position of the second opening on the substrate is different from a projection position of the first opening on the substrate.

[0024] The method for manufacturing the semiconductor structure as described above, after forming a second insulating layer on the redistribution layer, further includes: removing the second insulating layer corresponding to the dicing street region to expose the redistribution layer corresponding to the dicing street region.

[0025] The beneficial effects of the method for manufacturing the semiconductor structure provided by the embodiments of the present application are the same as those of the above semiconductor structure, and will not be elaborated herein.

[0026] In addition to the technical problems solved by the embodiments of the present application, the technical features constituting the technical solutions, and the beneficial effects brought by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the method for manufacturing the same provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 FIG. 18 is a schematic structural diagram of a semiconductor structure in the related art;

[0029] Figure 2 FIG. 22 is a top view schematic diagram of a redistribution layer in the semiconductor structure in the related art;

[0030] Figure 3 FIG. 26 is a partial structural schematic diagram of forming a first opening on a dielectric layer in the semiconductor structure in the related art;

[0031] Figure 4 FIG. 30 is a partial structural schematic diagram of forming a redistribution layer in the first opening in the semiconductor structure in the related art;

[0032] Figure 5Schematic structural diagram of the semiconductor structure provided by the embodiment of the present application;

[0033] Figure 6 Top view schematic diagram of the redistribution layer in the semiconductor structure provided by the embodiment of the present application;

[0034] Figure 7 Partial structural schematic diagram of forming a first opening and a bump on a dielectric layer in the semiconductor structure provided by the embodiment of the present application;

[0035] Figure 8 Partial structural schematic diagram of forming a redistribution layer in the semiconductor structure provided by the embodiment of the present application;

[0036] Figure 9 Flow schematic diagram of the manufacturing method of the semiconductor structure provided by the embodiment of the present application.

[0037] Reference numerals:

[0038] 100 - Substrate; 110 - Pad;

[0039] 200 - Dielectric layer; 210 - Passivation layer;

[0040] 220 - First insulating layer; 230 - Seed layer;

[0041] 201 - Bump; 202 - First opening;

[0042] 300 - Redistribution layer; 310 - Extension;

[0043] 320 - Sidewall; 400 - Second insulating layer;

[0044] 410 - Second opening. Detailed implementation manners

[0045] Figure 1 Schematic structural diagram of the semiconductor structure in the related art; Figure 2 Top view schematic diagram of the redistribution layer in the semiconductor structure in the related art; Figure 3 Partial structural schematic diagram of forming a first opening on a dielectric layer in the semiconductor structure in the related art; Figure 4 Partial structural schematic diagram of forming a redistribution layer in the first opening in the semiconductor structure in the related art.

[0046] Such as Figures 1 to 4As shown, in the related art, a semiconductor structure includes a substrate 100 and a dielectric layer 200 disposed on the substrate 100. The substrate 100 includes a plurality of array regions and a scribe lane region disposed between two adjacent array regions. Among them, the array region is represented by A, and the scribe lane region is represented by B. After the fabrication of each film layer of the semiconductor structure, and after packaging, molding, etc. are completed, cutting is performed at each scribe lane region B to form a plurality of independent dies; wherein, a plurality of spaced pads 110 are provided in the substrate 100, and a first opening 202 exposing the pads 110 is provided on the dielectric layer 200 corresponding to the scribe lane region B. A redistribution layer 300 is formed on the dielectric layer 200 and in the first opening 202. Since the redistribution layer 300 needs to fill the first opening 202, a depression and sidewalls 320 are formed at the position of the redistribution layer 300 corresponding to the first opening. It can be understood that the top surface of the depression is not flush with the sidewalls 320. The redistribution layer 300 is electrically connected to the pads 110. When performing an acceptance test on the wafer, the test probe only needs to contact the redistribution layer 300 at the first opening 202 to achieve the acceptance test of the wafer. However, since the redistribution layer 300 corresponding to the first opening 202 has a depression and sidewalls 320, and there are multiple probes arranged in a row on the test probe. When the test probe pierces into the redistribution layer 300 corresponding to the first opening, the test probe cannot pierce into the depression, and the width of the sidewalls 320 formed by the redistribution layer 300 corresponding to the first opening is too small. The test probe needs to be tilted at a certain angle to pierce into the side surface of the sidewalls 320. In this way, the depth of penetration of each probe on the test probe into the sidewalls 320 will be different. When the test probe is taken out, the probe that pierces deeper into the sidewalls 320 will bring out some debris of the redistribution layer 300, such as aluminum chips, etc., causing contamination of the test probe or the wafer, and even causing damage to the test probe.

[0047] In view of this, an embodiment of the present application provides a semiconductor structure and a preparation method thereof. In this semiconductor structure, by providing bumps on the pads of the substrate corresponding to the scribe lane region, a first opening is provided on the outer periphery of the bumps, and the first opening exposes a part of the pads. The redistribution layer has an extension portion filled in the first opening and disposed on the bumps, and the extension portion is electrically connected to the pads. When performing an acceptance test on the wafer through a test probe, the test probe only needs to contact the extension portion on the bumps to achieve the acceptance test of the wafer. Since the extension portion on the bumps facilitates the piercing of the test probe, the problem of contamination and even damage of the test probe caused by difficult piercing of the test probe can be avoided, thereby improving the working reliability of the test probe and extending the service life of the test probe.

[0048] In order to make the above objects, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0049] Figure 5 Structural schematic diagram of the semiconductor structure provided by the embodiment of the present application; Figure 6 Top view schematic diagram of the redistribution layer in the semiconductor structure provided by the embodiment of the present application; Figure 7 Partial structural schematic diagram of the semiconductor structure provided by the embodiment of the present application in which a first opening and bumps are formed on the dielectric layer; Figure 8 Partial structural schematic diagram of the semiconductor structure provided by the embodiment of the present application in which the redistribution layer is formed.

[0050] As Figures 5 to 8 shown, the semiconductor structure provided by the embodiment of the present application includes: a substrate 100, a dielectric layer 200 disposed on the substrate 100, and a redistribution layer 300 disposed on the dielectric layer 200.

[0051] It can be understood that the substrate includes a plurality of array regions (denoted by A) arranged at intervals and a scribe lane region (denoted by B) disposed between two adjacent array regions A. Most of the wafer testing and acceptance are carried out in the scribe lane region B to avoid damage to the wafer corresponding to the array region A caused by testing. After the testing is completed, cutting is performed from the scribe lane region B to form a plurality of independent die.

[0052] Bond pads 110 are provided in the substrate 100 corresponding to both the array region A and the scribe lane region B. For example, a plurality of bond pads of different sizes are provided in the substrate corresponding to the array region A, and the sizes of the bond pads range from several nanometers to several micrometers; a plurality of independently provided bond pads are also provided in the substrate corresponding to the scribe lane region B, and the size thereof can be 50×40 micrometers.

[0053] Among them, the number of bond pads 110 in the substrate 100 can be set according to actual needs. Figure 5 Only one bond pad 110 is shown in the scribe lane region B.

[0054] The dielectric layer 200 corresponding to the scribe lane region B has bumps 201 disposed on the bond pads 110 and a first opening 202 disposed on the outer periphery of the bumps 201, and the first opening 202 exposes a part of the bond pads 110; the redistribution layer 300 has an extension 310 filled in the first opening 202 and disposed on the bumps 201, and the extension 310 is electrically connected to the bond pads 110.

[0055] It is understandable that the substrate 100 can be made of a crystalline semiconductor material. For example, the substrate 100 can be a silicon (Si) substrate. The substrate 100 can also be a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, etc. In this regard, the embodiments of the present application do not make specific limitations.

[0056] In addition, the dielectric layer 200 is formed on the upper surface of the substrate 100. The portion of the dielectric layer 200 corresponding to the pad 110 forms bumps 201 and a first opening 202 provided on the outer periphery of the bumps 201. Among them, the first opening 202 exposes a part of the pad 110.

[0057] The redistribution layer 300 is formed on the dielectric layer 200. By providing the redistribution layer 300 on the dielectric layer 200, the redistribution layer 300 can change the positions of the circuit nodes in the integrated circuit, achieving the purpose of redistributing the circuit nodes, so that the semiconductor structure can adapt to different packaging forms and improve the versatility of the semiconductor structure.

[0058] In addition, the redistribution layer 300 formed on the dielectric layer 200 corresponding to the scribe lane area B has an extension portion filled in the first opening 202 and an extension portion provided on the bump 201. Moreover, the extension portion filled in the first opening 202 is formed on the pad 110. Therefore, the extension portion filled in the first opening 202 can be electrically connected to the pad 110, so that the extension portion provided on the bump 201 and the redistribution layer 300 other than the extension portion 310 are electrically connected to the pad 110.

[0059] In this way, when the wafer is tested and accepted, the test probe can be inserted into the upper surface of the extension portion on the bump 201. When each probe in the test probe is inserted into the extension portion, the insertion depth is basically the same, and it is not necessary to insert too deep to test the electrical properties of the extension portion 310, so as to realize the test and acceptance of the wafer. Therefore, the problem that the test probe is easily contaminated or even damaged during the wafer test and acceptance can be solved, the working reliability of the test probe is improved, and the service life of the test probe is extended.

[0060] In addition, the redistribution layer 300 can include, but is not limited to, an aluminum (Al) wiring layer. In other examples, the redistribution layer 300 can also be a copper wiring layer, etc. In this regard, the present embodiment does not make specific limitations.

[0061] The semiconductor structure provided by the embodiment of the present application is configured such that bumps 201 are disposed on the pads 110 of the substrate 100. A first opening 202 is provided on the outer periphery of the bumps 201, and the first opening 202 exposes a part of the pads 110. The redistribution layer 300 has an extension 310 filled in the first opening 202 and disposed on the bumps 201, and the extension 310 is electrically connected to the pads 110. When performing an acceptance test on the wafer through a test probe, the test probe only needs to contact the extension 310 on the bumps 201 to achieve the acceptance test of the wafer. Since the extension 310 on the bumps 201 facilitates the needle insertion of the test probe, it is possible to avoid problems such as contamination and even damage of the test probe due to difficult needle insertion, thereby improving the working reliability of the test probe and extending the service life of the test probe.

[0062] As an alternative embodiment, the first opening 202 is an annular opening surrounding the outer periphery of the bumps 201. In this way, the area of the exposed pads 110 can be increased, so that the area of the extension 310 formed at the first opening 202 is relatively large, thereby improving the reliability of the electrical connection between the extension 310 and the pads 110.

[0063] It can be understood that the cross-sectional shape of the bumps 201 in the thickness direction perpendicular to the dielectric layer 200 can be one of shapes such as circular, square, rectangular, elliptical, trapezoidal, etc.

[0064] Preferably, the cross-sectional shape of the bumps 201 in the thickness direction perpendicular to the dielectric layer 200 is square. In this way, the width of the first opening 202 in the extending direction is equal, so that the width of the extension 310 formed in the first opening 202 is consistent, in order to improve the reliability of the electrical connection between the extension 310 around the periphery in the first opening 202 and the pads 110.

[0065] As another alternative embodiment, the first opening 202 is at least two, and the at least two first openings 202 are arranged at intervals in the circumferential direction of the bumps 201. In this way, the area of the bumps 201 can be increased, and thus the area of the extension 310 on the bumps 201 can be increased, facilitating the insertion of the test probe.

[0066] Exemplarily, the first opening 202 can be two, three, or more, etc. The multiple first openings 202 are arranged at equal intervals in the circumferential direction of the bumps 201.

[0067] In one example, the center of the bumps 201 and the center of the pads 110 can be located on the same straight line perpendicular to the substrate 100. In this way, the bumps 201 are located at the center position of the pads 110.

[0068] In addition, the projected area of the extension on the bump 201 on the substrate 100 is larger than the projected area of the extension in the first opening 202 on the substrate 100, so that the extension on the bump 201 has sufficient area to accommodate the penetration of the test probe.

[0069] To facilitate the penetration of the test probe into the extension on the bump 201, the height of the bump 201 can be greater than or equal to the height of the dielectric layer 200. In this way, after the extension is formed on the bump 201, it is convenient for the test probe to penetrate for testing.

[0070] Exemplarily, the top surface of the bump 201 is flush with the upper surface of the dielectric layer 200. In this way, the upper surfaces of the redistribution layer 300 formed on the dielectric layer 200 and the extension 310 on the bump 201 are flush, which can improve the aesthetics of the semiconductor structure.

[0071] It can be understood that the bump 201 and the dielectric layer 200 can be formed by a single lithography process to reduce the processing steps of the semiconductor structure and save processing costs.

[0072] The projections of the first opening 202 and the bump 201 on the substrate 100 cover the projection of the pad 110 on the substrate 100. In this way, the areas of the extension in the first opening 202 and the extension on the bump 201 can be increased to improve the connection reliability between the extension 310 and the pad 110.

[0073] In one example, the dielectric layer 200 includes a passivation layer 210, a first insulating layer 220, and a seed layer 230 that are sequentially stacked, and the redistribution layer 300 is disposed on the seed layer 230.

[0074] Among them, the passivation layer 210 includes, but is not limited to, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0075] In one example, the first insulating layer 220 includes, but is not limited to, a polyimide layer or a polybenzoxazole layer.

[0076] The seed layer 230 is located on the upper surface of the first insulating layer 220 and the upper surface of the pad 110, and the redistribution layer 300 is located on the upper surface of the seed layer 230. The seed layer 230 can include, but is not limited to, a titanium (Ti) layer or a titanium nitride (TiN) layer, etc.

[0077] A second insulating layer 400 is provided on the redistribution layer 300 corresponding to the array region A. The second insulating layer 400 has a second opening 410 penetrating through the second insulating layer 400. The second opening 410 exposes a part of the redistribution layer 300, and a bonding wire is provided in the second opening 410. One end of the bonding wire is electrically connected to the redistribution layer 300.

[0078] Among them, the projection of the second opening 410 on the substrate 100 is in a different position from the projection of the first opening 202 on the substrate 100.

[0079] It can be understood that by providing the second opening 410 on the second insulating layer 400, the second opening 410 can be set at a specified position as needed to meet different packaging forms, so as to improve the versatility of the semiconductor structure.

[0080] In one example, the second insulating layer 400 includes, but is not limited to, a polyimide layer or a polybenzoxazole layer.

[0081] In addition, the bonding wire can include, but is not limited to, a bonding wire made of a conductive material such as a copper wire, an aluminum wire, or a gold wire.

[0082] Figure 9 It is a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0083] As Figure 9 shown, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, and the steps thereof include:

[0084] Step S101: Provide a substrate, the substrate includes a dicing street area, and pads are provided on the substrate corresponding to the dicing street area.

[0085] Among them, the substrate can include, but is not limited to, a silicon substrate; in addition, the pads can be made of a conductive material such as copper, aluminum (Al), gold, or silver.

[0086] Step S102: Form a dielectric layer on the substrate, the dielectric layer has bumps provided on the pads and a first opening provided on the outer periphery of the bumps, and the first opening exposes part of the pads.

[0087] Step S103: Form a redistribution layer on the dielectric layer, the redistribution layer has an extension portion that fills the first opening and is provided on the bumps, and the extension portion is electrically connected to the pads.

[0088] In the method for manufacturing the above semiconductor structure, first, by disposing a redistribution layer on the dielectric layer, the redistribution layer can change the positions of the circuit nodes in the integrated circuit, achieving the purpose of redistributing the circuit nodes, so that the semiconductor structure can adapt to different packaging forms and improve the versatility of the semiconductor structure. Additionally, by disposing bumps on the pads and a first opening disposed on the outer periphery of the bumps, the first opening exposes a portion of the pads. The redistribution layer has an extension portion filled in the first opening and disposed on the bumps, and the extension portion is electrically connected to the pads. When performing an acceptance test on the wafer through a test probe, the test probe only needs to contact the extension portion on the bumps to achieve the acceptance test of the wafer. Since the extension portion on the bumps facilitates the probing of the test probe, problems such as contamination or even damage of the test probe caused by difficult probing can be avoided, thereby improving the working reliability of the test probe and extending the service life of the test probe.

[0089] Wherein, forming a dielectric layer on the substrate specifically includes:

[0090] Forming a passivation layer on the substrate.

[0091] It can be understood that the passivation layer covers the upper surface of the substrate. The passivation layer can include a single-layer structure or a stacked structure of multiple materials. The passivation layer can include, but is not limited to, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0092] Forming a first insulating layer on the passivation layer. Exemplarily, the first insulating layer can be formed on the passivation layer by, but not limited to, a spin coating process.

[0093] Forming a first opening penetrating the first insulating layer, the passivation layer, and a portion of the substrate on the first insulating layer, the first opening exposing a portion of the pads.

[0094] In one example, the first insulating layer, the passivation layer, and a portion of the substrate can be exposed and developed by, but not limited to, a photolithography process to form the first opening. Of course, in other examples, the first insulating layer, the passivation layer, and a portion of the substrate can also be etched to form the first opening.

[0095] Forming a seed layer on the first insulating layer and the pads. Wherein, the passivation layer, the first insulating layer, and the seed layer form the dielectric layer, and the dielectric layer located on the pads forms the bumps, and the first opening surrounds the outer periphery of the bumps.

[0096] Exemplarily, the seed layer can be formed by electroplating or sputtering processes. The seed layer can include at least one of a titanium layer or a titanium nitride layer.

[0097] After that, forming a redistribution layer on the seed layer. The redistribution layer has an extension portion filling the first opening and located on the bumps, and the extension portion is electrically connected to the pads.

[0098] Among them, the redistribution layer can be formed by, but not limited to, electroplating process. The redistribution layer can include an aluminum wiring layer or can be a copper wiring layer, etc.

[0099] A redistribution layer is formed on the seed layer. The redistribution layer has a portion filling the first opening and an extension portion located on the bump. After the extension portion is electrically connected to the pad, it further includes:

[0100] A second insulating layer is formed on the redistribution layer.

[0101] Exemplarily, the second insulating layer can be formed by, but not limited to, spin coating process. The second insulating layer can include, but not limited to, a polyimide or polybenzoxazole layer.

[0102] And a photolithography process can be used to expose and develop the second insulating layer to form a second opening on the second insulating layer, exposing a part of the redistribution layer. There is a bonding wire in the second opening. The bonding wire is electrically connected to the redistribution layer, and the projection position of the second opening on the substrate is different from the projection position of the first opening on the substrate.

[0103] Of course, an etching process can also be used to etch the second insulating layer to form a second opening on the second insulating layer.

[0104] It can be understood that one end of the bonding wire is located in the second opening and is electrically connected to the redistribution layer, while the other end of the bonding wire is electrically connected to the interface of other products to achieve a re-layout of the circuit interface.

[0105] Exemplarily, a wire bond process can be used to electrically connect the bonding wire to the redistribution layer.

[0106] Further, continue to use photolithography to expose and develop the second insulating layer to remove the second insulating layer corresponding to the dicing street area B, so as to expose the redistribution layer corresponding to the dicing street area B, and retain the second insulating layer corresponding to the array area A.

[0107] In this way, when the wafer needs to be subjected to an acceptance test, the test probe can be inserted into the extension portion on the bump in the dicing street area B, so as to avoid the technical problems that the test probe is easily contaminated or even damaged, thereby improving the working reliability of the test probe and extending the service life of the test probe.

[0108] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0109] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0110] In the description of this specification, the description with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of this application. In this specification, the illustrative expression of the above terms does not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, rather than to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, Comprising: a substrate, a dielectric layer disposed on the substrate, and a redistribution layer disposed on the dielectric layer; the substrate includes a scribe line region, a pad is provided in the substrate corresponding to the scribe line region, the dielectric layer has bumps disposed on the pad and a first opening disposed on the outer periphery of the bumps, and the first opening exposes a part of the pad; the redistribution layer has an extension portion filled in the first opening and disposed on the bumps, and the extension portion is electrically connected to the pad; wherein, the top surface of the bump is flush with the upper surface of the dielectric layer, and the bump and the dielectric layer are formed by a single patterning process.

2. The semiconductor structure according to claim 1, wherein The first opening is an annular opening surrounding the outer periphery of the bump.

3. The semiconductor structure according to claim 2, characterized in that, The cross-sectional shape of the bump along the thickness direction perpendicular to the dielectric layer is one of a circle, a square, and a rectangle.

4. The semiconductor structure according to claim 1, wherein There are at least two first openings, and at least two first openings are arranged at intervals along the circumferential direction of the bump.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The center of the bump and the center of the pad are located on the same straight line perpendicular to the substrate.

6. The semiconductor structure according to any one of claims 1-4, characterized in that, The projected area of the extension portion on the bump on the substrate is larger than the projected area of the extension portion in the first opening on the substrate.

7. The semiconductor structure according to any one of claims 1-4, characterized in that, The projections of the first opening and the bump on the substrate cover the projection of the pad on the substrate.

8. The semiconductor structure according to claim 1, wherein The redistribution layer is an aluminum wiring layer or a copper wiring layer.

9. The semiconductor structure according to claim 1, wherein The dielectric layer includes a passivation layer, a first insulating layer, and a seed layer that are sequentially stacked, and the redistribution layer is disposed on the seed layer.

10. The semiconductor structure according to claim 9, wherein, The substrate further includes an array region spaced from the scribe line region, a second insulating layer is disposed on the redistribution layer corresponding to the array region, a second opening penetrating the second insulating layer is provided on the second insulating layer, the second opening exposes a part of the redistribution layer, and a bonding wire is provided in the second opening, and one end of the bonding wire is electrically connected to the redistribution layer; wherein, the projection of the second opening on the substrate is different from the projection of the first opening on the substrate in position.

11. A method for preparing a semiconductor structure, characterized in that, Comprising: providing a substrate, the substrate includes a scribe line region, and a pad is provided in the substrate corresponding to the scribe line region; forming a dielectric layer on the substrate, the dielectric layer has bumps disposed on the pad and a first opening disposed on the outer periphery of the bumps, and the first opening exposes a part of the pad; forming a redistribution layer on the dielectric layer, the redistribution layer has an extension portion filling the first opening and disposed on the bumps, and the extension portion is electrically connected to the pad; wherein, the top surface of the bump is flush with the upper surface of the dielectric layer, and the bump and the dielectric layer are formed by a single patterning process.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein forming a dielectric layer on the substrate specifically includes: forming a passivation layer on the substrate; forming a first insulating layer on the passivation layer; forming a first opening penetrating the first insulating layer, the passivation layer, and a part of the substrate on the first insulating layer, and the first opening exposes a part of the pad; A seed layer is formed on the first insulating layer and the pad, and the passivation layer, the first insulating layer and the seed layer form the dielectric layer. The dielectric layer located on the pad forms the bump.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein A redistribution layer is formed on the seed layer. The redistribution layer has an extension portion that fills the first opening and is located on the bump. After the extension portion is electrically connected to the pad, the method further includes: Forming a second insulating layer on the redistribution layer; Forming a second opening in the second insulating layer to expose a part of the redistribution layer. A bonding wire is disposed in the second opening. The bonding wire is electrically connected to the redistribution layer, and a projection position of the second opening on the substrate is different from a projection position of the first opening on the substrate.

14. The method for preparing a semiconductor structure according to claim 13, wherein After forming the second insulating layer on the redistribution layer, the method further includes: Removing the second insulating layer corresponding to the dicing street region to expose the redistribution layer corresponding to the dicing street region.

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