Semiconductor electrostatic protection device

Abstract

The present invention relates to a semiconductor electrostatic protection device, comprising: a substrate of a first conductivity type, in which a deep well region of a second conductivity type is formed; a first diode located in the deep well region of the second conductivity type; an anode of the first diode is connected to a first voltage via a plurality of first metal lines; a second diode located in the deep well region of the second conductivity type; a first pad connected to the anode of the first diode via a plurality of first metal lines, and the first pad is connected to the first voltage; a second pad connected to the cathode of the second diode via a plurality of second metal lines, and the second pad is connected to a second voltage; an input / output pad connected to the anode of the second diode and the cathode of the first diode via a plurality of third metal lines. The above semiconductor electrostatic protection device can significantly improve the electrostatic protection ability without increasing the layout area, enlarge the design window of the electrostatic protection device, and improve the reliability of the product.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor electrostatic protection device. Background Art

[0002] The manufacturing process of modern semiconductors is becoming more and more advanced, the channel length is getting shorter, the junction depth is getting shallower, and with the application of silicide and lightly doped drain (LDD) processes, the oxide layer is getting thinner, the window for ESD (electrostatic discharge) design is getting smaller, and the challenges faced by ESD protection design are getting greater. Currently, the existing electrostatic protection devices generally have poor electrostatic protection capabilities and cannot protect the reliability of products. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor electrostatic protection device to solve the above problems in the prior art.

[0004] To achieve the above object, on the one hand, the present application provides a semiconductor electrostatic protection device, including:

[0005] A substrate of a first conductivity type, in which a deep well region of a second conductivity type is formed;

[0006] A first diode, located in the deep well region of the second conductivity type; the anode of the first diode is connected to a first voltage via a plurality of first metal lines;

[0007] A second diode, located in the deep well region of the second conductivity type;

[0008] A first pad, connected to the anode of the first diode via a plurality of first metal lines, and the first pad is connected to a first voltage;

[0009] A second pad, connected to the cathode of the second diode via a plurality of second metal lines, and the second pad is connected to a second voltage;

[0010] An input / output pad, connected to the anode of the second diode and the cathode of the first diode via a plurality of third metal lines.

[0011] In one embodiment, it further includes: a protection ring, the deep well region of the second conductivity type is located within the protection ring, and the protection ring has a first conductivity type.

[0012] In one embodiment, it further includes: a doped well region of the first conductivity type and a doped well region of the second conductivity type, the doped well region of the first conductivity type and the doped well region of the second conductivity type are both located within the deep well region of the second conductivity type, the first diode is located in the doped well region of the first conductivity type, and the second diode is located in the doped well region of the second conductivity type.

[0013] In one embodiment, the doped well region of the first conductivity type and the doped well region of the second conductivity type are adjacent to each other.

[0014] In one embodiment, the first diode includes a first doped region of the first conductivity type and a second doped region of the second conductivity type. The first doped region is the anode of the first diode, and the second doped region is the cathode of the first diode.

[0015] The second diode includes a third doped region of the second conductivity type and a fourth doped region of the first conductivity type. The fourth doped region is the anode of the second diode, and the third doped region is the cathode of the second diode.

[0016] In one embodiment, the first doped region and the second doped region are alternately arranged at intervals along a first direction; the third doped region and the fourth doped region are alternately arranged at intervals along the first direction.

[0017] In one embodiment, the first metal line is located on the first diode and extends along the first direction; the second metal line is located on the second diode and extends along the first direction; the third metal line is located on the first diode and the second diode and extends along the first direction.

[0018] In one embodiment, the first metal line and the second metal line are arranged in one-to-one correspondence, and the first metal line and the second metal line and the third metal line are alternately arranged at intervals along a second direction; the second direction is perpendicular to the first direction.

[0019] In one embodiment, a fourth metal line is further included. The fourth metal line extends along the second direction and is connected to a plurality of the first metal lines to jointly form an interdigital structure with the first metal lines.

[0020] In one embodiment, a fifth doped region of the first conductivity type is further included. The fifth doped region is located in the deep well region of the second conductivity type and surrounds the first diode and the second diode; the first doped region encloses a plurality of first rings, and the second doped region is located within the first rings; the third doped region is connected to the fifth doped region to jointly enclose a plurality of second rings, and the fourth doped region is located within the second rings.

[0021] In one embodiment, one second doped region is provided in each of the first rings, and one fourth doped region is provided in each of the second rings.

[0022] In one embodiment, a plurality of the second doped regions are provided in each of the first rings. The plurality of the second doped regions located in the same first ring all extend in a second direction and are arranged at intervals along the second direction. A plurality of the fourth doped regions are provided in each of the second rings. The plurality of the fourth doped regions located in the same second ring all extend in the second direction and are arranged at intervals along the second direction. The second direction is perpendicular to the first direction.

[0023] In one embodiment, shallow trench isolation structures are disposed between the first doped region and the second doped region, between the first doped region and the third doped region, and between the third doped region and the fourth doped region.

[0024] In one embodiment, the first voltage is a power supply voltage and the second voltage is a ground voltage; or the first voltage is a ground voltage and the second voltage is a power supply voltage.

[0025] In one embodiment, the number of the first diodes is multiple, and the multiple first diodes are connected in series in sequence; the number of the second diodes is multiple, and the multiple second diodes are connected in series in sequence.

[0026] In one embodiment, the shape of at least one of the first pad, the second pad, and the input / output pad is grid-shaped.

[0027] Compared with the existing electrostatic protection devices, the semiconductor electrostatic protection device can significantly improve the electrostatic protection ability, increase the design window of the electrostatic protection device, and improve the reliability of the product without increasing the layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 is an equivalent circuit diagram of the semiconductor electrostatic protection device provided by the present application;

[0030] Figure 2 is a top view of the semiconductor electrostatic protection device provided by an embodiment of the present application;

[0031] Figure 3 is Figure 2 a cross-sectional structure schematic diagram of the semiconductor electrostatic protection device in

[0032] Figure 4 is Figure 2 a top view of a substrate of a first conductivity type in a semiconductor electrostatic protection device in

[0033] Figure 5 and Figure 6 is a top view of a semiconductor electrostatic protection device provided in another embodiment of the present application.

[0034] Explanation of reference numerals:

[0035] 10 - Substrate of the first conductivity type, 11 - Deep well region of the second conductivity type, 12 - First diode, 121 - First doped region; 122 - Second doped region, 13 - Second diode, 131 - Third doped region, 132 - Fourth doped region, 14 - First pad, 15 - Second pad, 16 - Input / output pad, 171 - First metal wire, 172 - Second metal wire, 173 - Third metal wire, 174 - Fourth metal wire, 18 - Protection ring, 19 - Doped well region of the first conductivity type, 20 - Doped well region of the second conductivity type, 21 - Fifth doped region, 22 - Shallow trench isolation structure. Detailed implementation manners

[0036] For ease of understanding the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0038] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0039] It can be understood that "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is an electrical signal or data transfer between the connected circuits, modules, units, etc.

[0040] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0041] Please refer to Figures 1 to 4 , the present invention provides a semiconductor electrostatic protection device, the semiconductor electrostatic protection device comprising: a substrate 10 of a first conductivity type, a deep well region 11 of a second conductivity type being formed in the substrate 10 of the first conductivity type; a first diode 12, the first diode 12 being located in the deep well region 11 of the second conductivity type; an anode of the first diode 12 being connected to a first voltage via a plurality of first metal lines 171; a second diode 13, the second diode 13 being located in the deep well region 11 of the second conductivity type; a first pad 14, the first pad 14 being connected to the anode of the first diode 12 via a plurality of first metal lines 171, and the first pad 14 being connected to a first voltage; a second pad 15, the second pad 15 being connected to the cathode of the second diode 13 via a plurality of second metal lines 172, and the second pad 15 being connected to a second voltage; an input / output pad 16, the input / output pad 16 being connected to the anode of the second diode 13 and the cathode of the first diode 12 via a plurality of third metal lines 173.

[0042] Compared with the existing electrostatic protection devices, the above semiconductor electrostatic protection device can significantly improve the electrostatic protection ability without increasing the layout area, enlarges the design window of the electrostatic protection device, and improves the reliability of the product.

[0043] Specifically, the material of the substrate 10 of the first conductivity type may include but is not limited to silicon, germanium, GaAs (gallium arsenide), InP (indium phosphide), or GaN (gallium nitride), etc., that is, the substrate 10 of the first conductivity type may be a silicon substrate, a germanium substrate, a GaAs substrate, an InP substrate, or a GaN substrate; in this embodiment, the substrate 10 of the first conductivity type may be a silicon substrate.

[0044] As an example, the depth of the deep well region 11 of the second conductivity type is less than the thickness of the substrate 10 of the first conductivity type.

[0045] Specifically, the deep well region 11 of the second conductivity type may be a lightly doped region.

[0046] As an example, the semiconductor electrostatic protection device further includes a protection ring 18. The deep well region 11 of the second conductivity type is located within the protection ring 18, that is, the protection ring 18 surrounds the periphery of the deep well region 11 of the second conductivity type; the protection ring 18 can have a spacing from the deep well region 11 of the second conductivity type.

[0047] Specifically, the protection ring 18 can have the first conductivity type, that is, the doping type of the protection ring 18 can be the same as the doping type of the substrate 10 of the first conductivity type.

[0048] In one example, the semiconductor electrostatic protection device further includes a doped well region 19 of the first conductivity type and a doped well region 20 of the second conductivity type. The doped well region 19 of the first conductivity type and the doped well region 20 of the second conductivity type are both located within the deep well region 11 of the second conductivity type. The first diode 12 is located in the doped well region 19 of the first conductivity type, and the second diode 13 is located in the doped well region 20 of the second conductivity type.

[0049] Specifically, the doped well region 19 of the first conductivity type and the doped well region 20 of the second conductivity type can both be lightly doped regions; the depth of the doped well region 19 of the first conductivity type can be the same as the depth of the doped well region 20 of the second conductivity type; more specifically, the depth of the doped well region 19 of the first conductivity type and the depth of the doped region 20 of the second conductivity type are both less than the depth of the deep well region 11 of the second conductivity type.

[0050] As an example, the doped well region 19 of the first conductivity type and the doped well region 20 of the second conductivity type can be adjacent. Specifically, the doped well region 19 of the first conductivity type and the doped well region 20 of the second conductivity type are arranged in a direction parallel to the surface of the substrate 10 of the first conductivity type.

[0051] As an example, as Figure 3 shown, the first diode 12 can include a first doped region 121 of the first conductivity type and a second doped region 122 of the second conductivity type. The first doped region 121 is the anode of the first diode 12, and the second doped region 122 is the cathode of the first diode 12; the second diode 13 can include a third doped region 131 of the second conductivity type and a fourth doped region 132 of the first conductivity type. The fourth doped region 132 is the anode of the second diode 13, and the third doped region 131 is the cathode of the second diode 13.

[0052] As an example, the first doped region 121 and the second doped region 122 can be alternately arranged at intervals in the first direction; the third doped region 131 and the fourth doped region 132 can be alternately arranged at intervals in the first direction.

[0053] As an example, as Figure 3As shown, the semiconductor electrostatic protection device further includes a fifth doped region 21 of the first conductivity type, which is located in the deep well region 11 of the second conductivity type and surrounds the first diode 12 and the second diode 13. Specifically, the fifth doped region 21 can be an annular doped region.

[0054] As an example, as Figure 4 shown, the first doped region 121 can enclose a plurality of first rings (not labeled), and the second doped region 122 is located within the first ring; the third doped region 131 is connected to the fifth doped region 21 and jointly encloses a plurality of second rings (not labeled), and the fourth doped region 132 is located within the second ring.

[0055] As an example, the depth of the first doped region 121, the depth of the second doped region 122, the depth of the third doped region 131, the depth of the fourth doped region 132, and the depth of the fifth doped region 21 are all less than the depth of the doped well region 19 of the first conductivity type and the depth of the doped well region 20 of the second conductivity type.

[0056] As an example, the first doped region 121, the second doped region 122, the third doped region 131, the fourth doped region 132, and the fifth doped region 21 can all be heavily doped regions.

[0057] In one example, one second doped region 122 is provided in each first ring, and one fourth doped region 132 is provided in each second ring, as Figure 4 shown.

[0058] In one example, a plurality of second doped regions 122 can be provided in each first ring. The plurality of second doped regions 122 located in the same first ring all extend in the second direction and are spaced apart along the second direction; a plurality of fourth doped regions 132 are provided in each second ring. The plurality of fourth doped regions 132 located in the same second ring all extend in the second direction and are spaced apart along the second direction; the second direction is perpendicular to the first direction.

[0059] In one example, the number of the first diodes 12 can be multiple, and the multiple first diodes 12 are connected in series in sequence; the number of the second diodes 13 can be multiple, and the multiple second diodes 13 are connected in series in sequence. The number of the first diodes 12 and the number of the second diodes 13 can be set according to actual needs and are not limited in this embodiment.

[0060] As an example, as Figure 3As shown, shallow trench isolation structures 22 are arranged between the first doping region 121 and the second doping region 122, between the first doping region 121 and the third doping region 131, and between the third doping region 131 and the fourth doping region 132. Specifically, shallow trench isolation structures are also provided between the first doping region 121 and the guard ring 18 and between the third doping region 131 and the guard ring 18.

[0061] Specifically, the longitudinal cross-sectional shape of the shallow trench isolation structure 22 can be rectangular, inverted trapezoidal, semi-elliptical, etc.

[0062] Specifically, the height of the shallow trench isolation structure 22 is greater than the depths of the first doping region 121, the second doping region 122, the third doping region 131, the fourth doping region 132, and the fifth doping region 21, and less than the depths of the doping well region 19 of the first conductivity type and the doping well region 20 of the second conductivity type.

[0063] In one example, the first conductivity type can be P-type, and the second conductivity type can be N-type.

[0064] In another example, the first conductivity type can be N-type, and the second conductivity type can be P-type.

[0065] In one example, the first voltage can be the power supply voltage VDD, and the second voltage is the ground voltage VSS; that is, the anode of the first diode 12 is connected to the power supply terminal, and the cathode is connected to the input / output terminal, and the anode of the second diode 13 is connected to the input / output terminal, and the cathode is connected to the ground terminal. Therefore, when an electrostatic discharge occurs between the input / output terminal and the power supply terminal, and the voltage generated by the electrostatic charge is greater than the reverse breakdown voltage of the first diode 12, the electrostatic charge is discharged through the first diode 12; when an electrostatic discharge occurs between the input / output terminal and the ground terminal, and when the voltage generated by the electrostatic charge is greater than the forward conduction voltage of the second diode 13, the electrostatic charge is discharged through the second diode 13.

[0066] In another alternative embodiment, as Figure 1 and Figure 3 shown, the first voltage is the ground voltage Vss, and the second voltage is the power supply voltage Vdd. That is, the anode of the first diode 12 is connected to the ground terminal, and the cathode is connected to the input / output terminal, and the anode of the second diode 13 is connected to the input / output terminal, and the cathode is connected to the power supply terminal. Therefore, when an electrostatic discharge occurs between the input / output terminal and the power supply terminal, and the voltage generated by the electrostatic charge is greater than the forward conduction voltage of the first diode 12, the electrostatic charge is discharged through the first diode 12; when an electrostatic discharge occurs between the input / output terminal and the ground terminal, and when the voltage generated by the electrostatic charge is greater than the reverse breakdown voltage of the second diode 13, the electrostatic charge is discharged through the second diode 13.

[0067] As an example, asFigure 2 As shown, the first metal wire 171 is located on the first diode 12 and extends along the first direction; the second metal wire 172 is located on the second diode 13 and extends along the first direction; the third metal wire 173 is located on the first diode 12 and the second diode 13 and extends along the first direction.

[0068] It should be noted that Figure 2 in the second metal wire 172 can also extend from the second diode 13 to the first diode 12, but the second metal wire 172 is only connected to the second diode 13 and not to the first diode 12.

[0069] It should be further noted that Figure 2 the output pad 16 connected by the third metal wire 173 in is not shown.

[0070] Specifically, the number of the first metal wires 171, the number of the second metal wires 172, and the number of the third metal wires 173 can be set according to actual needs. Figure 2 In, two first metal wires 171, two second metal wires 172, and three third metal wires 173 are taken as examples.

[0071] As an example, the first metal wires 171 and the second metal wires 172 are arranged in one-to-one correspondence, and the first metal wires 171 and the second metal wires 172 and the third metal wires 173 are alternately arranged at intervals along the second direction; the second direction is perpendicular to the first direction.

[0072] As an example, as Figure 2 shown, the shape of at least one of the first pad 14, the second pad 15, and the input / output pad 16 is grid-shaped; Figure 2 In the embodiment of, the shapes of the first pad 14, the second pad 15, and the input / output pad 16 are all grid-shaped as an example.

[0073] Specifically, the first metal wires 171, the second metal wires 172, and the third metal wires 173 can all include but are not limited to copper wires, aluminum wires, gold wires, or nickel wires, etc. In this embodiment, the first metal wires 171, the second metal wires 172, and the third metal wires 173 can all be copper wires.

[0074] The failure weak points of the semiconductor electrostatic protection device are on the metal wires (i.e., the first metal wires 171, the second metal wires 172, and the third metal wires 173). Figure 2 Although the semiconductor electrostatic protection device in has a certain improvement in electrostatic protection ability compared with the existing semiconductor electrostatic protection device, due to the less layout of the metal wires and the imperfect setting of the metal wires, Figure 2 the semiconductor electrostatic protection device in still has the problem of insufficient electrostatic protection ability.

[0075] In another embodiment, as Figure 5 and Figure 6 shown, Figure 5 and Figure 6 the specific structure of the semiconductor electrostatic protection device in Figures 1 to 4 is substantially the same as the specific structure of the semiconductor electrostatic protection device in Figure 5 and Figure 6 The difference between the two is that: Figures 1 to 4 the metal wires of the semiconductor electrostatic protection device in

[0076] are different from the metal wires of the semiconductor electrostatic protection device in Figure 5 Specifically, as

[0077] shown, the semiconductor electrostatic protection device further includes a fourth metal wire 174. The fourth metal wire 174 extends along the second direction and is connected to a plurality of first metal wires 171 to jointly form an interdigital structure with the first metal wires 171. Figure 5 and Figure 6 are top views of the same semiconductor electrostatic protection device. Since the first pad 14, the second pad 15, and the input / output pad 16 are not convenient to be shown simultaneously in the same drawing, they are respectively shown in Figure 5 and Figure 6 two drawings respectively.

[0078] Specifically, the number of the first metal wires 171, the number of the second metal wires 172, and the number of the third metal wires 173 can be set according to actual needs; specifically, in this embodiment, the number of the first metal wires 171 connected to the first diode 12 is three, the number of the third metal wires 173 is four, as Figure 5 shown; the number of the second metal wires 172 is three, as Figure 6 shown. Of course, in other examples, the number of the first metal wires 171, the number of the second metal wires 172, and the number of the third metal wires 173 can be set to more.

[0079] Figure 5 and Figure 6 By adding the fourth metal wire 174 to the semiconductor electrostatic protection device and adjusting the number of the first metal wires 171, the number of the second metal wires 172, and the number of the third metal wires 173, the semiconductor electrostatic protection device can have better electrostatic protection ability.

[0080] In the description of this specification, the descriptions referring to terms such as "one of the embodiments" and "other embodiments" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0081] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0082] The above-described embodiments merely represent several implementation manners of the present invention. The descriptions thereof are relatively specific and detailed, but should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A semiconductor electrostatic protection device, characterized in that, Comprising: A substrate of a first conductivity type, in which a deep well region of a second conductivity type is formed; A first diode, located within the deep well region of the second conductivity type; the anode of the first diode is connected to a first voltage via a plurality of first metal lines; A second diode, located within the deep well region of the second conductivity type; A first pad, connected to the anode of the first diode via a plurality of first metal lines, and the first pad is connected to a first voltage; A second pad, connected to the cathode of the second diode via a plurality of second metal lines, and the second pad is connected to a second voltage; An input / output pad, connected to the anode of the second diode and the cathode of the first diode via a plurality of third metal lines.

2. The semiconductor electrostatic protection device according to claim 1, wherein Further comprising: A guard ring, the deep well region of the second conductivity type is located within the guard ring, and the guard ring has a first conductivity type.

3. The semiconductor electrostatic protection device according to claim 1, wherein Further comprising: A doped well region of the first conductivity type and a doped well region of the second conductivity type, both the doped well region of the first conductivity type and the doped well region of the second conductivity type are located within the deep well region of the second conductivity type, the first diode is located within the doped well region of the first conductivity type, and the second diode is located within the doped well region of the second conductivity type.

4. The semiconductor electrostatic protection device according to claim 3, characterized in that, The doped well region of the first conductivity type and the doped well region of the second conductivity type are adjacent to each other.

5. The semiconductor electrostatic protection device according to claim 3, wherein The first diode includes a first doped region of the first conductivity type and a second doped region of the second conductivity type, the first doped region is the anode of the first diode, and the second doped region is the cathode of the first diode; The second diode includes a third doped region of the second conductivity type and a fourth doped region of the first conductivity type, the fourth doped region is the anode of the second diode, and the third doped region is the cathode of the second diode.

6. The semiconductor electrostatic protection device according to claim 5, characterized in that, The first doped region and the second doped region are alternately arranged at intervals in a first direction; the third doped region and the fourth doped region are alternately arranged at intervals in the first direction.

7. The semiconductor electrostatic protection device according to claim 6, characterized in that, The first metal lines are located on the first diode and extend in the first direction; the second metal lines are located on the second diode and extend in the first direction; the third metal lines are located on the first diode and the second diode and extend in the first direction.

8. The semiconductor electrostatic protection device according to claim 7, wherein The first metal lines and the second metal lines are arranged in one-to-one correspondence, and the first metal lines and the second metal lines and the third metal lines are alternately arranged at intervals in a second direction; the second direction is perpendicular to the first direction.

9. The semiconductor electrostatic protection device according to claim 8, characterized in that, Further comprising fourth metal lines, the fourth metal lines extend in the second direction and are connected to a plurality of the first metal lines to jointly form an interdigital structure with the first metal lines.

10. The semiconductor electrostatic protection device according to claim 6, wherein Further comprising a fifth doped region of the first conductivity type, the fifth doped region is located within the deep well region of the second conductivity type and surrounds the first diode and the second diode; the first doped region encloses a plurality of first rings, and the second doped region is located within the first rings; The third doped region is connected to the fifth doped region to jointly enclose a plurality of second rings, and the fourth doped region is located within the second rings.

11. The semiconductor electrostatic protection device according to claim 10, characterized in that, A second doped region is provided in each of the first rings, and a fourth doped region is provided in each of the second rings.

12. The semiconductor electrostatic protection device according to claim 10, characterized in that, A plurality of the second doped regions are provided in each of the first rings. The plurality of second doped regions located in the same first ring all extend in a second direction and are spaced apart along the second direction. A plurality of the fourth doped regions are provided in each of the second rings. The plurality of fourth doped regions located in the same second ring all extend in the second direction and are spaced apart along the second direction. The second direction is perpendicular to the first direction.

13. The semiconductor electrostatic protection device according to claim 5, characterized in that, Shallow trench isolation structures are disposed between the first doped region and the second doped region, between the first doped region and the third doped region, and between the third doped region and the fourth doped region.

14. The semiconductor electrostatic protection device according to claim 1, wherein The first voltage is a power supply voltage and the second voltage is a ground voltage; or the first voltage is a ground voltage and the second voltage is a power supply voltage.

15. The semiconductor electrostatic protection device according to claim 1, characterized in that, The number of the first diodes is multiple, and the multiple first diodes are connected in series in sequence; the number of the second diodes is multiple, and the multiple second diodes are connected in series in sequence.

16. The semiconductor electrostatic protection device according to claim 1, wherein, The shape of at least one of the first pad, the second pad, and the input / output pad is a grid shape.

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