A method for evaluating the lifetime of a gate oxide layer of a power device

Abstract

This application provides a method for evaluating the gate oxide lifetime of power devices, comprising: applying N different voltages to the gate of the power device, and conducting high-temperature gate bias tests at M different temperatures for each voltage, wherein N and M are both integers greater than 1; when all power devices fail, obtaining N*M time points at which a predetermined percentage of power devices failed in N*M high-temperature gate bias tests; calculating characteristic parameters of the power device to characterize the gate oxide lifetime based on the N different voltages, M different temperatures, and N*M time points; obtaining the evaluation voltage applied to the gate of the power device to be evaluated and the evaluation temperature of the power device to be evaluated, and calculating the gate oxide lifetime of the power device to be evaluated based on the characteristic parameters, evaluation voltage, and evaluation temperature. This application can evaluate the lifetime of power devices, and requires fewer devices for testing, resulting in low cost.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, and in particular to a method for evaluating the lifetime of the gate oxide layer of a power device. Background Technology

[0002] With the advancement of semiconductor technology, the thickness of gate oxide layers is gradually decreasing, while the electric field inside power semiconductor devices is continuously increasing. This internal electric field also causes the gate oxide layer performance of power devices to degrade over time. Furthermore, bias temperature stress and ionizing radiation can both cause gate oxide layer degradation, making gate oxide layer lifetime a significant issue. When the gate oxide layer of a power semiconductor device degrades, it leads to unstable electrical parameters and may even cause gate oxide layer breakdown, resulting in device failure. Therefore, the lifetime of the gate oxide layer in power semiconductor devices is crucial for the normal operation of the device. Summary of the Invention

[0003] In view of this, this application provides a method for evaluating the lifetime of the gate oxide layer of a power device, which can evaluate the lifetime of the power device and requires a small number of devices for testing, resulting in low cost.

[0004] An embodiment of this application provides a method for evaluating the gate oxide lifetime of a power device, comprising: applying N different voltages to the gate of a power device, and performing a high-temperature gate bias test at M different temperatures for each voltage, wherein N and M are both integers greater than 1; when all power devices fail, obtaining N*M time points in N*M high-temperature gate bias tests at which a preset percentage of the power devices failed; calculating characteristic parameters of the power device to characterize the gate oxide lifetime based on the N different voltages, the M different temperatures, and the N*M time points; obtaining the evaluation voltage applied to the gate of the power device to be evaluated and the evaluation temperature of the power device to be evaluated, and calculating the gate oxide lifetime of the power device to be evaluated based on the characteristic parameters, the evaluation voltage, and the evaluation temperature.

[0005] Compared with related technologies, the embodiments of this application have at least the following advantages: By applying N different voltages to the gate of the power device and conducting high-temperature gate bias tests at M different temperatures for each voltage, characteristic parameters for characterizing the gate oxide lifetime can be calculated based on the experimental data. When it is necessary to estimate the gate oxide lifetime of the power device to be evaluated, only the voltage applied to the gate of the power device to be evaluated and the temperature of the environment in which the power device to be evaluated are known, and the gate oxide lifetime of the power device to be evaluated can be estimated based on the previous experimental data. In addition, the embodiments of this application use fewer devices or chips, which can greatly save testing and analysis costs.

[0006] In one possible implementation, calculating the characteristic parameters of the power device used to characterize the gate oxide lifetime based on the N different voltages, the M different temperatures, and the N*M time points includes: calculating the N gate oxide field strengths of the power device based on the N different voltages; performing a first data processing on the N*M time points to obtain N*M first time feature values; plotting a first relationship graph between the gate oxide field strength and the first time feature values; performing a second data processing on the M different temperatures to obtain M temperature feature values; performing a third data processing on the N*M time points to obtain N*M second time feature values; plotting a second relationship graph between the temperature feature values ​​and the second time feature values; and obtaining the characteristic parameters based on the first and second relationship graphs.

[0007] In one possible implementation, obtaining the feature parameters based on the first and second relationship graphs includes: extracting M first slopes from the first relationship graph and plotting a third relationship graph between the absolute value of the first slope and the temperature feature value; extracting N second slopes from the second relationship graph and plotting a fourth relationship graph between the second slope and the gate oxide field strength; and obtaining the feature parameters based on the third and fourth relationship graphs.

[0008] In one possible implementation, the characteristic parameters include: an acceleration factor and an activation energy; obtaining the characteristic parameters based on the third and fourth relational graphs includes: obtaining the acceleration factor based on the third relational graph and obtaining the activation energy based on the fourth relational graph.

[0009] In one possible implementation, calculating the gate oxide lifetime of the power device under evaluation based on the characteristic parameters, the evaluation voltage, and the evaluation temperature includes: calculating the evaluation gate oxide field strength of the power device under evaluation based on the evaluation voltage; obtaining the activation energy of the power device under evaluation based on the evaluation gate oxide field strength and the fourth relationship diagram; and calculating the gate oxide lifetime of the power device under evaluation according to the following formula:

[0010] Where t2 is the gate oxide lifetime of the power device under evaluation, A is the acceleration factor, K is a constant, T2 is the ambient temperature, and E is the acceleration factor. a2 E represents the activation energy of the power device to be evaluated. a1 T1 is the activation energy of the power device in the fourth relationship diagram, and T1 is the activation energy of the power device in the fourth relationship diagram. a1 The corresponding temperature.

[0011] In one possible implementation, before applying N different voltages to the gate of the power device, the method further includes: testing the static parameters of multiple test power devices in their initial state; applying voltages to the gates of the multiple test power devices to perform a high-temperature gate bias test for a preset time at a preset temperature; testing the static parameters of the multiple test power devices after the high-temperature gate bias test and removing test power devices in a failed state; confirming whether all of the multiple test power devices have failed; if not all of the multiple test power devices have failed, increasing the gate voltage of the unfailed test power devices by a preset gradient and performing a high-temperature gate bias test for a preset time at a preset temperature until all of the multiple test power devices have failed; performing cross-sectional analysis on the failed test power devices and determining the failure type; obtaining N*M time points at which a preset percentage of the power devices failed in N*M high-temperature gate bias tests includes: obtaining N*M time points at which a preset percentage of the power devices failed in N*M high-temperature gate bias tests based on the cross-sectional analysis and the failure type determination results.

[0012] In one possible implementation, obtaining N*M time points in which a predetermined percentage of the power devices failed during N*M high-temperature gate bias tests, based on the results of the cross-sectional analysis and the failure type determination, includes: plotting a graph showing the relationship between the number of power devices in a failed state and the gate voltage, where the failure state includes intrinsic failure and external failure, and the number includes the number of power devices in intrinsic failure and the number of power devices in external failure; and obtaining N*M time points in N*M high-temperature gate bias tests in which a predetermined percentage of the power devices experienced intrinsic failure, based on the graph.

[0013] In one possible implementation, the static parameters include the gate resistance and gate leakage current of the test power device in the off state.

[0014] In one possible implementation, the power device is confirmed to be in a failed state when the leakage current of the gate of the power device is greater than a first threshold.

[0015] In one possible implementation, the static parameters of the power device include the leakage currents of the source and drain of the power device in the off state. Attached Figure Description

[0016] Figure 1 A schematic flowchart of a power device gate oxide lifetime assessment method provided in an embodiment of this application;

[0017] Figure 2 A first relationship graph between gate oxide field strength and first time characteristic value provided in an embodiment of this application;

[0018] Figure 3 A third graph showing the relationship between the absolute value of the first slope and the temperature characteristic value, provided for an embodiment of this application;

[0019] Figure 4 A second relationship diagram of temperature feature values ​​and second time feature values ​​provided in an embodiment of this application;

[0020] Figure 5 A fourth graph showing the relationship between the second slope and the gate oxide field strength, provided for an embodiment of this application;

[0021] Figure 6 A schematic flowchart of a power device gate oxide lifetime assessment method provided in an embodiment of this application;

[0022] Figure 7 A schematic diagram illustrating the intrinsic and external failure behaviors of the gate oxide layer of a silicon carbide power device provided in an embodiment of this application;

[0023] Figure 8 This is a graph showing the relationship between the number of failed power devices and the applied gate voltage as provided in an embodiment of this application.

[0024] Figure 9 This is a coordinate graph based on the statistical fitting of intrinsic failure and external failure, provided as an embodiment of this application. Detailed Implementation

[0025] To better understand the above-mentioned objectives, features, and advantages of this application, the application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0026] The following description sets forth many specific details to provide a full understanding of this application. The described embodiments are only some, not all, of the embodiments of this application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0028] It should be further noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0029] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and drawings of this application are used to distinguish similar objects, not to describe a specific order or sequence.

[0030] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0031] For ease of understanding, exemplary descriptions of some concepts related to the embodiments of this application are provided for reference.

[0032] As a thin insulating layer, the gate oxide layer plays an important role in the performance of power devices. As the thickness of the gate oxide layer decreases to its limit, the influence of external stress on the gate oxide layer becomes increasingly significant.

[0033] Bias temperature stress and ionizing radiation can both cause degradation of the gate oxide layer, which may lead to gate oxide breakdown and power device failure. Therefore, the reliability of the gate oxide layer is crucial for the normal operation of power devices.

[0034] Figures 1 to 5 In this context, Eox represents the electric field strength; T63% represents the failure time point corresponding to the 63rd device failure in all intrinsic failure cases, sorted by time; Feild Accelerationγ represents the field acceleration factor; temperature represents the temperature; and Activation Energy represents the activation energy.

[0035] Please see Figure 1 , Figure 1 This is a flowchart illustrating a power device gate oxide lifetime assessment method provided in one embodiment of this application.

[0036] Step S101: Based on the high-temperature gate bias reliability device for power devices, apply N different voltages to the gate of the power device, such as 15 volts, 20 volts, 25 volts, 27 volts, and 29 volts (details omitted here); and conduct high-temperature gate bias tests at M different temperatures for each voltage, such as 200-400 degrees Celsius, 150-300 degrees Celsius, and 25-175 degrees Celsius (details omitted here).

[0037] In some embodiments, N and M are both integers greater than 1.

[0038] Step S102: When all power devices fail, obtain N*M time points in N*M high-temperature gate bias tests where a preset percentage of power devices fail.

[0039] To facilitate understanding, the following provides specific examples of how to conduct high-temperature gate bias tests and how to obtain time points in this embodiment:

[0040] A certain number of power devices were selected, and four temperature points (M=4) were chosen: 150°C, 200°C, 250°C, and 300°C. Four gate oxide field strengths (M=4, M=8.2 mV / cm, M=8.6 mV / cm, M=9 mV / cm, and M=9.5 mV / cm) were also selected. The gate oxide field strength was calculated by dividing the effective voltage applied to the gate oxide layer by the thickness of the gate oxide layer. In other words, four different voltages (N=4) were applied to the gate of the power devices, placing them within the four gate oxide field strengths. High-temperature gate bias tests were conducted under these conditions until all devices failed (a total of 16 tests). The time point at which 63% of the devices failed was defined as T63%. Fifty power devices were tested under each condition.

[0041] Step S103: Calculate the characteristic parameters of the power device used to characterize the gate oxide lifetime based on N different voltages, M different temperatures, and N*M time points.

[0042] In some embodiments, the characteristic parameters can be calculated as follows: N gate oxide field strengths of the power device are calculated based on the N different voltage values; the N*M time points are subjected to a first data processing to obtain N*M first time characteristic values; a first relationship graph is plotted between the gate oxide field strengths and the first time characteristic values; the M different temperatures are subjected to a second data processing to obtain M temperature characteristic values; the N*M time points are subjected to a third data processing to obtain N*M second time characteristic values; a second relationship graph is plotted between the temperature characteristic values ​​and the second time characteristic values; and the characteristic parameters are obtained based on the first and second relationship graphs.

[0043] Specifically, obtaining the feature parameters based on the first and second relationship graphs includes: extracting M first slopes from the first relationship graph and plotting a third relationship graph between the absolute value of the first slope and the temperature feature value; extracting N second slopes from the second relationship graph and plotting a fourth relationship graph between the second slope and the gate oxide field strength; and obtaining the feature parameters based on the third and fourth relationship graphs.

[0044] In some embodiments, the characteristic parameters include: acceleration factor and activation energy; obtaining the characteristic parameters according to the third relationship diagram and the fourth relationship diagram includes: obtaining the acceleration factor according to the third relationship diagram and obtaining the activation energy according to the fourth relationship diagram.

[0045] To facilitate understanding, the following will be combined with... Figures 2 to 5 This embodiment provides a detailed explanation of how the acceleration factor and activation energy are calculated:

[0046] Please see Figure 2 This is the first graph showing the relationship between the gate oxide field strength and the first time eigenvalue. Figure 2 The x-axis represents the gate oxide field strength. Figure 2 The vertical axis is the logarithm of time point T63% to the base 10. That is, the N*M time points are processed by the first data processing to obtain N*M first time feature values. Specifically, the N*M time points are each taken as the logarithm to the base 10 to obtain N*M first time feature values.

[0047] At four temperature points—150°C, 200°C, 250°C, and 300°C—each temperature point corresponds to four sets of gate oxide field strengths and first-time characteristic values. Based on the above data, plotting... Figure 2 ,get Figure 2 The four straight lines shown.

[0048] Please see Figure 3 This is the third graph showing the relationship between the absolute value of the first slope and the temperature characteristic value. Figure 3The horizontal axis represents the temperature characteristic value, and the vertical axis represents the absolute value of the first slope; extraction Figure 2 The slopes of the four straight lines are used to obtain four first slopes. 150°C, 200°C, 250°C, and 300°C are converted to Kelvin, and 1000 is divided by these four Kelvin values ​​to obtain four temperature characteristic values. Therefore, based on these temperature characteristic values ​​and the absolute values ​​of the first slopes, a plot can be drawn. Figure 3 .according to Figure 3 The acceleration factor can be obtained by using the coordinate formula of the straight line.

[0049] Please see Figure 4 This is the second relationship graph between the temperature characteristic value and the second time characteristic value. Figure 4 The horizontal axis represents the temperature characteristic value, and the vertical axis represents the logarithm of time point T63% to the base e. In other words, the N*M time points are subjected to third data processing to obtain N*M second time characteristic values. Specifically, the logarithm of each of the N*M time points is taken to the base e to obtain N*M second time characteristic values.

[0050] At four gate oxide field strengths of 8.2 mV / cm, 8.6 mV / cm, 9 mV / cm, and 9.5 mV / cm, each gate oxide field strength corresponds to four sets of temperature points and second time characteristic values. Based on the above data, plotting... Figure 4 You can get Figure 4 The four straight lines shown.

[0051] Please see Figure 5 This is the fourth graph showing the relationship between the second slope and the gate oxide field strength. Figure 5 The x-axis represents the gate oxide field strength, and the y-axis represents the second slope; extract Figure 4 The slopes of the four straight lines are used to obtain four second slopes. Therefore, based on the above gate oxide field strength and second slopes, the following can be plotted: Figure 5 .according to Figure 5 The activation energy can be obtained by using the coordinate formula of the straight line.

[0052] Step S104: Obtain the evaluation voltage applied to the gate of the power device to be evaluated and the evaluation temperature of the power device to be evaluated, and calculate the gate oxide lifetime of the power device to be evaluated based on the characteristic parameters, evaluation voltage and evaluation temperature.

[0053] In some embodiments, calculating the gate oxide lifetime of the power device under evaluation based on the characteristic parameters, the evaluation voltage, and the evaluation temperature includes: calculating the evaluation gate oxide field strength of the power device under evaluation based on the evaluation voltage; obtaining the activation energy of the power device under evaluation based on the evaluation gate oxide field strength and the fourth relationship diagram; and calculating the gate oxide lifetime of the power device under evaluation according to the following formula:

[0054] Where t2 is the gate oxide lifetime of the power device to be evaluated, A is the acceleration factor, K is a constant, T2 is the ambient temperature, and E is the voltage. a2 E represents the activation energy of the power device to be evaluated. a1 T1 represents the activation energy of the power device in the fourth relationship diagram, and E represents the activation energy of the device. a1 The corresponding temperature.

[0055] Compared with related technologies, the embodiments of this application have at least the following advantages: By applying N different voltages to the gate of the power device and conducting high-temperature gate bias tests at M different temperatures for each voltage, characteristic parameters for characterizing the gate oxide lifetime can be calculated based on the experimental data. When it is necessary to estimate the gate oxide lifetime of the power device to be evaluated, only the voltage applied to the gate of the power device to be evaluated and the temperature of the environment in which the power device to be evaluated are known, and the gate oxide lifetime of the power device to be evaluated can be estimated based on the previous experimental data. In addition, the embodiments of this application use fewer devices or chips, which can greatly save testing and analysis costs.

[0056] The second embodiment of this application relates to a method for evaluating the gate oxide lifetime of a power device. This embodiment is a further improvement on the foregoing embodiment. Specifically, the improvement lies in that, before applying voltage to the gate of the power device, the method further includes: determining the failure type of the power device, and selecting a preset percentage of the time points at which intrinsic failure of the power device occurs when acquiring the time points. This approach improves the accuracy of subsequent tests, thereby enhancing the accuracy of the power device gate oxide lifetime evaluation.

[0057] Please see Figure 6 , Figure 6 This is a flowchart illustrating a power device gate oxide lifetime assessment method provided in one embodiment of this application.

[0058] Step S201: Test the static parameters of multiple test power devices in their initial state.

[0059] In some embodiments, the static parameters of the power device may include the electrical parameters of the power device in the off state, such as the gate resistance, gate leakage current, and source-drain leakage current of the power device.

[0060] In some embodiments, the number of test power devices is not specifically limited and can be set according to actual needs.

[0061] Step S202: Apply voltage to the gate of multiple test power devices to perform a high-temperature gate bias test for a preset time at a preset temperature, test the static parameters of the multiple test power devices after the high-temperature gate bias test, and remove the test power devices that are in a failed state.

[0062] In some embodiments, after testing the static parameters of multiple power devices in their initial state, a voltage V is applied to the gates of these power devices. g0 A high-temperature gate bias (HTGB) test is performed at a preset temperature, and the test duration can be preset. The preset time can be set according to actual testing requirements, and this application does not limit it.

[0063] The power device can be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0064] In a specific scenario, the number of power devices can be greater than 100. For example, 240 power devices can be selected, and their static parameters in the initial state can be tested. Then, the gate voltage V of the 240 power devices can be measured. g0 Set to 15 volts and conduct HTGB tests at 150 degrees Celsius for up to 168 hours.

[0065] After the first stage of high-temperature gate bias test, the static parameters of these test power devices can be tested, and the failed test power devices can be eliminated based on the static parameters obtained after the test.

[0066] Specifically, embodiments of this application can determine whether a test power device has failed based on its static parameters. For example, when the gate leakage current of the test power device is greater than a first threshold, the test power device can be confirmed as failing; or when the source-drain leakage current of the test power device is greater than a second threshold, the test power device can be confirmed as failing.

[0067] Step S203: Confirm whether all of the multiple test power devices have failed; if not all of the multiple test power devices have failed, increase the gate voltage of the unfailed test power devices by a preset gradient and perform a high-temperature gate bias test for a preset time at a preset temperature until all of the multiple test power devices have failed.

[0068] In some embodiments, the gate voltage V of the remaining unfailed power devices is... g1 The voltage is set to 18 volts, and an HTGB test is conducted at 150 degrees Celsius for 168 hours. Thus, the difference between the second voltage (e.g., 18 volts) and the first voltage (e.g., 15 volts) is 3 volts. It can be understood that in this embodiment, the voltage V... g1 Greater than voltage V g0 Voltage Vg1 With voltage V g0 The difference between them is a preset threshold.

[0069] Therefore, after the second stage of high-temperature gate bias test, the static parameters of these power devices can be tested, and the failed power devices can be removed based on the static parameters obtained after the test.

[0070] If not all of the selected power devices fail, that is, if some of the selected power devices still have not failed, then the gate voltage step stress test will continue to be performed on these power devices that have not failed.

[0071] For example, if not all tested power devices fail, repeat step S203, increasing the gate voltage of each high-temperature gate bias test by a preset threshold (e.g., 3 volts) until all devices fail. For example, the gate voltage V of the remaining unfailed power devices can be... g2 The voltage was set to 21 volts, and an HTGB test was conducted at 150 degrees Celsius for 168 hours. Next, the gate voltage V of the remaining undone power devices was... g3 Set to 24 volts and conduct a high-temperature gate bias test for a preset time at a preset temperature. Test the static parameters of the power devices after the high-temperature gate bias test, and continue to eliminate failed power devices.

[0072] It is understandable that the aforementioned gate voltage V g0 and gate voltage V g1 There is a 3-volt voltage difference between them, and the gate voltage V g1 and gate voltage V g2 There is a 3-volt voltage difference between them, and the gate voltage V g2 and gate voltage V g3 There is a voltage difference of 3 volts between them.

[0073] Therefore, the gate voltage step stress experiment was completed until all power devices failed.

[0074] Step S204: Perform cross-sectional analysis on the failed test power device and determine the failure type.

[0075] In some embodiments, the failure state includes intrinsic failure and external failure, and the quantity includes the number of power devices in the intrinsic failure state and the number of power devices in the external failure state.

[0076] Please see Figure 7Power devices that fail due to gate oxide thinning can be defined as exhibiting external failure behavior, which can be associated with the packaging. Problems during the packaging process can lead to gate oxide thinning, causing the power device to fail. Conversely, power devices that fail without gate oxide thinning can be defined as exhibiting intrinsic failure behavior.

[0077] In this embodiment of the application, after performing cross-sectional analysis on the failed power device, a graph showing the relationship between the number of failed devices and the applied gate voltage and the voltage value can be obtained.

[0078] Please see Figure 8 The vertical axis represents the number of devices that fail each time, and the horizontal axis represents the voltage value after subtracting the initial gate voltage from the gate voltage applied each time. It can also distinguish between intrinsic failure behavior and external failure.

[0079] Please see Figure 9 Based on the intrinsic failure experimental data, a graph showing the relationship between In(-In(1-F)) and failure time was plotted.

[0080] Specifically, the number of power devices that failed in each step of the high-temperature gate bias test is counted, and the failure types are classified to draw statistical charts of internal and external failures of the power devices.

[0081]

[0082] For example, the number of power devices exhibiting external failure behavior and the number of power devices exhibiting intrinsic failure behavior can be counted, and the F-value can be calculated. This F-value can satisfy the following formula:

[0083] Where i is the number of failed power devices and N is the total number of devices being tested.

[0084] Therefore, embodiments of this application can calculate the value of -In(1-F) and plot -In(1-F) against Vg0-Vg. N The relationship between points is plotted, and a straight line is fitted.

[0085] Step S205: Based on the results of the cross-sectional analysis and the failure type determination, draw a graph showing the relationship between the number of power devices in the failure state and the gate voltage and the voltage value.

[0086] Step S206: Apply N different voltages to the gate of the power device, and conduct a high-temperature gate bias test at M different temperatures for each voltage.

[0087] Step S207: When all power devices fail, according to the relationship diagram, obtain N*M time points at which the preset percentage of power devices experienced intrinsic failure in N*M high-temperature gate bias tests.

[0088] Step S208: Calculate the characteristic parameters of the power device used to characterize the gate oxide lifetime based on N different voltages, M different temperatures, and N*M time points.

[0089] Step S209: Obtain the evaluation voltage applied to the gate of the power device to be evaluated and the evaluation temperature of the power device to be evaluated, and calculate the gate oxide lifetime of the power device to be evaluated based on the characteristic parameters, evaluation voltage and evaluation temperature.

[0090] Compared with related technologies, the embodiments of this application have at least the following advantages: By applying N different voltages to the gate of the power device and conducting high-temperature gate bias tests at M different temperatures for each voltage, characteristic parameters for characterizing the gate oxide lifetime can be calculated based on the experimental data. When it is necessary to estimate the gate oxide lifetime of the power device to be evaluated, only the voltage applied to the gate of the power device to be evaluated and the temperature of the environment in which the power device to be evaluated are known, and the gate oxide lifetime of the power device to be evaluated can be estimated based on the previous experimental data. In addition, the embodiments of this application use fewer devices or chips, which can greatly save testing and analysis costs.

[0091] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application.

Claims

1. A method for evaluating the lifetime of the gate oxide layer of a power device, characterized in that, include: N different voltages are applied to the gate of the power device, and a high-temperature gate bias test is performed at M different temperatures for each voltage, where N and M are both integers greater than 1. When all the power devices fail, obtain N. In the Mth high-temperature gate bias test, a predetermined percentage of the power devices failed (N). M time points; Based on the N different voltages, the M different temperatures, and the N... At M time points, the characteristic parameters used to characterize the gate oxide lifetime of the power device are calculated, including: acceleration factor and activation energy; The evaluation voltage applied to the gate of the power device to be evaluated and the evaluation temperature of the power device to be evaluated are obtained, and the gate oxide lifetime of the power device to be evaluated is calculated based on the characteristic parameters, the evaluation voltage and the evaluation temperature. The N different voltages, the M different temperatures, and the N At M time points, calculate the characteristic parameters of the power device used to characterize the gate oxide lifetime, including: Calculate the N gate oxide field strengths of the power device based on the N different voltage values; The N The first data is processed at M time points to obtain N. M first-time feature values; Plot a first relationship graph between the gate oxide field strength and the first time eigenvalue; The M different temperatures are subjected to a second data processing to obtain M temperature feature values; The N The third data processing is performed at M time points to obtain N. M second-time feature values; Plot a second relationship graph between the temperature characteristic value and the second time characteristic value; The feature parameters are obtained based on the first relationship diagram and the second relationship diagram; The step of obtaining the feature parameters based on the first relationship diagram and the second relationship diagram includes: Based on the first relationship graph, extract M first slopes and draw a third relationship graph between the absolute value of the first slope and the temperature feature value; Based on the second relationship graph, extract N second slopes and draw a fourth relationship graph between the second slope and the gate oxide field strength; The feature parameters are obtained based on the third and fourth relationship diagrams; The step of obtaining the feature parameters based on the third relationship diagram and the fourth relationship diagram includes: The acceleration factor is obtained from the third relationship diagram, and the activation energy is obtained from the fourth relationship diagram.

2. The power device gate oxide lifetime assessment method as described in claim 1, characterized in that, The step of calculating the gate oxide lifetime of the power device under evaluation based on the characteristic parameters, the evaluation voltage, and the evaluation temperature includes: The evaluation gate oxide field strength of the power device to be evaluated is calculated based on the evaluation voltage. The activation energy of the power device to be evaluated is obtained based on the assessed gate oxide field strength and the fourth relationship diagram. The gate oxide lifetime of the power device to be evaluated is calculated using the following formula: in, Let A be the gate oxide lifetime of the power device to be evaluated, A be the acceleration factor, and K be a constant. For the evaluation temperature, The activation energy of the power device to be evaluated is denoted as .

3. The power device gate oxide lifetime assessment method as described in claim 1, characterized in that, Before applying N different voltages to the gate of the power device, the method further includes: Test the static parameters of multiple test power devices in their initial state; A voltage is applied to the gate of the plurality of test power devices to perform a high-temperature gate bias test for a preset time at a preset temperature; The static parameters of the multiple test power devices after the high-temperature gate bias test are tested, and the test power devices that are in a failed state are removed. Confirm whether all of the multiple test power devices have failed; If not all of the multiple test power devices fail, the gate voltage of the unfailed test power devices will be increased in a preset gradient, and a high-temperature gate bias test will be performed at a preset temperature for a preset time until all of the multiple test power devices fail. The failed test power devices were subjected to cross-sectional analysis and the failure type was determined. The acquisition of N In the Mth high-temperature gate bias test, a predetermined percentage of the power devices failed (N). There are M time points, including: Based on the results of the cross-sectional analysis and the failure type determination, N is obtained. In the Mth high-temperature gate bias test, a predetermined percentage of the power devices failed (N). M time points.

4. The power device gate oxide lifetime assessment method as described in claim 3, characterized in that, Based on the results of the cross-sectional analysis and the failure type determination, N is obtained. In the Mth high-temperature gate bias test, a predetermined percentage of the power devices failed (N). There are M time points, including: Based on the results of the cross-sectional analysis and the failure type determination, a graph showing the relationship between the number of power devices in a failure state and the gate voltage is plotted. The failure state includes intrinsic failure and external failure, and the number includes the number of power devices in the intrinsic failure state and the number of power devices in the external failure state. Based on the relationship diagram, obtain N. In the M high-temperature gate bias tests, a predetermined percentage of the power devices experienced intrinsic failure. M time points.

5. The power device gate oxide lifetime assessment method as described in claim 3, characterized in that, The static parameters include the gate resistance and gate leakage current of the test power device in the off state.

6. The power device gate oxide lifetime assessment method as described in claim 5, characterized in that, When the leakage current of the gate of the power device exceeds a first threshold, the power device is confirmed to be in a failed state.

7. The power device gate oxide lifetime assessment method according to any one of claims 3 to 6, characterized in that, The static parameters of the power device include the leakage current of the source and drain of the power device in the off state.

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