Chip and its fabrication method

Abstract

A chip and its fabrication method are disclosed. The chip includes a substrate, a control circuit, an in-memory computing layer, and a near-memory computing layer. The control circuit is disposed on the substrate, and the in-memory computing layer and the near-memory computing layer are disposed on the side of the control circuit away from the substrate. The in-memory computing layer is disposed on the side of the near-memory computing layer that is close to or away from the substrate. The in-memory computing layer includes multiple memory modules, and the near-memory computing layer includes multiple vertically complementary field-effect transistors (VFETs). The multiple memory modules and the multiple VFETs are electrically connected to the control circuit. The control circuit, the in-memory computing layer, and the near-memory computing layer of this chip can be disposed on the same substrate. The in-memory computing layer and the near-memory computing layer can each perform different computational functions, enabling the chip to process complex neural networks, such as deep learning super-resolution algorithms.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a chip and a method for fabricating the same. Background Technology

[0002] Enhanced deep super-resolution network (EDSR) is an algorithm network that uses deep learning neural networks to recover high-resolution images from a series of noisy, blurred, and undersampled low-resolution image sequences.

[0003] Spatial resolution is an important indicator of image quality; higher resolution images contain more detail and have greater sharpness. Peak signal-to-noise ratio (PSNR) is the ratio of the maximum power of a signal to the power of its noise, used to measure the quality of a compressed, reconstructed image. A higher PSNR value indicates better image quality. The resolution of the original image is limited by the imaging conditions and methods of the hardware; deep learning super-resolution algorithms can restore and improve the resolution of the original image without increasing hardware costs.

[0004] Traditional methods for increasing pixel density (i.e., adding more pixels to a unit area of ​​a computer image), such as bicubic interpolation, use the gray values ​​of 16 surrounding pixels to perform cubic interpolation. The weights of these 16 pixels are then calculated using an interpolation basis function, and the value of the sampled point is equal to the weighted sum of these 16 pixels. This method of increasing pixel density can cause areas with large pixel variations (excessive derivatives) to appear continuous and less prominent, resulting in a perceptual blur. Super-resolution algorithms, building upon pixel density increases, use deep learning neural networks to train the definition of pixel value functions. This gives the value selection method a self-learning mechanism, allowing the pixel values ​​to approximate the optimized target image as closely as possible.

[0005] The structure of EDSR is as follows Figure 1 As shown, the first row represents the network structure, divided into low-level feature extraction, high-level feature extraction, upsampling layers, and reconstruction layers. The second row represents the construction of residual blocks, as well as the upsampling layers, feature extraction layers, and reconstruction convolutional layers. The input pixel information is processed through a convolutional layer and then output in two paths. One output goes through 17 residual block layers and one convolution, and is weighted and summed with the other output at the intersection. This summation is then combined with the upsampling and convolutional outputs, merging feature information at different levels.

[0006] Chips capable of achieving the aforementioned EDSR require the execution of multiple complex calculation programs, resulting in a relatively complex structure, complicated fabrication process, and large chip size. Summary of the Invention

[0007] At least one embodiment of this disclosure provides a chip, the chip including a substrate, a control circuit, an in-memory computing layer, and a near-memory computing layer; the control circuit is disposed on the substrate, the in-memory computing layer and the near-memory computing layer are disposed on the side of the control circuit away from the substrate, wherein the in-memory computing layer is disposed on the side of the near-memory computing layer close to or away from the substrate; wherein the in-memory computing layer includes a plurality of memories, the near-memory computing layer includes a plurality of vertical complementary field-effect transistors, and the plurality of memories and the plurality of vertical complementary field-effect transistors are electrically connected to the control circuit.

[0008] For example, in a chip provided in at least one embodiment of this disclosure, each of the plurality of vertical complementary field-effect transistors includes a first semiconductor layer and a first source / drain electrode layer, a first insulating layer, a first gate, a second insulating layer, a second semiconductor layer, and a second source / drain electrode layer; wherein, the first source / drain electrode layer is disposed on the side of the first semiconductor layer away from or near the substrate, and includes a first source and a first drain electrode spaced apart; the first insulating layer is disposed on the side of the first semiconductor layer and the first source / drain electrode layer away from the substrate, and includes a first via exposing the first drain electrode; the first gate is disposed on the side of the first insulating layer away from the substrate; and the second insulating layer is disposed on the side of the first gate away from the substrate, and includes a first via exposing the first drain electrode. The second via, the second semiconductor layer, and the second source / drain electrode layer are disposed on the side of the second insulating layer away from the substrate. The second source / drain electrode layer is disposed on the side of the second semiconductor layer away from or close to the substrate, and includes a second source and a second drain disposed at intervals. The second drain is electrically connected to the first drain through the first via and the second via. The first semiconductor layer, the first source / drain electrode layer, the first insulating layer, and the first gate constitute a first transistor, and the first gate, the second insulating layer, the second semiconductor layer, and the second source / drain electrode layer constitute a second transistor. One of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor.

[0009] For example, in the chip provided in at least one embodiment of this disclosure, the first transistor is a P-type transistor, the material of the first semiconductor layer includes P-type nanomaterials or P-type oxides, the second transistor is an N-type transistor, and the material of the second semiconductor layer includes N-type nanomaterials or N-type oxides; or the first transistor is an N-type transistor, the material of the first semiconductor layer includes N-type nanomaterials or N-type oxides, the second transistor is a P-type transistor, and the material of the second semiconductor layer includes P-type nanomaterials or P-type oxides.

[0010] For example, in a chip provided in at least one embodiment of this disclosure, each of the plurality of memories includes a first electrode, a second electrode, and a resistive switching layer between the first electrode and the second electrode.

[0011] For example, in a chip provided in at least one embodiment of this disclosure, each of the plurality of memories further includes: a thermal enhancement layer disposed between the first electrode and the resistive switching layer and / or between the second electrode and the resistive switching layer.

[0012] For example, in a chip provided in at least one embodiment of this disclosure, the first source and / or the first drain and / or the first gate are electrically connected to the first electrode, and the second electrode is electrically connected to the control circuit.

[0013] For example, in a chip provided in at least one embodiment of this disclosure, the control circuit includes a plurality of third transistors, each of the plurality of third transistors including a second gate, a third source and a third drain, wherein the second electrode is electrically connected to the third drain.

[0014] For example, at least one embodiment of the present disclosure provides a chip that further includes: a first passivation layer disposed between the in-memory computing layer and the near-memory computing layer, wherein the first passivation layer has a first interlayer via, and the first source and / or the first drain and / or the first gate are electrically connected to the first electrode through the first interlayer via.

[0015] For example, in a chip provided in at least one embodiment of this disclosure, the first interlayer via has a conductive filler.

[0016] For example, at least one embodiment of the present disclosure provides a chip that further includes a conductive interconnect layer disposed on the side of the first passivation layer away from the substrate, and includes a conductive pattern electrically connected to the conductive filler.

[0017] For example, in a chip provided in at least one embodiment of this disclosure, the conductive filler includes tungsten, and the conductive pattern includes aluminum.

[0018] For example, at least one embodiment of the present disclosure provides a chip that further includes: a second passivation layer disposed on the side of the conductive interconnect layer away from the substrate, wherein the second passivation layer has a second interlayer via exposing the conductive pattern, and the first source and / or the first drain and / or the first gate are electrically connected to the first electrode in sequence through the second interlayer via, the conductive pattern and the conductive filler.

[0019] For example, in a chip provided in at least one embodiment of this disclosure, the control circuit includes a plurality of third transistors, each of the plurality of third transistors including a second gate, a third source and a third drain, wherein the first source and / or the first drain and / or the first gate are electrically connected to the second gate and / or the third source and / or the third drain.

[0020] At least one embodiment of this disclosure provides a method for fabricating a chip, comprising: providing a substrate and a control circuit, wherein the control circuit is disposed on the substrate, and an in-memory computing layer and a near-memory computing layer are formed on the side of the control circuit away from the substrate, wherein the in-memory computing layer is formed on the side of the near-memory computing layer that is close to or away from the substrate; wherein the in-memory computing layer includes a plurality of memories, the near-memory computing layer includes a plurality of vertical complementary field-effect transistors, and the plurality of memories and the plurality of vertical complementary field-effect transistors are electrically connected to the control circuit.

[0021] For example, in the fabrication method provided in at least one embodiment of this disclosure, an in-memory computing layer and a near-memory computing layer are formed on the side of the control circuit away from the substrate, including: forming a plurality of memories in the in-memory computing layer and a plurality of vertical complementary field-effect transistors in the near-memory computing layer under process conditions of less than or equal to 300 degrees Celsius.

[0022] For example, in at least one embodiment of the present disclosure, the method for forming an in-memory computing layer on the side of the control circuit away from the substrate includes: forming a second electrode material layer on the side of the control circuit away from the substrate, forming a resistive switching material layer on the side of the second electrode material layer away from the substrate, forming a first electrode material layer on the side of the resistive switching material layer away from the substrate, and patterning the first electrode material layer, the resistive switching material layer, and the second electrode material layer to form the plurality of memories.

[0023] For example, at least one embodiment of the present disclosure provides a preparation method that further includes: forming a first passivation material layer on the side of the in-memory computing layer away from the substrate; patterning the first passivation material layer to form a first passivation layer having a first interlayer via; forming a conductive material layer on the side of the first passivation layer away from the substrate; and removing the portion of the conductive material layer outside the first interlayer via to form a conductive filler in the first interlayer via.

[0024] For example, at least one embodiment of the present disclosure provides a preparation method that further includes: forming a conductive interconnect material layer on the side of the first passivation layer away from the substrate, and patterning the conductive interconnect material layer to form a conductive pattern electrically connected to the conductive filler.

[0025] For example, at least one embodiment of the present disclosure provides a preparation method that further includes: forming a second passivation material layer on the side of the conductive interconnect layer away from the substrate, and patterning the second passivation material layer to form a second passivation layer having a second interlayer via, wherein the second interlayer via exposes the conductive pattern.

[0026] For example, the fabrication method provided in at least one embodiment of this disclosure further includes: forming another conductive filler in the second interlayer via, and forming a first semiconductor layer of the plurality of vertical complementary field-effect transistors on the side of the second passivation layer away from the substrate. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1 This is a network structure diagram for a deep learning super-resolution algorithm.

[0029] Figure 2 This is a schematic diagram of the stacked structure of a chip provided in at least one embodiment of the present disclosure.

[0030] Figure 3 This is a three-dimensional structural diagram of a chip provided in at least one embodiment of the present disclosure.

[0031] Figure 4 A cross-sectional schematic diagram of a portion of the structure of a chip provided in at least one embodiment of this disclosure;

[0032] Figure 5 Transmission electron microscope image of a chip provided in at least one embodiment of this disclosure;

[0033] Figure 6 This is a structural diagram of a chip executing a deep learning super-resolution algorithm provided in at least one embodiment of the present disclosure;

[0034] Figure 7 A comparison of the chip performance of the deep learning super-resolution algorithm provided in at least one embodiment of this disclosure with other methods;

[0035] Figure 8 A comparison chart of the power consumption of a chip executing a deep learning super-resolution algorithm and a GPU, provided for at least one embodiment of this disclosure; and

[0036] Figure 9 A comparison chart showing the running time of a chip executing a deep learning super-resolution algorithm according to at least one embodiment of this disclosure with that of a traditional two-dimensional chip structure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0039] Monolithic 3D integration technology is an advanced semiconductor manufacturing technology. Its advantage lies in the ability to vertically stack novel logic, memory, and in-memory computing devices with multiple layers that can be integrated through back-end processes on a single chip, significantly reducing chip area while increasing data transmission bandwidth between layers. Unlike millimeter-diameter through-silicon vias (TSVs), monolithic 3D integration does not require drilling interconnects between multiple silicon wafers. Instead, it utilizes inter-layer vias (ILVs) at the hundred-nanometer scale to achieve ultra-high bandwidth interconnects between multiple functional layers of devices on a single silicon wafer, greatly improving data exchange efficiency. Currently, monolithic 3D integration technology explores homogeneous materials, i.e., stacking multiple silicon transistors vertically. Traditional silicon-based semiconductor processes require high-temperature processes such as active layer growth, ion implantation, and annealing. Metal interconnects and other temperature-sensitive processes are placed after the high-temperature processes. Therefore, after fabricating one layer of transistors using traditional silicon-based processes, it is impossible to continue using the same high-temperature processes to fabricate a second layer of devices on the same chip. The use of epitaxy, bonding, and other processes is also limited by factors such as temperature and yield.

[0040] On the other hand, current two-dimensional planar chips rely heavily on silicon-based peripheral circuits on silicon substrates, making it difficult to achieve multi-layer high-density integration. Data transmission efficiency between in-memory computing arrays and CMOS circuits, as well as between in-memory computing arrays, is limited by bandwidth. As the complexity of computing networks increases, the speed and energy consumption advantages brought by in-memory computing will also be dragged down by data transmission through the bus.

[0041] In neural network operations, the main bottleneck is the transfer of weight matrices between the storage module and the computation module. Using in-memory computation eliminates this data transfer, making the efficiency of data transfer in input, output and other computations the decisive factor in computational efficiency.

[0042] At least one embodiment of this disclosure provides a chip and a method for fabricating the same. The chip includes a substrate, a control circuit, an in-memory computing layer, and a near-memory computing layer. The control circuit is disposed on the substrate, and the in-memory computing layer and the near-memory computing layer are disposed on the side of the control circuit away from the substrate. The in-memory computing layer is disposed on the side of the near-memory computing layer that is close to or away from the substrate. The in-memory computing layer includes multiple memory modules, and the near-memory computing layer includes multiple vertical complementary field-effect transistors (VFETs). The multiple memory modules and the multiple VFETs are electrically connected to the control circuit.

[0043] The control circuit, in-memory computing layer, and near-memory computing layer of the chip provided in at least one embodiment of this disclosure can be disposed on the same substrate. The in-memory computing layer and the near-memory computing layer can perform different computing functions respectively, realizing a hybrid in-memory computing architecture. Data communication between the near-memory computing layer and the in-memory computing layer can be carried out through efficient inter-layer interconnection, thus having a high communication bandwidth and improving the computing efficiency of the chip in processing neural networks, especially complex neural networks (e.g., EDSR). In addition, the chip can be fabricated on the same substrate using monolithic three-dimensional integration technology at a low temperature environment of, for example, less than or equal to 300 degrees Celsius. The fabrication process is simple, and the obtained chip structure is compact and small in size.

[0044] The chip and its fabrication method disclosed herein will be described below through several specific embodiments.

[0045] This disclosure provides a chip in at least one embodiment. Figure 2 A schematic diagram of the chip's stacked structure is shown. Figure 3 A three-dimensional structural diagram of the chip is shown. Figure 4 A cross-sectional schematic diagram of part of the chip's structure is shown.

[0046] like Figures 2-4As shown, the chip includes a substrate 11, a control circuit 12, an in-memory computing layer 20, and a near-memory computing layer 30. The control circuit 12 is disposed on the substrate 11, forming a control circuit substrate 10. For example, the control circuit substrate 10 can be a control logic circuit substrate manufactured using standard silicon-based CMOS (Complementary Metal Oxide Semiconductor) technology, which has advantages such as high performance, high reliability, and mature technology. However, due to process temperature and other reasons, only one layer of silicon-based CMOS can be fabricated on a single substrate 11. Therefore, the part of the chip with the highest reliability requirements can be implemented using it.

[0047] The in-memory computing layer 20 and the near-memory computing layer 30 are disposed on the side of the control circuit 12 away from the substrate 11. The in-memory computing layer 20 is disposed on the side of the near-memory computing layer 30 close to the substrate 11 (as shown in the figure) or away from the substrate 11.

[0048] The in-memory computation layer 20 includes multiple memories R. For example, it can compute the product of a vector and a matrix, with the matrix stored in the memory and the vector input to the memory outputting the product result. The in-memory computation layer 20 offers advantages such as low power consumption in its computational implementation.

[0049] The near-memory computing layer 30 includes multiple vertically complementary field-effect transistors T, which can, for example, implement other logic AND operations that cannot be implemented by the in-memory computing layer 20.

[0050] Multiple memory R and multiple vertical complementary field-effect transistors T are electrically connected to the control circuit 12, so that together with the control circuit 12, they can jointly realize the function of processing complex neural networks, such as deep learning super-resolution algorithms.

[0051] For example, as an example, Figure 4 A memory R and a vertically complementary field-effect transistor T are shown in a stacked configuration. Figure 4 As shown, in some embodiments, the multiple memories R can be various types of memories such as resistive switching memory, phase-change memory, magnetic memory, ferroelectric memory, and conductive bridge memory. They can realize in-memory computing modules. Their advantage is that multiple layers of memory can be stacked (one layer is shown in the figure as an example), and matrix-vector multiplication operations in neural networks can be implemented efficiently.

[0052] For example, in some embodiments, such as Figure 4 As shown, each of the plurality of memories R includes a first electrode 21, a second electrode 22, and a resistive switching layer 23 between the first electrode 21 and the second electrode 22.

[0053] For example, in some embodiments, such as Figure 4As shown, each of the plurality of memories R may also include a thermal enhancement layer 34, which is disposed between the first electrode 21 and the resistive switching layer 23 (as shown in the figure) and / or between the second electrode 22 and the resistive switching layer 23, to achieve the effects of heat preservation, heat storage, and optimization of device characteristics.

[0054] For example, in some embodiments, the first electrode 21 and the second electrode 22 can be made of materials such as TiN, W, Pd, Pt, or TaN; the resistive switching layer 23 can be made of HfO2, SiO2, Si3N4, Al2O3, ZnO, MgO, TiO2, Nb2O3, Ta2O5, ZrO2, and multi-element oxides of these elements, such as HfAlOx, HfZrTiOx, etc.; and the thermal enhancement layer 34 can be made of TaO. x Materials such as HfOx or Ta.

[0055] For example, such as Figure 4 As shown, in some embodiments, each of the plurality of vertical complementary field-effect transistors T includes a first semiconductor layer 31 and a first source / drain electrode layer 32, a first insulating layer 33, a first gate G, a second insulating layer 34, a second semiconductor layer 35, and a second source / drain electrode layer 36.

[0056] The first source / drain electrode layer 32 is disposed on the side of the first semiconductor layer 31 away from the substrate 11 (as shown in the figure) or on the side close to the substrate 11, and includes a first source electrode S1 and a first drain electrode D1 disposed at intervals. The first insulating layer 33 is disposed on the side of the first semiconductor layer 31 and the first source / drain electrode layer 32 away from the substrate 11, and includes a first via V1 exposing the first drain electrode D1.

[0057] The first gate G is disposed on the side of the first insulating layer 33 away from the substrate 11, and the second insulating layer 34 is disposed on the side of the first gate G away from the substrate 11, including a second via V2 that exposes the first via V1.

[0058] The second semiconductor layer 35 and the second source / drain electrode layer 36 are disposed on the side of the second insulating layer 34 away from the substrate 11. The second source / drain electrode layer 36 is disposed on the side of the second semiconductor layer 35 away from the substrate 11 (as shown in the figure) or close to the substrate 11, and includes a second source S2 and a second drain D2 disposed at intervals. The second drain D2 is electrically connected to the first drain D1 through the first via V1 and the second via V2.

[0059] The first semiconductor layer 31, the first source / drain electrode layer 32, the first insulating layer 33, and the first gate G constitute a first transistor, and the first insulating layer 33 can serve as the gate oxide layer of the first transistor. The first gate G, the second insulating layer 34, the second semiconductor layer 35, and the second source / drain electrode layer 36 constitute a second transistor, and the second insulating layer 34 can serve as the gate oxide layer of the second transistor. One of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor. Thus, the first transistor and the second transistor of the vertical complementary field-effect transistor share a first gate G, for example, as the input terminal of the vertical complementary field-effect transistor.

[0060] For example, in some embodiments, the first transistor is a P-type transistor, and the material of the first semiconductor layer 31 includes P-type nanomaterials or P-type oxides; the second transistor is an N-type transistor, and the material of the second semiconductor layer 35 includes N-type nanomaterials or N-type oxides. Thus, the field-effect transistor is formed as a vertically complementary field-effect transistor with a P-type transistor at the bottom and an N-type transistor at the top. Both the first semiconductor layer 31 and the second semiconductor layer 35 are made of nanomaterials and oxide materials, which can be fabricated and patterned in low-temperature environments (e.g., below 300 degrees Celsius). Therefore, they can be formed as a subsequent process on the substrate 11 where the control circuit 12 has already been formed, and interconnection with the previously formed circuit can be completed, thereby avoiding the impact of high-temperature processes on the already formed transistors or circuits.

[0061] Alternatively, in some embodiments, the first transistor is an N-type transistor. In this case, the material of the first semiconductor layer 31 includes N-type nanomaterials or N-type oxides, the second transistor is a P-type transistor, and the material of the second semiconductor layer 35 includes P-type nanomaterials or P-type oxides. Thus, the field-effect transistor is formed as a vertically complementary field-effect transistor with an N-type transistor at the bottom and a P-type transistor at the top. Similarly, both the first semiconductor layer 31 and the second semiconductor layer 35 are made of materials such as nanomaterials and oxide materials that can be fabricated and patterned in low-temperature environments (e.g., below 300 degrees Celsius). Thus, they can be formed as a subsequent process on the substrate 11 where the control circuit 12 has already been formed, and interconnection with the previously formed circuit can be completed, thereby avoiding the influence of high-temperature processes on the already formed transistors or circuits.

[0062] For example, in some embodiments, P-type nanomaterials may include CNTs, WSe2, or black phosphorus, and P-type oxides may include SnO; N-type nanomaterials may include MoS2 or WS2, and N-type oxides may include IGZO, ITO, IWO, or IZO. These materials can all be formed / prepared and patterned in low-temperature environments (e.g., below 300 degrees Celsius), and their preparation processes are simple.

[0063] For example, in some embodiments, such as Figure 4 As shown, the first source / drain electrode layer 32 is disposed on the side of the first semiconductor layer 31 away from the substrate 101, and the second source / drain electrode layer 36 is disposed on the side of the second semiconductor layer 35 away from the substrate 101.

[0064] Alternatively, in other embodiments, the first semiconductor layer 31 may be disposed on the side of the first source / drain electrode layer 32 away from the substrate 11; or, the second semiconductor layer 35 may be disposed on the side of the second source / drain electrode layer 36 away from the substrate 11; or, the first semiconductor layer 31 may be disposed on the side of the first source / drain electrode layer 32 away from the substrate 11, while the second semiconductor layer 35 may be disposed on the side of the second source / drain electrode layer 36 away from the substrate 101. However, compared to these embodiments, Figure 4 The field-effect transistors in the illustrated embodiments exhibit better overall performance. For example, when the first semiconductor layer 31 is disposed on the side of the first source / drain electrode layer 32 away from the substrate 11, if the first semiconductor layer 31 is made of nanomaterials such as carbon nanotubes, it is difficult to form the first semiconductor layer 31 on the first source / drain electrode layer 32, or the contact between the first semiconductor layer 31 and the first source / drain electrode layer 32 is relatively poor, thus affecting the device performance. Similarly, when the second semiconductor layer 35 is disposed on the side of the second source / drain electrode layer 36 away from the substrate 11, due to factors such as process technology, the actual field-effect transistor may have relatively weak driving capability.

[0065] For example, in some embodiments, the first transistor is a P-type transistor, the first semiconductor layer 31 includes CNTs, the second transistor is an N-type transistor, and the second semiconductor layer 35 includes IGZO; or, the first transistor is an N-type transistor, the first semiconductor layer 31 includes IGZO, the second transistor is a P-type transistor, and the second semiconductor layer 35 includes CNTs. The fabrication processes of semiconductor materials CNTs and IGZO are simple and easy to control, enabling large-scale integration and facilitating the realization of monolithic (using a single substrate 11) three-dimensional integrated chips.

[0066] For example, in some embodiments, such as Figure 4 As shown, the vertical complementary field-effect transistor T may further include a passivation layer 37, which is disposed on the side of the first semiconductor layer 31 and the first source / drain electrode layer 32 away from the substrate 11. A first insulating layer 33 is disposed on the side of the passivation layer 37 away from the substrate 11. The passivation layer 37 includes a third via V3 that penetrates the first via V1 and the second via V2 to facilitate the interconnection of the first drain D1 and the second drain D2. For example, both the passivation layer 37 and the first insulating layer 33 may be made of a metal oxide insulating material.

[0067] For example, by setting a structure of two oxide layers (i.e., a first insulating layer 33 and a passivation layer 37), the first oxide layer (passivation layer 37) can achieve a good interface with the semiconductor material, and the second oxide layer (first insulating layer 33) can realize a high-k dielectric. A high-k dielectric can enhance gate control capability. Since different semiconductor materials have different matching oxide materials to form a better interface, adding the passivation layer 37 can achieve a better interface with the first semiconductor layer 31.

[0068] For example, in some embodiments, the material of the passivation layer 37 may include Y2O3, and the material of the first insulating layer 33 may include HfO2. HfO2 is a high-k dielectric, which is beneficial for enhancing the gate control capability of transistors, while Y2O3 can have a good interface with nano-semiconductor materials (such as carbon nanotubes).

[0069] For example, such as Figure 4 As shown, when the second source / drain electrode layer 36 is disposed on the side of the second semiconductor layer 35 away from the substrate 11, the second semiconductor layer 36 has a fourth via V4 that penetrates the first via V1, the second via V2 and the third via V3 to facilitate the interconnection of the first drain D1 and the second drain D2.

[0070] For example, in embodiments of this disclosure, the substrate 11 can be a silicon substrate, and the first source / drain electrode layer 32 and the second source / drain electrode layer 36 can be made of metal materials or alloy materials such as palladium, titanium, aluminum, copper, and molybdenum. The materials of the first source / drain electrode layer 31 and the second source / drain electrode layer 32 can be the same or different. The first gate G can also be made of metal materials or alloy materials such as palladium, titanium, aluminum, copper, and molybdenum, and the second insulating layer 34 can be made of insulating materials such as HfO2.

[0071] For example, the vertical complementary field-effect transistors T in the near-memory computing layer 30 can be stacked in multiple layers (one layer is shown in the figure as an example) to achieve computations that cannot be achieved in the in-memory computing layer 20 in the neural network. By stacking the near-memory computing layer 30 directly above or below the in-memory computing layer 20, extremely high communication bandwidth can be obtained through interlayer dielectric vias.

[0072] For example, in some embodiments, the first source S1 and / or the first drain D1 and / or the first gate G of the vertical complementary field-effect transistor T are electrically connected to the first electrode 21 of the memory R, ​​and the second electrode 22 is electrically connected to the control circuit 12.

[0073] For example, in some embodiments, the control circuit 12 includes a plurality of third transistors, each of the plurality of third transistors including a second gate G2, a third source S3 and a third drain D3, and the second electrode 22 is electrically connected to the third drain D3. Figure 4The diagram illustrates a scenario where the first source S1 of a vertical complementary field-effect transistor T is electrically connected to the first electrode 21 of a memory R, ​​and the second electrode 22 of the memory R is electrically connected to the third drain D3 of a third transistor. For example, in some embodiments, the plurality of third transistors may include multiple pairs of P-type and N-type transistors.

[0074] For example, a vertically complementary field-effect transistor (VFET) T and a memory chip R can be connected via interlayer dielectric vias. The size of these interlayer dielectric vias is typically in the hundreds of nanometers range. Compared to millimeter-diameter through-silicon vias (TSVs), interlayer dielectric vias can achieve ultra-high bandwidth interconnects across multiple device layers, significantly improving the efficiency of data exchange within the chip.

[0075] For example, such as Figure 4 As shown, the chip may further include a first passivation layer 41, which is disposed between the in-memory computing layer 20 and the near-memory computing layer 30. The first passivation layer 41 has a first interlayer via 41A, through which the first source S1 and / or the first drain D1 and / or the first gate G are electrically connected to the first electrode 21. For example, the first passivation layer 41 may be made of an inorganic insulating material such as silicon oxide, and the first interlayer via 41A may be implemented in the range of hundreds of nanometers by photolithography.

[0076] For example, in some embodiments, the first interlayer via 41A has a conductive filler 42 to improve the electrical connectivity of the two conductive structures connected through the first interlayer via 41A, reduce contact resistance, and improve data exchange efficiency.

[0077] For example, in some embodiments, the chip may further include a conductive interconnect layer 43 disposed on the side of the first passivation layer 41 away from the substrate 11, including a conductive pattern 43A electrically connected to the conductive filler 42. For example, the planar shape of the conductive pattern 43A may have different patterns, such as straight lines, bends, arcs, etc., to facilitate the connection of two conductive structures at different distances, thereby realizing the interconnection of devices in the two layers.

[0078] For example, in some embodiments, the conductive filler 42 may include tungsten, and the conductive pattern 43A may include aluminum. Tungsten has good electroplating filling properties and does not contaminate semiconductor materials or semiconductor processes; aluminum is easier to etch, facilitating the patterning of the conductive pattern 43A; in addition, both materials are low in cost, which helps to save costs.

[0079] For example, in some embodiments, the chip may further include a second passivation layer 44 disposed on the side of the conductive interconnect layer 43 away from the substrate 11. The second passivation layer 44 has a second interlayer via 44A that exposes a conductive pattern 43A. The first source S1 and / or the first drain D1 and / or the first gate G are electrically connected to the first electrode 21 in sequence through the second interlayer via 44A, the conductive pattern 43A and the conductive filler 42.

[0080] For example, in some embodiments, the second interlayer via 44A may have another conductive filler 45 to improve the electrical connectivity of the two conductive structures connected through the second interlayer via 44A, reduce contact resistance, and improve data exchange efficiency.

[0081] For example, in other embodiments, the control circuit 12 includes a plurality of third transistors, as referenced. Figure 4 Each of the plurality of third transistors includes a second gate G2, a third source S3, and a third drain D3, with the first source S1 and / or the first drain D1 and / or the first gate G electrically connected to the second gate G2 and / or the third source S3 and / or the third drain D3. That is, the plurality of vertically complementary field-effect transistors in the near-memory computing layer 30 can be directly connected to the control circuit 12, not just indirectly connected to the control circuit 12 through the plurality of memories in the in-memory computing layer 20. In this case, the plurality of vertically complementary field-effect transistors in the near-memory computing layer 30 can be electrically connected to the control circuit 12 through at least one interlayer dielectric via in the passivation layer, and the near-memory computing layer 30 can still be disposed on the side of the in-memory computing layer 20 closer to or farther from the substrate 11.

[0082] For example, in some embodiments, reference Figure 3 In the in-memory computing layer 20, multiple memories R located in the same layer can be connected in a simpler way. For example, the first electrodes of multiple memories R located in the same row can be connected together using the same connection electrode, and then electrically connected to the control circuit 12 or the near-memory computing layer 30; the second electrodes of multiple memories R located in the same column can be connected together using the same connection electrode, and then electrically connected to the control circuit 12 or the near-memory computing layer 30.

[0083] Similarly, in the near-memory computing layer 30, multiple vertically complementary field-effect transistors (VFETs) T located on the same layer can be connected in a simpler way. For example, the first sources of multiple VFETs T located in the same row can be connected together using the same connection electrode, and then electrically connected to the control circuit 12 or the near-memory computing layer 30. The first drains of multiple VFETs T located in the same row can also be connected together using the same connection electrode, and then electrically connected to the control circuit 12 or the near-memory computing layer 30. The first gates of multiple memory R located in the same column can be connected together using the same connection electrode, and then electrically connected to the control circuit 12 or the near-memory computing layer 30.

[0084] Similarly, the connection between the in-memory computing layer 20 and the control circuit 12 can also be achieved through the interlayer dielectric vias described above. That is, at least one passivation layer and at least one interlayer vias are provided between the in-memory computing layer 20 and the control circuit 12. The memory in the in-memory computing layer 20 and the third transistor and other devices in the control circuit 12 are electrically connected through the interlayer vias.

[0085] For example, Figure 5 Transmission electron microscope (TEM) images of chips provided in at least one embodiment of this disclosure are shown, such as... Figure 5 As shown, the memory and control circuit 12 in the in-memory computing layer 20 can be electrically connected through multiple passivation layers D, interlayer vias / conductive fillers D1 in the passivation layers, and conductive patterns D2 on the passivation layers D. The number of passivation layers D can be determined according to the complexity of the connection between the in-memory computing layer 20 and the control circuit 12.

[0086] In the chip provided in this embodiment, the in-memory computing layer 20 and the near-memory computing layer 30 can be directly disposed on the substrate 11 on which the control circuit 12 is formed. The in-memory computing layer 20 uses memory R to implement the in-memory computing module, which can efficiently realize matrix-vector multiplication operations in the neural network. The near-memory computing layer 30 can be used to realize calculations that the in-memory computing layer 20 cannot realize in the neural network. Thus, the control circuit 12, the in-memory computing layer 20 and the near-memory computing layer 30 together can jointly realize complex deep neural networks, such as the EDSR network.

[0087] At least one embodiment of this disclosure provides a method for fabricating a chip, comprising: providing a substrate and a control circuit, wherein the control circuit is disposed on the substrate; forming an in-memory computing layer and a near-memory computing layer on the side of the control circuit away from the substrate, wherein the in-memory computing layer is formed on the side of the near-memory computing layer that is close to or away from the substrate; the in-memory computing layer includes a plurality of memories, the near-memory computing layer includes a plurality of vertical complementary field-effect transistors, and the plurality of memories and the plurality of vertical complementary field-effect transistors are electrically connected to the control circuit.

[0088] For example, in some embodiments, forming an in-memory computing layer and a near-memory computing layer on the side of the control circuit away from the substrate includes: forming a plurality of memory cells in the in-memory computing layer and a plurality of vertical complementary field-effect transistors in the near-memory computing layer on the side of the control circuit away from the substrate under process conditions of less than or equal to 300 degrees Celsius.

[0089] Below, with Figure 4 Taking the chip shown as an example, the chip fabrication method provided in this disclosure embodiment will be introduced.

[0090] For example, the fabrication process for forming the control circuit 12 on the substrate 11 can be performed by a foundry, such as a CMOS process. Therefore, the substrate and the control circuit can be provided together, and then an in-memory computing layer 20 and a near-memory computing layer 30 can be formed on the substrate 11 on which the control circuit 12 is formed.

[0091] For example, in some embodiments, combined Figure 4 The process of forming an in-memory computing layer on the side of the control circuit away from the substrate includes: forming a second electrode material layer on the side of the control circuit 12 away from the substrate 11, for example, forming a TiN material layer approximately 30 nm thick on the side of the control circuit 12 away from the substrate 11 using a method such as physical vapor deposition; forming a resistive switching material layer on the side of the second electrode material layer away from the substrate, for example, forming an HfO2 material layer approximately 8 nm thick on the side of the second electrode material layer away from the substrate using a method such as atomic layer deposition; forming a first electrode material layer on the side of the resistive switching material layer away from the substrate, for example, forming a TiN material layer approximately 30 nm thick on the side of the resistive switching material layer away from the substrate using a method such as physical vapor deposition; and then patterning the second electrode material layer, the resistive switching material layer, and the first electrode material layer to form multiple memory R.

[0092] For example, the first electrode material layer, the resistive switching material layer, and the second electrode material layer are all formed on the entire surface of the substrate 11 on which the control circuit 12 is formed. Then, a multilayer pattern of multiple memory Rs is formed through a single patterning process. For example, the single patterning process includes steps such as photoresist formation, exposure, development, and etching. For example, after the second electrode material layer, the resistive switching material layer, and the first electrode material layer are formed sequentially, a photoresist material is coated on the first electrode material layer. Then, the photoresist material is exposed and developed to form a photoresist pattern. Afterward, using the photoresist pattern as a mask, the first electrode material layer, the resistive switching material layer, and the second electrode material layer are simultaneously etched, for example, by dry etching, to form the multilayer pattern of the memory R.

[0093] For example, in some embodiments, the fabrication method further includes forming a thermally enhanced layer between the first electrode and the resistive switching layer and / or between the second electrode and the resistive switching layer. In this case, it is only necessary to form a thermally enhanced material layer on the first electrode material layer after the first electrode material layer is formed, for example, by forming a TaO layer with a thickness of about 45 nm using physical vapor deposition. x Alternatively, after the resistive switching material layer is formed, a reinforcing material layer can be formed on top of it, for example, a TaO layer approximately 45 nm thick can be formed using physical vapor deposition. x Then, the second electrode material layer, the reinforcing material layer, the resistive switching material layer and the first electrode material layer are patterned simultaneously to form multiple memory R.

[0094] For example, in some embodiments, the memory R in the in-memory computing layer 20 can be formed as multiple layers, and the fabrication process of each layer is basically the same, which will not be described in detail here.

[0095] For example, combining Figure 4 After the in-memory computing layer 20 is fabricated, the fabrication method further includes forming a first passivation material layer on the side of the in-memory computing layer 20 away from the substrate 11, for example, forming a silicon oxide layer with a thickness of about 400 nm using plasma-enhanced chemical vapor deposition; and patterning the first passivation material layer, for example, forming a photoresist pattern, and then dry etching the first passivation material layer using the photoresist pattern as a mask to form a first passivation layer 41 with a first interlayer via 41A. Afterwards, a conductive material layer is formed on the side of the first passivation layer 41 away from the substrate 11, for example, forming a tungsten material layer using electroplating, and removing the portion of the conductive material layer outside the first interlayer via 41A, for example, cleaning the portion of the conductive material layer outside the first interlayer via 41A using chemical mechanical polishing, to form a conductive filler 42 in the first interlayer via 41A.

[0096] For example, combining Figure 4 The fabrication method further includes forming a conductive interconnect material layer on the side of the first passivation layer 41 away from the substrate 11, for example, depositing a metal Al layer about 400 nm thick using a physical vapor deposition method, and then patterning the conductive interconnect material layer, for example, forming a photoresist pattern on the conductive interconnect material layer, and then etching (e.g., dry etching) the conductive interconnect material layer using the photoresist pattern as a mask to form a conductive pattern 43A electrically connected to the conductive filler 42.

[0097] For example, combining Figure 4The fabrication method further includes forming a second passivation material layer on the side of the conductive interconnect layer 43 away from the substrate 11, for example, depositing a SiO2 material layer about 1000 nm thick using a plasma-enhanced chemical vapor deposition method, and then patterning the second passivation material layer, for example, forming a photoresist pattern on the second passivation material layer, and then etching (e.g., dry etching) using the photoresist pattern as a mask to form a second passivation layer 44 having a second interlayer via 44A, the second interlayer via 44A exposing the conductive pattern 43A.

[0098] For example, combining Figure 4 The preparation method further includes: depositing a layer of tungsten metal on the second passivation layer 44 by electroplating, and then cleaning the portion of the tungsten metal outside the second interlayer via 44A by chemical mechanical polishing or other methods to form another conductive filler 45 in the second interlayer via 44A, and then forming a first semiconductor layer 31 of a plurality of vertical complementary field-effect transistors T on the side of the second passivation layer 44 away from the substrate 11.

[0099] For example, in some embodiments, forming a first semiconductor layer 31 on the side of the second passivation layer 44 away from the substrate 11 may include: forming a first semiconductor material layer on the side of the second passivation layer 44 away from the substrate 11 under process conditions of less than 300 degrees Celsius, and patterning the first semiconductor material layer to form the first semiconductor layer 31.

[0100] For example, the step of forming the first semiconductor material layer can be carried out by wet transfer (e.g. for nanomaterials), deposition (e.g. for oxide semiconductor material layers), or sputtering, evaporation, etc. Patterning can be carried out by forming photoresist, exposure, development, etching, etc. These methods can all be carried out under process conditions of less than 300 degrees Celsius, so as not to damage the structure already formed above or below the substrate.

[0101] The following describes the subsequent fabrication method of the chip, taking as an example that the first transistor is a P-type transistor, the first semiconductor layer 31 includes CNT, the second transistor is an N-type transistor, and the second semiconductor layer 35 includes IGZO.

[0102] For example, under process conditions of less than 300 degrees Celsius, a first semiconductor material layer is formed on the side of the second passivation layer 44 away from the substrate 11. In this embodiment, the first semiconductor material layer includes CNTs (carbon nanotubes), and a wet transfer method can be used to form the CNT material layer on the side of the second passivation layer 44 away from the substrate 11.

[0103] For example, a first photoresist pattern is formed on a first semiconductor material layer. This can be achieved by methods such as photoresist coating, exposure, and development. The first photoresist pattern includes a first cutout region and a second cutout region corresponding to the first source and first drain, respectively. Next, a first source / drain electrode material layer is formed on the side of the first photoresist pattern away from the substrate. This layer, approximately 30 nm thick, can be formed using electron beam evaporation. For example, in this embodiment, the first source / drain electrode material layer can be made of palladium (Pd). Then, the first photoresist pattern is peeled off, along with the first source / drain electrode material formed above it, thereby forming the first source S1 and the first drain D1.

[0104] For example, after forming the first source S1 and the first drain D1, a second photoresist pattern is formed on the side of the first semiconductor material layer and the first source S1 and the first drain D1 away from the substrate 101. This second photoresist pattern can be formed by methods such as photoresist coating, exposure, and development. The second photoresist pattern covers the formation area of ​​the first semiconductor layer (i.e., the area to be covered by the first semiconductor layer), and may also cover the areas of the first source S1 and the first drain D1. Then, using the second photoresist pattern as a mask, the first semiconductor material layer 1021 is etched, for example, by plasma etching, such as oxygen plasma etching, to etch away the portion of the first semiconductor material layer outside the area covered by the second photoresist pattern. Then, the second photoresist pattern is stripped to form the first semiconductor layer 31. For example, in some examples, the planar pattern of the first semiconductor layer 31 formed by the above configuration is a linear pattern between the first source S1 and the first drain D1.

[0105] For example, in some embodiments, after the first semiconductor layer 31, the first source S1, and the first drain D1 are formed, a passivation material layer can be formed thereon. For example, a passivation material layer of about 10 nm thickness can be formed by deposition. For example, in this embodiment, the passivation material layer can be yttrium oxide (Y2O3).

[0106] For example, after the passivation material layer is formed, a first insulating material layer can be formed on the passivation material layer, for example, by a method using atomic layer deposition equipment to form a first insulating material layer approximately 10 nm thick. For example, in this embodiment, the first insulating material layer can use hafnium oxide as the gate oxide layer of the first transistor.

[0107] For example, combining Figure 4After the passivation material layer and the first insulating material layer are formed, a patterning process can be used to simultaneously form vias in the passivation material layer and the first insulating material layer, thereby forming the passivation layer 37 and the first insulating layer 33. At this time, the passivation layer 37 includes a third via V3, and the first insulating layer 33 includes a first via V1. The third via V3 and the first via V1 penetrate each other.

[0108] For example, the above patterning process includes forming a photoresist pattern on a passivation material layer and a first insulating material layer (e.g., including steps such as coating photoresist, exposing and developing the photoresist material), the photoresist pattern exposing the areas where the third via V3 and the first via V1 will be formed, and then using the photoresist pattern as a mask to etch the passivation material layer and the first insulating material layer, for example, by using ICP etching, to form the interpenetrating third via V3 and first via V1.

[0109] For example, in some embodiments, forming the first gate on the side of the first insulating layer 33 away from the substrate includes: forming a third photoresist pattern on the side of the first insulating layer 33 away from the substrate 11, for example, by coating photoresist, exposure, development, etc., to form the third photoresist pattern, the third photoresist pattern including a third cutout region corresponding to the first gate G, and then forming a first gate material layer on the side of the third photoresist pattern away from the substrate, for example, by vapor deposition to form a first gate material layer about 45 nm thick, in this embodiment, the first gate material layer can be made of palladium (Pd), and then the third photoresist pattern is stripped off, and the first gate material above the third photoresist pattern is also stripped off, thereby forming the first gate G.

[0110] For example, after the first gate G is formed, a second insulating material layer is formed on the side of the first gate G away from the substrate 11. For example, an atomic layer deposition method can be used to form a second insulating material layer approximately 15 nm thick. Then, the second insulating material layer is patterned, for example, by forming a photoresist pattern on the second insulating material layer. This photoresist pattern exposes the first via V1. Then, using the photoresist pattern as a mask, the second insulating material layer is etched, for example, by ICP etching, to form a second via V2 penetrating the first via V1 in the second insulating material layer, thereby forming the second insulating layer 34. For example, in this embodiment, the second insulating material layer includes hafnium oxide (HfO2) as the gate oxide layer of the second transistor.

[0111] For example, in some embodiments, forming a second semiconductor layer 35 and a second source / drain electrode layer 36 on the side of the second insulating layer 34 away from the substrate includes: forming a second semiconductor material layer on the side of the second insulating layer 34 away from the substrate under process conditions of less than 300 degrees Celsius, for example, by deposition, and patterning the second semiconductor material layer to remove material from the second semiconductor material layer located in the second via V2, the first via V1, and the third via V3 to form a fourth via V4.

[0112] Alternatively, in other embodiments, after the second insulating material layer and the second semiconductor material layer are formed on the first gate G, a single patterning process can be used to remove the material of the second insulating material layer and the second semiconductor material layer located in the first via V1 and the third via V3 to form the second via V2 and the fourth via V4.

[0113] For example, a fourth photoresist pattern is formed on the side of the second semiconductor material layer away from the substrate. The fourth photoresist pattern is formed by methods such as coating photoresist, exposure, and development. The fourth photoresist pattern includes a fourth cutout region and a fifth cutout region corresponding to the second source S2 and the second drain D2, respectively. A second source / drain electrode material layer (not shown in the figure) is formed on the side of the fourth photoresist pattern away from the substrate. For example, the second source / drain electrode material layer is formed by vapor deposition. In this embodiment, the second source / drain electrode material layer may include titanium and palladium (Ti / Pd), for example, forming a Ti layer with a thickness of about 20 nm and a Pd layer with a thickness of 65 nm. Then, the fourth photoresist pattern is peeled off, and the second source / drain electrode material on the fourth photoresist pattern is also peeled off to form the second source S2 and the second drain D2.

[0114] For example, after the second source S2 and the second drain D2 are formed, a fifth photoresist pattern is formed on the side of the second semiconductor material layer and the second source S2 and the second drain D2 away from the substrate. This fifth photoresist pattern is formed, for example, by coating photoresist, exposure, and development. The fifth photoresist pattern covers the formation area of ​​the second semiconductor layer, and may also cover the second source S2 and the second drain D2. Then, the second semiconductor material layer is etched, for example, by wet etching or dry etching, to etch away the portion of the second semiconductor material layer outside the area covered by the fifth photoresist pattern. Afterward, the fifth photoresist pattern is stripped to form the second semiconductor layer 35. For example, in some examples, the planar pattern of the second semiconductor layer 35 formed by the above configuration is a linear pattern between the second source S2 and the second drain D2, not shown in the figure.

[0115] For example, in some embodiments, after the vertical complementary field-effect transistor is fabricated, other passivation layers and metal interconnect patterns can be formed on the vertical complementary field-effect transistor to complete the circuit pattern of the overall chip. The specific fabrication process can be referred to the above description and will not be repeated here.

[0116] In summary, the fabrication method provided in this disclosure can form the in-memory computing layer 20 and the near-memory computing layer 30 on the substrate 00 where the control circuit 12 has already been formed at a low temperature. Compared with traditional silicon-based semiconductor fabrication processes, which inevitably introduce high-temperature steps in transistor processes, the high-temperature process can cause the existing circuitry in the lower layer to fail when fabricating other structures on a substrate with existing driving circuitry. Therefore, it is impossible to form memory and vertical complementary field-effect transistors on the same substrate. The embodiments of this disclosure utilize monolithic three-dimensional heterogeneous integration technology to develop fabrication methods and interconnection methods for back-end memory and vertical complementary field-effect transistors. Compared with traditional planar chips, the vertical stacking structure of vertical chips further reduces the chip area and can achieve high density, high performance, multifunctionality, and low power consumption of a single chip.

[0117] For example, Figure 6 This illustration demonstrates the application of a chip according to an embodiment of the present disclosure in implementing a deep learning super-resolution algorithm, the purpose of which is to restore low-resolution images to high-resolution images. Its network structure is as follows: Figure 1 As shown, matrix-vector multiplication in convolution is implemented using in-memory computation layer 20, while other logic and operations, such as data interfaces, routing, caching, and CMOS logic, are implemented using near-memory computation layer 30. Figure 6 As shown in the figure. Simulation of the chip architecture demonstrates that the chip achieves a very high peak signal-to-noise ratio, similar to that of a GPU, indicating that the chip functions normally and its performance is as shown. Figure 7 As shown.

[0118] Figure 7The image on the left is a comparison image, a low-resolution image. Among the four magnified images in the middle, the top left image is the high-resolution version of the low-resolution image, serving as a comparison of the performance of the various methods. The top right image is obtained using bicubic interpolation, where pixels are padded according to certain rules. The images obtained by the GPU and the chip provided in this embodiment are the bottom left and bottom right images, respectively, both obtained using deep learning for super-resolution tasks. By comparing the images and the peak signal-to-noise ratios (PSNRs) obtained by the three methods, it can be seen that the resolution of the images obtained by the chip provided in this embodiment and the GPU using deep learning for super-resolution tasks is not significantly different, and their PSNRs are also similar. This verifies the effectiveness of the chip provided in this embodiment using deep learning for super-resolution tasks.

[0119] Furthermore, by comparing the energy consumption of a GPU and the chip provided in the embodiments of this disclosure when performing the same task, such as... Figure 8 As shown, the chip provided in this embodiment has a relative power consumption that is 149 times lower than that of a GPU; by comparing the runtime of a traditional two-dimensional chip architecture obtained by traditional planar technology with that of the chip provided in this embodiment to perform the same task, as shown... Figure 9 As shown, the chip provided in this embodiment of the disclosure has a speed improvement of 48.3 times compared to traditional two-dimensional chip architectures. Therefore, the chip provided in this embodiment of the disclosure exhibits excellent performance in terms of power consumption and runtime.

[0120] The following points also need to be explained:

[0121] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0122] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0123] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0124] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A chip, comprising: Substrate, The control circuit is disposed on the substrate. An in-memory computing layer and a near-memory computing layer are disposed on the side of the control circuit away from the substrate, wherein the in-memory computing layer is disposed on the side of the near-memory computing layer that is close to or away from the substrate; The in-memory computing layer includes multiple memories, and the near-memory computing layer includes multiple vertical complementary field-effect transistors (VFETs). The multiple memories and the multiple VFETs are electrically connected to the control circuit. Each of the plurality of vertically complementary field-effect transistors includes: A first semiconductor layer and a first source / drain electrode layer, wherein the first source / drain electrode layer is disposed on the side of the first semiconductor layer that is away from or close to the substrate. A first insulating layer is disposed on the side of the first semiconductor layer and the first source / drain electrode layer away from the substrate. A first gate is disposed on the side of the first insulating layer away from the substrate. A second insulating layer is disposed on the side of the first gate away from the substrate. A second semiconductor layer and a second source / drain electrode layer are disposed on the side of the second insulating layer away from the substrate, wherein the second source / drain electrode layer is disposed on the side of the second semiconductor layer away from or close to the substrate.

2. The chip according to claim 1, wherein, The first source-drain electrode layer includes a first source and a first drain disposed at a distance. The first insulating layer includes a first via exposing the first drain. The second insulating layer includes a second via exposing the first via. The second source-drain electrode layer includes a second source and a second drain disposed at a distance. The second drain is electrically connected to the first drain through the first via and the second via. The first semiconductor layer, the first source / drain electrode layer, the first insulating layer, and the first gate constitute a first transistor; the first gate, the second insulating layer, the second semiconductor layer, and the second source / drain electrode layer constitute a second transistor. One of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor.

3. The chip according to claim 2, wherein, The first transistor is a P-type transistor, and the material of the first semiconductor layer includes P-type nanomaterials or P-type oxides; the second transistor is an N-type transistor, and the material of the second semiconductor layer includes N-type nanomaterials or N-type oxides; or The first transistor is an N-type transistor, and the material of the first semiconductor layer includes N-type nanomaterials or N-type oxides. The second transistor is a P-type transistor, and the material of the second semiconductor layer includes P-type nanomaterials or P-type oxides.

4. The chip according to claim 2 or 3, wherein, Each of the plurality of memories includes a first electrode, a second electrode, and a resistive switching layer between the first electrode and the second electrode.

5. The chip according to claim 4, wherein, Each of the plurality of memories further includes: A thermal enhancement layer is disposed between the first electrode and the resistive switching layer and / or between the second electrode and the resistive switching layer.

6. The chip according to claim 4, wherein, The first source and / or the first drain and / or the first gate are electrically connected to the first electrode. The second electrode is electrically connected to the control circuit.

7. The chip according to claim 6, wherein, The control circuit includes a plurality of third transistors, each of which includes a second gate, a third source, and a third drain. The second electrode is electrically connected to the third drain electrode.

8. The chip according to claim 6, further comprising: A first passivation layer is disposed between the in-memory computing layer and the near-memory computing layer, wherein the first passivation layer has a first interlayer via, and the first source and / or the first drain and / or the first gate are electrically connected to the first electrode through the first interlayer via.

9. The chip according to claim 8, wherein, The first interlayer via contains a conductive filler.

10. A method for fabricating a chip, comprising: A substrate and a control circuit are provided, wherein the control circuit is disposed on the substrate. An in-memory computing layer and a near-memory computing layer are formed on the side of the control circuit away from the substrate, wherein the in-memory computing layer is formed on the side of the near-memory computing layer that is close to or away from the substrate; The in-memory computing layer includes multiple memories, and the near-memory computing layer includes multiple vertical complementary field-effect transistors (VFETs). The multiple memories and the multiple VFETs are electrically connected to the control circuit. Each of the plurality of vertically complementary field-effect transistors includes: A first semiconductor layer and a first source / drain electrode layer, wherein the first source / drain electrode layer is disposed on the side of the first semiconductor layer that is away from or close to the substrate. A first insulating layer is disposed on the side of the first semiconductor layer and the first source / drain electrode layer away from the substrate. A first gate is disposed on the side of the first insulating layer away from the substrate. A second insulating layer is disposed on the side of the first gate away from the substrate. A second semiconductor layer and a second source / drain electrode layer are disposed on the side of the second insulating layer away from the substrate, wherein the second source / drain electrode layer is disposed on the side of the second semiconductor layer away from or close to the substrate.

Images