Semiconductor device, compute-in-memory chip, integrated circuit product, and operating method

Abstract

The application provides a semiconductor device, a memory and computing chip, an integrated circuit product and an operation method, and belongs to the technical field of semiconductor devices.The semiconductor device comprises: N MTJ units, any MTJ unit comprising at least two MTJs; a control unit for performing a write operation and a read operation on the N MTJ units; the control unit is used for selectively controlling the current of the write operation, and writing an operation bit sequence into an MTJ in M MTJ units, M being the number of bits of the operation bit sequence; the control unit is used for selectively controlling the current of an operation operation based on the operation bit sequence, injecting the MTJ in the M MTJ units, and controlling the current flowing out of the M MTJ units, and the control duration of the injected or flowing current is a product value of a lock value and a unit time; and the control unit is used for determining an operation result based on a read value of the flowing current of the M MTJ units.The application can be used for providing a magnetic memory and a chip with operation capability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a semiconductor device, an operating method of a semiconductor device, a memory-compute chip and an integrated circuit product. BACKGROUND

[0002] With the application of chips in the fields of big data centers, Internet of Things, new energy vehicles and artificial intelligence and the vigorous development of chip technology, a large amount of unstructured data is generated, and the demand for efficient processing of these data is increasing sharply. In the current traditional von Neumann computing architecture, the computer and the memory are separated, and data transmission is performed through a data bus. However, in the application of chips in the fields of Internet of Things, big data centers and artificial intelligence, the transmission and processing of massive data make the traditional von Neumann computing architecture face the challenges of bandwidth and power consumption, which are respectively referred to as the "memory wall" and the "power wall" problems.

[0003] The technical goal of "memory-compute integration" is to complete the computation within the memory array, break the "memory wall" and "power wall", effectively reduce the power consumption of data transfer, and thus achieve a magnitude improvement in the computing energy efficiency index. Therefore, the technology of realizing a chip with the characteristics of memory-compute integration (memory-compute chip or memory-compute chip) is considered by the industry as one of the disruptive technologies in the post-moore era to solve the bottleneck of von Neumann computing architecture and relieve the pressure of device size miniaturization. However, due to the problems of chip design complexity and manufacturing cost and the lack of application driving, the early memory-compute integration technology only stays in the research stage and has not been applied in practice. The current memory-compute integration technology integrates static random access memory (SRAM) and logic computing units in a single unit. However, the SRAM is actually used as a cache memory, and the logic computing unit performs the actual operation. At the same time, the data storage of SRAM is volatile. This way of memory-compute integration technology still faces the problem of static power consumption. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor device, a memory-compute chip, an integrated circuit product and an operating method, which avoids the need for read-write operation of the semiconductor device in which data as a storage element needs to be operated within the logic computing unit, thereby breaking through the power consumption and chip area bottleneck of the semiconductor device and the memory-compute chip, and realizing a memory-compute chip with substantial operation capability.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application provide a semiconductor device, which comprises:

[0006] N MTJ units, any MTJ unit comprising at least two MTJs, N being a positive integer;

[0007] a control unit configured to perform a write operation and a read operation on the N MTJ units;

[0008] the control unit is configured to selectively control a current of the write operation, and write a sequence of operation bits to MTJs in M MTJ units, M being a number of bits in the sequence of operation bits;

[0009] the control unit is configured to selectively control a current of the operation based on the sequence of operation bits, inject the MTJs in the M MTJ units, and control a current flowing out of the M MTJ units, a control duration of the injecting or flowing out of the current being a product of a lock value and a specified unit time;

[0010] the control unit is configured to determine an operation result based on read values of the current flowing out of the M MTJ units.

[0011] In particular, the control durations of the injecting currents of the MTJs in each of the M MTJ units are locked to increase or decrease exponentially by 2.

[0012] The control durations of the current flowing out of the M MTJ units are locked to increase or decrease exponentially by 2.

[0013] In particular, the operation result is represented as a sum of the read values of the current flowing out of the M MTJ units after the control durations of the current flowing out of the M MTJ units all end.

[0014] In particular, the operation result is composed of a sum of first-type product values, each of the first-type product values being a product of a unit operation value of each of the M MTJ units and a corresponding lock value.

[0015] The unit operation value is composed of a sum of second-type product values, each of the second-type product values being a product of a read value of the current flowing out of each of the MTJs in one of the M MTJ units and a corresponding lock value.

[0016] In particular, all the MTJs in any of the MTJ units share a same bottom electrode, and each of the MTJs has an independent top electrode.

[0017] In particular, the control unit includes a first control transistor array and a second control transistor array.

[0018] A specified transistor in the first control transistor array is configured to selectively control a current flowing out of a bottom electrode of the M MTJ units, wherein the on-off times of the specified transistor are locked to increase or decrease exponentially by 2.

[0019] the specified transistor in the second control transistor array is used for selectively controlling injection of the current of the operation into the top electrode of the specified MTJ in the M MTJ units, wherein the on time of the specified transistor is locked to exponentially increase or decrease by 2 between the on times.

[0020] Specifically, there are P groups of transistors in the specified transistors in the second control transistor array, and whether each group of transistors is on or off is controlled by the operation bit sequence, and P is the number of bits in the operation bit sequence.

[0021] The transistors in the same group are specifically used for selectively controlling injection of the current of the operation into the top electrode of the MTJ in which the same bit value is recorded in the M MTJ units, and the same bit value is the bit value on the same bit position in the operation bit sequence.

[0022] Specifically, in the M MTJ units, the on time of the current flowing out of the jth MTJ unit is 2 j-1 T1, j takes 1 to the number of bits in the operation bit sequence, and T1 is a specified unit time.

[0023] The locking value corresponding to the jth MTJ unit is 2 j-1 .

[0024] Specifically, in any one of the M MTJ units, the on time of the current injected into the MTJ corresponding to the ith bit position is 2 i-1 T2, i takes 1 to the number of bits in the operation bit sequence, and T2 is a specified unit time.

[0025] The locking value corresponding to the MTJ is 2 i-1 .

[0026] Specifically, the rth transistor in the first control transistor array is connected with the bottom electrode in any one of the MTJ units and also connected with the pth source line, and is used for selectively controlling the current flowing out of the any one of the MTJ units, and r and p are positive integers.

[0027] Specifically, the cth transistor in the second control transistor array is connected with the top electrode of the corresponding MTJ in any one of the MTJ units, and also connected with the nth bit line and the mth word line, respectively, and is used for selectively controlling the current injected into the corresponding MTJ, and c, n and m are positive integers.

[0028] Specifically, the semiconductor device is a spin magnetic storage unit.

[0029] The current value of the operation operation is less than the current value of the write operation, and the direction of the current of the operation operation is the same as the direction of the current of the read operation.

[0030] Specifically, the control unit includes a CMOS logic unit.

[0031] The control unit is configured to, in the first period of the write operation, apply a first VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the specified MTJ unit, and write the first type of bit value in the bit sequence to be written into the specified MTJ unit by the CMOS logic unit and the configured SOT current.

[0032] The control unit is configured to, in the second period of the write operation, apply a second VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the specified MTJ unit, and write the second type of bit value in the bit sequence to be written into the specified MTJ unit by the CMOS logic unit and the configured SOT current.

[0033] Specifically, the CMOS logic unit includes an XOR gate and an AND gate.

[0034] Specifically, the control unit is configured to, in the read operation, apply a VCMA voltage to the top electrode of the MTJ corresponding to the bit to be read, control the SOT current injected into the MTJ, and determine the read value of the current flowing out of the MTJ unit where the MTJ is located.

[0035] Specifically, the control unit is configured to, in the read operation, apply a VCMA voltage to the top electrode of the MTJ corresponding to the bit to be read, control the SOT current injected into the MTJ, and determine the read value of the current flowing out of the MTJ unit where the MTJ is located.

[0036] The control duration of the injected current exponentially increases or decreases between the at least two bits.

[0037] Embodiments of the present application provide a semiconductor device, which comprises:

[0038] A control unit includes at least three transistors, and the at least three transistors are formed on a substrate.

[0039] An MTJ unit includes at least two MTJs, and the structure of the at least two MTJs is a nanorod structure, and the nanorod structure is grown in the region of at least two transistors of the at least three transistors.

[0040] The at least two MTJs have a same bottom electrode, and each MTJ has an independent top electrode.

[0041] The top electrodes of the at least two MTJs are respectively connected with the at least two transistors, and the bottom electrodes of the at least two MTJs are connected with one of the at least three transistors.

[0042] Embodiments of the present application provide an operation method of a semiconductor device, wherein the semiconductor device comprises N MTJ units and a control unit, any MTJ unit comprises at least two MTJs, N is a positive integer; the control unit is used for performing a write operation and a read operation on the N MTJ units; the operation method is performed by the control unit, and the operation method comprises:

[0043] selectively control a current of the write operation, and write an operation bit sequence to an MTJ in M MTJ units, M is a bit number of the operation bit sequence;

[0044] based on the operation bit sequence, selectively control a current of an operation operation, inject the MTJ in the M MTJ units, and control a current flowing out of the M MTJ units, and a control duration of the injected or flowing current is a product value of a lock value and a specified unit time;

[0045] based on a read value of the flowing current of the M MTJ units, determine an operation result.

[0046] In still another aspect, embodiments of the present application provide a memory and computing chip, which comprises the foregoing semiconductor device.

[0047] In yet another aspect, embodiments of the present application provide an integrated circuit product, which comprises at least one processor and the foregoing semiconductor device, the semiconductor device being connected with the at least one processor; or the integrated circuit product comprises the foregoing memory and computing chip.

[0048] The semiconductor device comprising MTJ cells with magnetic tunnel junctions (MTJs) in this invention is a non-volatile memory, specifically a magnetic random access memory (MRAM). When logical calculations are required on the bit sequence to be operated on, this invention first performs a write operation on the MTJ cell based on the characteristics of the operand and bit sequences, using the control unit. Then, the result of the bit operation is obtained by reading the current flowing out of the MTJ cell using the current from the operation. This eliminates the need to read the operand and operand bit sequences into a logic calculation unit (e.g., an arithmetic logic unit or register file) or to perform the calculation through that unit. Specifically, the calculation is a multiplication operation, thus overcoming the power consumption and chip area bottlenecks of semiconductor devices and products with the same data storage capacity.

[0049] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0050] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0051] Figure 1 This is a schematic diagram of the stacking structure of MTJ used in an embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram of an exemplary MTJ unit according to an embodiment of the present invention;

[0053] Figure 3 This is a schematic diagram of an exemplary MTJ unit according to an embodiment of the present invention;

[0054] Figure 4 This is a schematic diagram of an exemplary array-type semiconductor device according to an embodiment of the present invention;

[0055] Figure 5 This is a schematic diagram of an exemplary CMOS logic cell according to an embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram of an exemplary MTJ unit with 8 MTJs according to an embodiment of the present invention;

[0057] Figure 7 This is a schematic diagram of an exemplary MTJ unit performing a first-cycle write operation according to an embodiment of the present invention;

[0058] Figure 8 An exemplary MTJ cell diagram for performing a second cycle write operation for an embodiment of the present application;

[0059] Figure 9 An exemplary MTJ cell diagram for performing a single bit read operation for an embodiment of the present application;

[0060] Figure 10 An exemplary MTJ cell diagram for performing a two bit read operation for an embodiment of the present application;

[0061] Figure 11 An exemplary MTJ cell diagram for performing a four bit read operation for an embodiment of the present application;

[0062] Figure 12 An exemplary MTJ cell diagram for performing an eight bit read operation for an embodiment of the present application;

[0063] Figure 13 An exemplary MTJ cell diagram for performing a 2x2 bit scale operation for an embodiment of the present application;

[0064] Figure 14 An exemplary MTJ cell diagram for performing a 4x3 bit scale operation for an embodiment of the present application;

[0065] Figure 15 An exemplary integrated circuit product diagram for an embodiment of the present application;

[0066] Figure 16 An exemplary integrated circuit product diagram for an embodiment of the present application. DETAILED DESCRIPTION

[0067] The specific embodiments of the present application will be described in detail below with reference to the drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of the present application.

[0068] Applicants find that based on new non-volatile memory technology (such as resistive random access memory, phase change memory, spin magnetic memory, etc.), it is expected to find a real solution of storage and computing integrated chip. Among them, the emergence and experimental research of spin magnetic memory devices such as spin-transfer torque magnetoresistive random access memory (STT-MRAM) and spin-orbit torque magnetoresistive random access memory (SOT-MRAM) bring new hope for faster development of storage and computing integrated technology. The resistance storage principle of MRAM in the embodiment of the application can not only be used for storing data, but also can realize computing capability.

[0069] The structure of the MTJ in the MRAM can include two ferromagnetic layers of ferromagnetic material and a very thin insulating oxide barrier layer of non-ferromagnetic insulating material between the two ferromagnetic material layers; one of the two ferromagnetic material layers has a substantially fixed magnetization vector and is called a pinned layer (PL), and the other has a magnetization vector that forms a stable direction parallel or antiparallel to the direction of the pinned layer under the action of a magnetic field, and is called a free layer (FL).

[0070] As an example of an embodiment of the application, as shown in Figure 1 , the structure of the MTJ is an MTJ nanopillar (MTJ_np), the ferromagnetic material layer is a cobalt-iron-boron (CoFeB) layer, and the non-ferromagnetic insulating material layer is a magnesium oxide (MgO) layer, and the three material layers form a magnetic tunnel junction; the magnetization vector of the pinned layer PL is not easy to flip and the direction of the magnetization vector is opposite to the oxide barrier layer OB, that is, the direction from the distal surface of the pinned layer PL to the proximal surface, that is Figure 1 upward. For example, the MTJ nanopillar is suitable for an STT current switching state mechanism, and when the value of the STT current I STT injected into the MTJ nanopillar is greater than the value of the flip threshold current I C0 , the magnetization vector of the free layer FL is easy to flip. If the direction of the current I STT is from the free layer FL to the pinned layer PL, so that the direction of the magnetization vector of the free layer FL is opposite to the direction of the magnetization vector of the pinned layer PL, at this time the MTJ nanopillar is in an anti-parallel (AP) state, and if the direction of the current I STTThe direction of the magnetization vector of the pinned layer PL is the same as the direction of the magnetization vector of the free layer FL, so that the direction of the magnetization vector of the free layer FL is also the same as the direction of the magnetization vector of the pinned layer PL, at this time, the MTJ nanocolumn is in a parallel (Parallel, denoted as: P) state, and therefore, the magnetization vector of the entire MTJ has two states of parallel and antiparallel. Correspondingly, the MTJ exhibits two states of high resistance (corresponding to the AP state) and low resistance (corresponding to the P state) in the resistance size. By using the resistance change between the two states, single-bit data storage can be realized, for example, the P state corresponds to the bit value (i.e., the logic value) "0" of the data, and the AP state corresponds to the bit value (i.e., the logic value) "1" of the data. Table 1 shows the relationship between the MTJ state and the logic value.

[0071] Table 1 MTJ state and logic value relationship table

[0072] MTJ state Logical value AP state 1 P state 0

[0073] It can be understood that this is a configurable example but not a limiting embodiment. If a transistor for controlling data reading and writing (as a logic control circuit) is added, an MRAM storage unit is formed. In the embodiment of the present application, for the purpose of simple notation, "MTJ" can represent a stack with a magnetic tunnel junction function, and the stack can have an electrode layer; the above-mentioned STT current will be used as a component current of the SOT current in the subsequent content.

[0074] MRAM has the advantages of non-volatility, high integration, low power consumption, high durability, etc. Compared with the read-write speed of SRAM / dynamic random access memory (DRAM), the MRAM storage unit is a resistance type device, which is more suitable for data reading and writing under current driving, and MRAM also has the characteristics of fast reading and writing. At the same time, like the flash memory, the data of MRAM is not easy to lose power. The silicon wafer area occupied by the unit storage capacity of MRAM has an advantage over SRAM, NOR flash / embedded NOR flash. The read-write delay of MRAM is close to that of top SRAM, and MRAM has more excellent power consumption performance among various memories and storage technologies. Most notably, the manufacturing process of MRAM is compatible with the standard CMOS semiconductor process, while the manufacturing process of DRAM / flash is not compatible with the standard CMOS semiconductor process. MRAM can be integrated with a logic control circuit into the same chip, which has application prospects and value. Therefore, the embodiment of the present application provides an MRAM storage and computing integrated solution.

[0075] Embodiment 1

[0076] The embodiment of the present application provides a semiconductor device, which can include:

[0077] N MTJ cells, any MTJ cell comprising at least two MTJs, N being a positive integer;

[0078] a control unit for performing write operation and read operation on the N MTJ cells;

[0079] the control unit for selectively controlling current of the write operation, writing an operation bit sequence to an MTJ of the M MTJ cells, M being the number of bits of the operation bit sequence and M≤N;

[0080] the control unit for selectively controlling current of the operation operation, injecting the MTJ of the M MTJ cells based on the operation bit sequence, and for controlling current flowing out of the M MTJ cells, the control duration of the injected or flowing current being a product of a (configured) lock value and a specified unit time; the control unit for determining the operation result based on a read value of the flowing current of the M MTJ cells.

[0081] In embodiments of the present application, the semiconductor device is a non-volatile memory cell, which is also a spin magnetic storage cell / electron spin device. The MTJ cell is a physical, spin magnetic storage medium; any MTJ cell has at least two MTJs, for example, 2 MTJs, 4 MTJs, 8 MTJs, 16 MTJs, etc., and the structure of each MTJ in the MTJ cell can be a stacked structure, such as a nanocolumn; in some application scenarios, the number of MTJs in any MTJ cell can be consistent with 2 a or an even number, a=1, 2, 3…, and in some customized application scenarios, the number of MTJs in any MTJ cell can be a customized number, such as an odd number or a specified number. The control unit can include a plurality of transistors, the manufacturing process of which is compatible with the manufacturing process of the MTJs in the MTJ cell, and the transistors can connect each MTJ to a word line (Wordline, which can be abbreviated as WL) and a bit line (Bitline, which can be abbreviated as BL), for performing instruction operation on each MTJ cell, which can include write (instruction) operation and / or read (instruction) operation. In this way, any one MTJ cell and transistor can form a memory cell, which is a bit-cell that records binary values / bits. Any one MTJ in the memory cell can correspond to a specified bit associated with the word line and the bit line, so that any two MTJs in the memory cell correspond to bits with high and low characteristics.

[0082] In any given MTJ unit, all MTJs share the same bottom electrode, and each MTJ has an independent top electrode. The bottom electrode is the bottom electrode layer, and the top electrode is the top electrode layer. Both the bottom electrode and the top electrode can be metal layers. The metal layers can be made of metals such as gold or copper, or conductive materials containing metal elements. The materials of the two electrode layers can be the same or chosen independently. The bottom electrode is in contact with the free layer of any MTJ in the MTJ unit, or the distance between the bottom electrode and the free layer of any MTJ is less than the distance between the bottom electrode and the pinned layer of any MTJ. That is, there can be a bottom functional layer structure between the bottom electrode and the free layer of any MTJ, such as a layer structure for buffering (facilitating manufacturing), controlling the magnetization vector, or adjusting the exchange bias field (the exchange bias field can also be generated at the bottom electrode). The top electrode is in contact with the pinned layer of any MTJ in the MTJ unit, or the distance between the top electrode and the pinned layer of any MTJ in the MTJ unit is less than the distance between the top electrode and the free layer of any MTJ. That is, there can be a top functional layer structure between the top electrode and the pinned layer of any MTJ, such as a layer structure for buffering. The bottom electrode can also be in contact with a designated substrate region. It is understood that there is no distinction between top and bottom electrodes. In this embodiment of the invention, relative to the layer structure of MTJ, the direction from the free layer to the studded layer can be the orientation of the top, and the direction from the studded layer to the free layer can be the orientation of the bottom. This is only a simplified way of explaining.

[0083] Based on the above, as the first exemplary MTJ unit structure example disclosed in this invention, see [link to relevant documentation]. Figure 2 An MTJ unit can include two MTJs. The layer structure of an MTJ can include a free layer, a barrier layer, and a pinned layer, and also includes a top electrode and a bottom electrode. Figure 2 In the middle, double-headed arrows are used. The MTJ state is indicated by either the AP or P state. A unidirectional arrow "↑" represents the characteristic that the state of the pinned layer is not easily changed. There is a barrier layer without an arrow between the free layer and the pinned layer. The top electrode (layer) is represented by a shorter gray area perpendicular to the direction from the free layer to the pinned layer, and the bottom electrode (layer) is represented by a longer gray area perpendicular to this direction. MTJ L PL nail-rolled layer L With top electrode TE L Independent contact, MTJ R PL nail-rolled layer R With top electrode TE R Independent contact, MTJ L free layer FL L and MTJ R free layer FL LThe MTJ units are in contact with the bottom electrode BE, share the bottom electrode BE, one MTJ unit can include one bottom electrode BE, and the two MTJ units have a specified interval distance between the contact areas on the bottom electrode BE along the extension direction of the bottom electrode BE (also along the direction perpendicular to the pinning layer of the free layer). At this time, the control unit can include three transistors, the top electrode TE L and the top electrode TE R are connected with the transistor M L , the transistor M R respectively, and the bottom electrode BE is connected with the transistor M0 and the ground terminal respectively. Among them, the top electrode TE L of the MTJ L is not in contact with the top electrode TE R of the MTJ R , the pinning layer PL L of the MTJ L is not in contact with the pinning layer PL R of the MTJ R , the barrier layer OB L of the MTJ L is not in contact with the barrier layer OB R of the MTJ R , and the free layer FL L of the MTJ L is not in contact with the free layer FL R of the MTJ R .

[0084] On the basis of Figure 2 , as a second exemplary MTJ unit structure example disclosed by the present application, referring to Figure 3 , one MTJ unit can include four MTJs, MTJ 00 - MTJ 03 , the top electrode TE 00 - TE 03 is connected with the transistor M 00 - M 03 respectively, and the four contact areas of the free layer FL 00 - FL 03 on the bottom electrode BE are arranged at equal interval distances along the extension direction of the bottom electrode BE, which is conducive to the implementation of multi-bit read and write operation. In the embodiment of the present application, in order to simplify the purpose of record, no distinguishing text number "first", "second" and the like is added, for example, MTJ 00 - MTJ 03 may represent: first (having a magnetic tunnel junction function) stack MTJ 00 , second stack MTJ 01 , third stack MTJ 02 and fourth stack MTJ 03 ; the top electrode TE00 TE 03 TE 00 TE 01 TE 02 TE 03 TE

[0085] In an exemplary embodiment disclosed herein, a semiconductor device has a plurality of MTJ cells arranged therein, each of the MTJ cells has a same number of MTJs, a same arrangement of the MTJs, and the like, each of the MTJ cells can include eight MTJs, the eight MTJs can share a bottom electrode, the bottom electrode can have a strip shape, and the eight MTJs can be arranged at equal intervals along an extension direction of the bottom electrode. A first control transistor array in a control unit has at least one transistor, and the at least one transistor connects the bottom electrode of the MTJ cell to a source line (SL). A second control transistor array in the control unit has eight transistors, the eight transistors can be a first control transistor group, the eight transistors can correspond to the eight MTJs respectively, and any one of the eight transistors connects a top electrode of the MTJ corresponding to the any one of the eight transistors to a word line and a bit line.

[0086] In this example, the at least one transistor mentioned above can be the rth transistor, one end of the strip-shaped bottom electrode can be connected to the pth source line through the rth transistor, the rth transistor is controlled by a specified control signal which can be generated by a signal generator, the rth transistor can be used to selectively control the current flowing out of each MTJ cell, and the pulse width of the control signal can be used to lock the control duration of the rth transistor; in the semiconductor device mentioned above, the MTJ cell adjacent to the arrangement position of the MTJ cell mentioned above, the bottom electrode of the adjacent MTJ cell can be connected to the p-1th source line through the r-1th transistor, or can be connected to the p+1th source line through the r+1th transistor. The eight MTJs mentioned above can be considered to be arranged in a relative order in the extension direction of the bottom electrode, for example, the 1st MTJ, the 2nd MTJ, …, the cth MTJ, …, the 8th MTJ, the cth MTJ in the eight MTJs mentioned above corresponds to the cth transistor, the top electrode of the cth MTJ is connected to the nth bit line through the cth transistor and is also connected to the mth word line, the cth transistor is controlled by the mth word line, the c-1th transistor is controlled by the m-1th word line or the c+1th transistor is controlled by the m+1th word line, the c-1th transistor, the cth transistor and the c+1th transistor can be used to selectively control the current injected into each MTJ, and the pulse width of the control signal on the word line can be used to lock the control duration of the transistor connected to the corresponding word line; the second control transistor array in the control unit has another eight transistors, which can be a second control transistor group, the top electrode of the cth MTJ in the adjacent MTJ cell is connected to the n+1th bit line or the n-1th bit line through the cth transistor in the second control transistor group and is also connected to the mth word line, and the cth transistor in the second control transistor group is controlled by the mth word line. Wherein, r, p, c, n, m are positive integers. The correspondence between elements and bit positions in the semiconductor device is shown in Table 2.

[0087] Table 2: Correspondence between elements and bit positions in the semiconductor device

[0088]

[0089] In Table 2, two MTJ cells in the semiconductor device are shown, BL n represents the nth bit line (in some cases, the subscript starts from 0, so BL0 represents the 1st bit line, BL n represents the n+1th bit line), WL m represents the mth word line, SL p represents the pth source line, MTJU M represents the Mth MTJ cell, MTJ Mc represents the cth MTJ in the Mth MTJ cell (the number of MTJs in each MTJ cell is at least two), Qr represents a transistor in the first control transistor array corresponding to the Mth MTJ unit (i.e., the rth transistor), Q Mc represents a transistor in the second control transistor array corresponding to the Mth MTJ unit (i.e., the cth transistor), CMc represents a bit corresponding to the cth MTJ in the Mth MTJ unit; and BL n-1 represents the n-1th bit line and is adjacent to (index ±1) BL n is adjacent (index ±1), MTJU M-1 represents the M-1th MTJ unit and is adjacent to MTJU M is adjacent, and so on, to obtain the corresponding relationship between more elements in the semiconductor device and the corresponding relationship with the bit. It can be understood that the index of the MTJ represents the positioning area of the MTJ in the semiconductor device, which can be determined by the corresponding bit line and word line, for example, the word line can represent the column address information of the corresponding MTJ, and the bit line can represent the row address information of the corresponding MTJ, or in more cases, the word line can represent the row address information of the corresponding MTJ, and the bit line can represent the column address information of the corresponding MTJ.

[0090] As an exemplary array type semiconductor device disclosed by the present application, as Figure 4 (transistor identifier rewritten as Q), the semiconductor device can include M MTJ units, each of which can include 8 MTJs, which are arranged at equal intervals, and in combination with Table 2, the corresponding relationship between each MTJ and the bit, transistor, word line, bit line, and source line can be observed. For MTJU0~MTJU M , MTJ 00 ~MTJ 07 , MTJ 10 ~MTJ 17 ……MTJU M , MTJ M0 ~MTJ M7 . The M MTJ units are connected to the source lines (SL0~SL r ) through r transistors in the first control transistor array, Q0~Q p . The MTJs are connected to the corresponding bit lines and word lines through the corresponding transistors (Q 00 ~Q M7 ) in the second control transistor array, forming memory cells, and the bit is C00~CM7. The high and low characteristics of the bit are consistent in each MTJ unit, for example, MTJ 11 is connected to the second bit line BL1 through transistor Q 11 and is connected to the second bit line BL1 through transistor Q 11The gate of the second control transistor array is connected with the second word line WL2, and the gate of the first control transistor array is connected with the first word line WL1. 11 The corresponding bit is C11. The transistors in the first control transistor array and the second control transistor array are gated by specified signal sources, and the gating time of the transistors is controlled by pulse width. Each signal source can be realized by a signal generator, or the gate of the transistor can be connected with a port generating a voltage signal.

[0091] The magnetic anisotropy of the semiconductor device in the embodiment of the application is voltage-controlled. The MTJ in the semiconductor device is a voltage-controlled magnetic anisotropy (VCMA) MTJ, denoted as VCMA-MTJ. With respect to the pinning layer PL of the MTJ, the magnetic anisotropy of the MTJ is controlled by a transistor in a second control transistor array corresponding to the MTJ and a bit line connected with the transistor. The MTJ can be connected with an external voltage V b (applied on a bit line corresponding to the MTJ), and the external voltage V b of the specific size makes the magnetization direction of the free layer FL of the MTJ more / less likely to be flipped by a current. In the embodiment of the application, the following configurations can be used.

[0092] AP state: when the external voltage V b is higher than the critical flipping voltage V c and the external voltage V b is a positive voltage, the SOT current (component current) configured switches the state of the MTJ to the AP state after passing through the MTJ;

[0093] P state: when the external voltage V b is higher than the critical flipping voltage V c and the external voltage V b is a negative voltage, the SOT current (component current) configured switches the state of the MTJ to the P state after passing through the MTJ;

[0094] read MTJ state: when the external voltage V b is lower than the critical flipping voltage V c and the external voltage V b is a negative voltage, or when the external voltage V b is 0, the SOT current (component current) configured does not easily flip the state of the MTJ after passing through the MTJ, i.e., the state of the MTJ remains unchanged before the external voltage V b is applied.

[0095] The positive and negative are relative, for example, the positive voltage is a voltage value greater than 0 applied to the MTJ pegging layer PL, and the negative voltage is a voltage value less than 0 applied to the MTJ pegging layer PL, and the direction of the magnetization vector of the pegging layer PL is the direction from the free layer FL to the pegging layer PL.

[0096] In the write operation of the embodiment of the application, in some application scenarios, the aforementioned SOT current can be a spin-orbit torque current injected into the MTJ cell through the bottom electrode of the MTJ cell and having a component current flowing out from the top electrode of the MTJ, and the state of the MTJ is switched to the AP state, or a spin-orbit torque current having a component current injected from the top electrode of the MTJ and flowing out from the bottom electrode of the MTJ, and the state of the MTJ is switched to the P state; the value of the SOT current in the read operation can be smaller than the value of the SOT current in the write operation, and the SOT current in the read operation is a spin-orbit torque current having a component current injected from the top electrode of the MTJ and flowing out from the bottom electrode of the MTJ, and the SOT current in the write operation can change the state of the MTJ, and the SOT current in the read operation cannot change the state of the MTJ.

[0097] The aforementioned control unit can further include a CMOS logic unit. The manufacturing process of the CMOS logic unit is also compatible with the manufacturing process of the MTJ cell, and the CMOS logic unit can serve as a gating control function in the write operation and can be placed in the control unit of the aforementioned semiconductor device. The CMOS logic unit can include an XOR gate and an AND gate, and the XOR gate and the AND gate can each have two input terminals. The XOR gate and the AND gate can correspond to a specified bit, which can be a bit corresponding to the same word line, and the XOR gate and the AND gate can constitute a pair of elements. In some application scenarios, the XOR gate and the AND gate corresponding to the mth word line WL m The corresponding bit C(M-1)c and bit CMc, etc.; the number of MTJs in the storage unit or the number of transistors in the second control transistor array for controlling each storage unit is the same as the number of pairs of elements constituted by the XOR gate and the AND gate.

[0098] For a pair of XOR gate and AND gate, the input terminals of the XOR gate can respectively receive the control (instruction / ) signal (denoted as W1 / 0 signal, or denoted as Write signal) of the first period or the second period of the write operation and receive the bit value on the specified sequence bit of the bit sequence to be written; the input terminals of the AND gate can respectively receive the control (instruction / ) signal of the VCMA of the write operation, denoted as VCMA voltage, and the size and the positive and negative directions of the VCMA voltage depend on the external voltage V bthe control duration of the VCMA voltage depends on the configured pulse width voltage signal, denoted as WPD1 signal, and the input of an AND gate also receives the output value / signal of the XNOR gate, the output of the XNOR gate is connected, and the output of the AND gate is connected to a designated word line (the output value / signal of the AND gate accesses a designated word line), for gating control of the column of MTJs corresponding to the word line. It can be understood that the WPD1 signal provides the control duration of the applied voltage V b The WPD1 signal can include low voltage (logic value 0) and high voltage (logic value 1), and the W1 / 0 signal can also include low voltage and high voltage.

[0099] The write operation of the embodiment of the application can be referred to as a "dual cycle 1 / 0" write operation.

[0100] In the first write operation example, in the first cycle (time) of the write operation, when the W1 / 0 signal is set to low (logic value 0) and the WPD1 signal corresponding to the designated bit line is set to high (logic value 1), the magnitude of the negative applied voltage V b is higher than the critical flipping voltage V c At this time, the applied WPD1 signal and the applied voltage V b , i.e. the first VCMA voltage, through the CMOS logic unit and the configured SOT current (component current injected from the top electrode of each MTJ), can write the first type of bit value in the bit sequence / data to be written into the MTJ of the designated MTJ unit in the storage unit; in the second cycle of the write operation, when the W1 / 0 signal is set to high (logic value 1) and the WPD1 signal corresponding to the designated bit line is set to high (logic value 1), the magnitude of the positive applied voltage V b is higher than the critical flipping voltage V c At this time, the applied WPD1 signal and the applied voltage V b , i.e. the second VCMA voltage, through the CMOS logic unit and the configured SOT current (component current flowing out from the top electrode of each MTJ), can write the second type of bit value in the bit sequence / data to be written into the MTJ of the storage unit. The CMOS logic unit functions to select the bit position corresponding to the MTJ to be written in the different cycles of the write operation and match the bit value to be written in the bit sequence to be written. The first cycle and the second cycle can be configured based on a reference clock or pulse width.

[0101] In the second write operation example, in the first cycle of the write operation, when the W1 / 0 signal is set to high (logic value 1) and the WPD1 signal corresponding to the designated bit line is set to high (logic value 1), the positive applied voltage V b is higher than the critical flipping voltage V c , at this time the applied WPD1 signal and the applied voltage V b , i.e. the first VCMA voltage, through the CMOS logic unit and the configured SOT current (component current flows out from the top electrode of each MTJ), can write the first type of bit value in the bit sequence / data to be written into the MTJ of the designated MTJ cell in the bit line; in the second cycle of the write operation, when the W1 / 0 signal is set to low (logic value 0) and the WPD1 signal corresponding to the designated bit line is set to high (logic value 1), the negative applied voltage V b is higher than the critical flipping voltage V c , at this time the applied WPD1 signal and the applied voltage V b , i.e. the second VCMA voltage, through the CMOS logic unit and the configured SOT current (component current flows out from the top electrode of each MTJ), can write the second type of bit value in the bit sequence / data to be written into the MTJ of the designated MTJ cell in the bit line.

[0102] As an exemplary array structure of CMOS logic units matching the aforementioned array type semiconductor device example, see Figure 5 , the CMOS logic unit can include 8 pairs of paired elements composed of XNOR gates and AND gates. For example, in the first pair of elements, the XNOR gate XNOR0 receives the W1 / 0 signal and the bit value corresponding to the designated bit D0 in the data bit; the AND gate AND0 receives the output value of the XNOR gate XNOR0 output end and the WPD1 signal, and the output value C:0 of the AND gate AND0 output end will be used to select the first word line WL0, and the selection of the word line of the remaining paired elements in the CMOS logic unit can be similarly derived, and will not be described again.

[0103] In the above write operation, the voltage drop direction of both the first and second VCMA voltage can change the energy barrier of the MTJ. The VCMA voltage is applied to the top electrode of the MTJ, and in this configuration, by configuring the magnitude of the SOT current, the magnitude of the VCMA voltage applied to the target MTJ (i.e., the MTJ corresponding to the bit to be written or read) can be adjusted, so that the target MTJ can be selectively written or read as mentioned later. The selection of the target MTJ is achieved by switching the transistors in the first and second control transistor arrays as mentioned above. In the read operation, a reverse and small magnitude VCMA voltage (i.e., the applied voltage V b is negative and lower than the voltage V c ) or no voltage is applied to the MTJ, the energy barrier of the MTJ is high, and the SOT current is not sufficient to drive it to flip, and the corresponding MTJ state will not change; in the write operation, a forward / negative and large magnitude VCMA voltage (i.e., the applied voltage V b is forward or negative and higher than the voltage V 17 ) is applied to the MTJ, the energy barrier of the MTJ is low, and the SOT current can drive it to flip to the specified state, and the corresponding MTJ state will change. In the embodiment of the present application, bit correspondence means that the bit position of the specified bit in the to-be-written bit sequence is consistent / unique with the bit position of the specified MTJ in the bit positions corresponding to all the MTJs of the storage unit, i.e., the specified bit and the specified MTJ are bit corresponding / are in a bit corresponding relationship, and the specified bit value can be written to the specified MTJ, which is achieved by selective switching of the transistors.

[0104] As an example of a write operation scenario of the array semiconductor device as mentioned above, the to-be-written bit sequence D[7:0] is 10110100, and the bit positions are sequentially denoted as D0 to D7. If the to-be-written bit sequence is written to the second MTJ unit MTJU1, as shown in Figure 6 , the MTJ state in MTJU1 is any one of the AP state and the P state, and the MTJ farthest from the second transistor Q1 in the first control transistor array along the extension direction of the bottom electrode BE1 of MTJU1 is the lowest bit position, and according to the second write operation example as mentioned above, the first period is configured to write a logical value 1 (i.e., the first type of bit value at this time), and the second period is configured to write a logical value 0 (i.e., the second type of bit value at this time), then the MTJ 10 , MTJ 12MTJ 13 MTJ 15 performing a write operation, and then the MTJ 11 MTJ 14 MTJ 16 MTJ 17 performing a write operation. The write operation of the semiconductor device can include:

[0105] W1) providing a first VCMA voltage VCMA1 to the MTJ U1:

[0106] based on the specified row-column address signals, selecting the MTJ U1 (latching the address information in the row-column address signals) via a row-column decoder, connecting the second bit line BL1 to a forward applied voltage V b , and setting the WPD1 signal to high level;

[0107] W2) configuring the signal size, and based on the bit sequence to be written and the configured signal, selecting the word line:

[0108] As Figure 7 , setting the W1 / 0 signal to high level (logic value 1), and simultaneously inputting D0 to D7 in the aforementioned bit sequence to be written D[7:0] into each XNOR gate in 8 pairs of XNOR gates and AND gates in the CMOS logic unit, respectively, and connecting the output signals C:0~C:7 of the 8 AND gates of the CMOS logic unit to the word lines WL0~WL7, wherein, specifically, connecting the output signal C:0 of the AND gate (the pair of XNOR gates receiving the bit value of bit D0) to the first word line WL0, connecting the output signal C:1 of the AND gate (the pair of XNOR gates receiving the bit value of bit D1) to the second word line WL1,..., and connecting the output signal C:7 of the AND gate (the pair of XNOR gates receiving the bit value of bit D7) to the eighth word line WL7;

[0109] W3) selecting the transistors via the selected word line, and performing the first period write of the write operation:

[0110] At this time, the first word line WL0, the third word line WL2, the fourth word line WL3, and the sixth word line WL5 are selected via the output signals C:0, C:2, C:3, and C:5, and the first transistor Q 10 , the third transistor Q 12 , the fourth transistor Q 13 , and the sixth transistor Q 15and the gate of the second transistor Q1 in the first control transistor is connected to the WPD2 signal, which is set as an opening signal with a specified pulse width (logic value 0 or 1, depending on the type of transistor Q1), and the specified pulse width is the first period, in which the MTJU1 bottom electrode BE1 has the SOT current in the first direction, which is from the MTJ 17 (through the contact area on the bottom electrode BE1) to the MTJ 10 (through the contact area on the bottom electrode BE1) of the highest bit, or from the MTJU1 bottom electrode BE1 to the MTJU1 through the second transistor Q1, the component currents of the SOT current pass through the MTJ 10 , the MTJ 12 , the MTJ 13 , the MTJ 15 , and the directions of the component currents are all from the free layer to the pinned layer (indicated by the dashed arrow in Figure 7 , which is also the direction of the current flowing out of the top electrode), after the first period ends, the states of the MTJ 10 , the MTJ 12 , the MTJ 13 , the MTJ 15 are set to the AP state, thereby completing the recording of the first type of bit value in the bit sequence to be written;

[0111] W4) providing the second VCMA voltage VCMA2 to the MTJU1, i.e. applying a negative external voltage V b , and setting the WPD1 signal to high level. The signal size is configured, and based on the bit sequence to be written and the configured signal, the word line is selected:

[0112] The W1 / 0 signal is set to low level (logic value 0), and the aforementioned D0 to D7 in the bit sequence to be written D[7:0] are simultaneously input to each XNOR gate in the 8 pairs of XNOR gates and AND gates in the CMOS logic unit, and the output signals C:0~C:7 of the 8 AND gates in the CMOS logic unit are connected to the word lines WL0~WL7;

[0113] W5) by selecting the word line, the transistor is turned on, and the second period of the write operation is performed:

[0114] As Figure 8 , the second word line WL1, the fifth word line WL4, the seventh word line WL6, and the eighth word line WL7 are selected by the output signals C:1, C:4, C:6, and C:7 at this time, and the second transistor Q 11 , the fifth transistor Q 14 , the seventh transistor Q 16 , and the eighth transistor Q 17Simultaneously, the gate of the second transistor Q1 in the first control transistor is connected to the WPD2 signal, which is set to an on (voltage) signal with a specified pulse width, which is the second cycle. During the second cycle, there is a SOT current in the second direction at the bottom electrode BE1 of MTJU1. The second direction is formed by the highest bit of MTJ. 10 (Contact area on bottom electrode BE1) to the lowest bit MTJ 17 The SOT current component flows through the MTJ in the direction of the contact area (on the bottom electrode BE1) or in the direction of injection from the second transistor Q1 into the bottom electrode BE1 of MTJU1. 11 MTJ 14 MTJ 16 MTJ 17 Furthermore, the direction of the component currents is from the studded layer to the free layer. Figure 8 The dashed arrow in the middle indicates the direction of the injected top electrode. After the second cycle ends, MTJ 11 MTJ 14 MTJ 16 MTJ 17 The state is set to P state, thus completing the recording of the second type of bit value in the bit sequence to be written, as shown in Table 3 below.

[0115] Table 3. Relationship between MTJ state and logic value in MTJU1 after write operation.

[0116] MTJU1 MTJ 10 ]]> MTJ n ]]> MTJ 12 ]]> MTJ 13 ]]> MTJ 14 ]]> MTJ 15 ]]> MTJ 16 ]]> MTJ 17 ]]> MTJ state AP P AP AP P AP P P Logical value 1 0 1 1 0 1 0 0

[0117] It is to be noted that the current of the foregoing write operation is the SOT current in the write operation and its component current. The foregoing steps W1) to W5) of the write operation performed on the MTJU1 are also applicable to the remaining MTJ units, and one or more MTJ units in the semiconductor device can synchronously or asynchronously perform the steps W1) to W5) of the write operation. The foregoing SOT current in the first direction and the SOT current in the second direction can be generated by driving the second source line SL1. The transistor Q1 is connected with the bottom electrode BE1 and also connected with the source, which can be connected with a current source or a voltage source, and the gate is controlled by the WPD2 signal. The transistors in the first transistor array can be configured in this way, and in some application scenarios, the source of the array device is configured in one or more specified position areas. The first period and the second period can have equal lengths or have independent length configurations. It can be understood that, alternatively, after being configured according to the foregoing first write operation example, in the first period, the W1 / 0 signal can be configured to be low to write “0” in the bit sequence to be written into the MTJ unit, and then in the second period, the W1 / 0 signal can be configured to be high to write “1” in the bit sequence to be written into the MTJ unit. The relationship between the bit sequence to be written, the signal configuration, and the output signal can be seen in Table 4 below.

[0118] Table 4 Relationship table of bit sequence and signal

[0119]

[0120] In this table 4, Dx represents any one bit in the bit sequence to be written, and x takes 0, 1, 2, 3, etc.; C:x represents the output signal of the CMOS logic unit corresponding to Dx, 1 represents an on signal, and 0 represents an off signal.

[0121] On the basis of the foregoing semiconductor device including 8 MTJ units, as an example of a single-bit read operation scenario in this example, the read operation of the foregoing semiconductor device can include:

[0122] R1) Selecting the MTJU1 through the row-column decoder based on the specified row-column address signal. As Figure 9 , the bottom electrode BE1 is connected with the source through the transistor Q1 in the first control transistor array, and the bottom electrode BE1 is also connected with the ground. The second bit line BL1 is connected to the pre-charge sense amplifier (PCSA or SA for short), and the second bit line BL1 is pre-charged to a potential V DD by the PCSA, and then the charging is stopped. It can be understood that a plurality of MTJ units can share the same PCSA, and the PCSA also includes a plurality of transistors, which can constitute a differential circuit connected with the potential VDD In some scenarios of transistor connection configuration, the differential circuit can also be connected with the source line SL1 and also connected with the ground, the differential circuit can convert the current pulse into a voltage pulse, the PCSA can also include a counter connected with the output of the differential circuit for voltage pulse counting, in Figure 9 is not shown.

[0123] R2) providing a smaller, reverse VCMA voltage or no VCMA voltage to the MTJU1, based on the specified row-column address signal, the word line is selected (the open signal is applied) through the row-column decoder and at the same time (the open signal is applied) the transistor in the second control transistor array corresponding to the MTJ in the MTJU1 is selected, the MTJ is the MTJ corresponding to the bit to be read, for example, the MTJ corresponding to the bit to be read is the MTJ 12 , the 3rd word line WL2 is selected and at the same time the corresponding transistor Q 12 , transistor Q1 is selected;

[0124] R3) after transistor Q1 is opened by WPD2 signal and transistor Q 12 is selected by the 3rd word line WL2, the generated current flows through the PCSA to the 2nd bit line BL1, and through transistor Q 12 injects into the MTJ 12 , forms a component current of the injected MTJ 12 , the SOT current of the MTJ 12 flows out of the source through transistor Q1 before the 2nd source line SL1 is grounded. The PCSA determines the state of the MTJ 12 by comparing the value of the component current with the value of the reference current to obtain the read value, and the current direction on the bottom electrode BE1 is the MTJ 12 The direction of the contact area on the bottom electrode BE1 points to the MTJ 10 The direction of the contact area on the bottom electrode BE1. Because the high and low resistance states of the MTJ 12 produce different voltage drops on the 2nd bit line BL1, the current injected into or flowing out of the MTJ 12 is also different, so the PCSA obtains the read value of the current injected into or flowing out of the MTJ 12 based on the value of the reference current. Among them, the final output of the logic value 0 and 1 is determined by the PCSA according to the comparison of the value of the injected or flowing current with a configured reference current value, the reference current value is configured to be the current value between the current value of the AP state and the current value of the P state, and the current value of the AP state and the current value of the P state are relative to the same voltage value. If the read operation is performed after the aforementioned write operation, the MTJ 12The state of the MTJ unit is AP state, i.e. bit C12 stores a logic value 1. In some application scenarios, the MTJ unit or MTJ configured for reference has the characteristic that the current flowing out or injected by the MTJ unit or MTJ has the value of the reference current, so that the reference current is obtained; the VCMA voltage applied in the read operation is optional, i.e. the read operation can be performed without applying the VCMA voltage.

[0125] The semiconductor device of the embodiment of the present application also supports the read operation of multiple (at least two) bit positions. In the MTJ unit, reading multiple bit positions is to simultaneously drive the current to be injected into each MTJ corresponding to the bit positions to be read, and the control duration of the injected current is exponentially increased or decreased by 2 between the bit positions to be read. For example, there are four MTJs in the MTJ unit, the four MTJs store binary data, and the four bit positions store bit values D0, D1, D2 and D3 from the lowest bit position to the highest bit position in sequence. Before reading the binary data, the gate-on time of the transistors corresponding to the lowest bit position to the highest bit position is locked to 1 unit time, 2 unit times, 4 unit times and 8 unit times respectively, and the unit time can be 1 or more clock cycle times, i.e. the four locking values are 1, 2, 4 and 8 respectively. At this time, the control duration of the current injected into the four MTJs, i.e. the gate-on time of the transistors, can be configured according to the pulse width of the opening signal of each transistor. When starting to read the binary data, the bit line connected to the MTJ unit is first pre-charged, and the voltage of the bit line reaches a potential V DD Then, the four transistors are simultaneously and in parallel applied with the opening signals of the four configured pulse widths, and the current is continuously injected into the MTJ storing D0 for 1 unit time to read D0, the current is continuously injected into the MTJ storing D1 for 2 unit times to read D1, the current is continuously injected into the MTJ storing D2 for 4 unit times to read D2, and the current is continuously injected into the MTJ storing D3 for 8 unit times to read D3.

[0126] Since the current passing through the MTJ unit will lower the voltage on the bit line, the binary data is in a proportional relationship with the voltage drop ΔV on the bit line, and the PCSA can be configured according to the proportional relationship, and the PCSA can determine the read binary data (read value) according to the value of the current flowing out of the MTJ unit and the value of the reference current. It should be noted that in principle, the above-mentioned binary data Bin = D3D2D1D0 can continue to be used, and based on the conversion relationship between the binary number and the decimal number (the selection of the locking value is also determined based on the relationship), the decimal number Dec represented by the binary data Bin can be obtained:

[0127] Dec = 8 × D3 + 4 × D2 + 2 × D1 + D0

[0128] The decimal number Dec ranges from 0 to 15. Based on the aforementioned 4-MTJ MTJ cell, the voltage drop AV is:

[0129] AV = 8 x R3I + 4 x R2I + 2 x R1I + R0I = I x (8R3+ 4R2+ 2R1+ R0)

[0130] R3, R2, R1, R0 are the resistances of the MTJs from the highest bit to the lowest bit, and the resistance of the MTJ in the AP state is denoted as R AP , the resistance in the P state is denoted as R P , R AP > R P If the binary data Bin = 1111, the voltage drop at this time is the maximum voltage drop AVmax:

[0131] AVmax = I x (8R AP + 4R AP + 2R AP + R AP ) = 15 x IR AP

[0132] If the binary data Bin = 0000, the voltage drop at this time is the minimum voltage drop AVmin:

[0133] AVmin = I x (8R P + 4R P + 2R P + R P ) = 15 x IR P

[0134] It can also be noted that the difference between the binary number 1111 and the binary number 0000 is the binary number 1111 (decimal number 15), and AVmax - AVmin = 15 x I (R AP - R P ), therefore, each binary number can be distinguished and identified by I (R AP - R P ), where (R AP - R P ) is a fixed value, and it can be seen that only the value of the current (and / or the change in the value of the transistor at the time of turning off) needs to be determined to determine the read value of the multiple bits, and the size of this I can be used as the value of the reference current of the PCSA configuration or as the configuration basis of the value. In the embodiments of the present application, the specific disclosed quantities such as numbers and subscripts described for the purpose of illustration are not the only limited implementation of the present application, and can be changed according to the actual situation of product characteristics and application scenarios, and each disclosed quantity in the embodiments of the present application can be understood in this way.

[0135] On the basis of the aforementioned semiconductor device comprising 8 MTJ of MTJ unit, as one example of the scene of the exemplary multi-bit read operation of this example, the two-bit read operation of the aforementioned semiconductor device is performed, and can also include:

[0136] RT1) Select MTJU1 via row decoder based on the specified row-column address signal. As Figure 10 (2T, T, etc. represent the duration of the transistor current injection controlled by the word line, and the current direction is indicated by the dashed arrow), the bottom electrode BE1 is connected to the source through transistor Q1 in the first array of control transistors, and the bottom electrode BE1 is also connected to the ground. The second bit line BL1 is connected to the PCSA, and the second bit line BL1 is pre-charged to the potential V DD , and then stop charging;

[0137] RT2) Select the 7th word line WL6 and the 8th word line WL7 via row decoder based on the specified row-column address signal, and simultaneously apply an enable signal to the transistors in the second array of control transistors corresponding to the specified bit of MTJ in MTJU1.

[0138] In step RT2), the specified bit is bit C16-C17, and after the write operation, the state of MTJ 16 ~ MTJ 17 is AP state, AP state. Select the 7th word line WL6 and the 8th word line WL7 and simultaneously enable the corresponding transistors Q 16 ~ Q 17 , and transistor Q1, transistor Q 16 ~ Q 17 The enable time of the transistors is the product of the respective lock value and the unit time (T), and the lock value is 2, 1, and the enable time is 2 unit times and 1 unit time, respectively, and transistor Q1 can be closed after 2 unit times. Among them, in the first unit time, two component currents pass through transistors Q 16 ~ Q 17 and continuously inject MTJ 16 ~ MTJ 17 , and the SOT current direction on the bottom electrode BE1 is MTJ 17 The contact area on the bottom electrode BE1 points to MTJ 16 The contact area on the bottom electrode BE1 (or from MTJ 17 The contact area on the bottom electrode BE1 points to the source), and after this first unit time, the current (pulse) corresponding to "1" will be obtained. In the second unit time, one component current still passes through transistor Q 16 and continuously injects MTJ 16 , while transistor Q 17 is closed, and MTJ17 SOT current direction on the bottom electrode BE1 is from MTJ 16 The contact area on the bottom electrode BE1 points to the source, and after this first unit time, a current (pulse) corresponding to "0" will be obtained.

[0139] On the basis of the two-bit read operation, a four-bit read operation of the aforementioned semiconductor device can be performed, see Figure 11 It can also include:

[0140] RF1) Based on the specified row-column address signal, select MTJU1 through the row-column decoder, and pre-charge the second bit line BL1 to the potential V DD Then stop charging.

[0141] RF2) Based on the specified row-column address signal, select the fourth to eighth word lines WL4-WL7 through the row-column decoder, and simultaneously apply an enable signal to the transistors in the second control transistor array corresponding to the MTJs of the specified bit in MTJU1, at this time the transistor gating time is 8T, 4T, 2T, 1T respectively, and the lock value is 8, 4, 2, 1 respectively, and transistor Q1 can be closed after 8T.

[0142] Wherein, in step RT2), the specified bit is bit C14-C17, after the write operation, the state of MTJ 14 -MTJ 17 is P state, AP state, P state, P state.

[0143] In the first unit time, four component currents pass through transistors Q 14 -Q 17 and continuously inject MTJ 14 -MTJ 17 , and the SOT current direction on the bottom electrode BE1 is from MTJ 17 The contact area on the bottom electrode BE1 points to the source, and after this first unit time, a current (pulse) corresponding to "0" will be obtained.

[0144] In the second unit time, three component currents still pass through transistors Q 14 -Q 16 and continuously inject MTJ 14 -MTJ 16 , while transistor Q 17 is closed, and MTJ 17 will not pass through component current, and the SOT current direction on the bottom electrode BE1 is from MTJ16 The contact area on the bottom electrode BE1 points to the source, and after the 2nd unit time, a current (pulse) corresponding to "0" will be obtained.

[0145] In the 4th unit time, the 2-way component current still passes through transistor Q 14 ~ Q 15 continuously injects the MTJ 14 ~ MTJ 15 After the 2nd unit time, transistor Q 16 has been turned off, and the MTJ 16 There will be no component current passing through, and the direction of the SOT current on the bottom electrode BE1 is from the MTJ 15 The contact area on the bottom electrode BE1 points to the source, and after the 4th unit time, a current (pulse) corresponding to "1" will be obtained.

[0146] In the 8th unit time, the 1-way component current still passes through transistor Q 14 continuously injects the MTJ 14 After the 4th unit time, transistor Q 15 has been turned off, and the MTJ 15 There will be no component current passing through, and the direction of the SOT current on the bottom electrode BE1 is from the MTJ 14 The contact area on the bottom electrode BE1 points to the source, and after the 8th unit time, a current (pulse) corresponding to "0" will be obtained.

[0147] In the above 8 unit times, from the start time of the 1st unit time to the end time of the 8th unit time, the PCSA obtains a read value "0100" through the current pulse.

[0148] On the basis of the four-bit read operation, as Figure 12 , the eight-bit read operation of the aforementioned semiconductor device can also be performed, and can also include:

[0149] RE1) In the first 8T, read the low four bits of the semiconductor device according to steps RF1) to RF2);

[0150] RE2) In the second 8T, read the high four bits of the semiconductor device according to steps RF1) to RF2), and obtain a read value "10110100".

[0151] In some application scenarios, the first 8T and the second 8T can have the same starting time, while in other application scenarios, the starting time of the second 8T can be after the ending time of the first 8T. It can be understood that, based on the number of MTJs in the semiconductor device, more bit read operations can also be performed according to the read operation described above. It should be noted that, in the single-bit read operation described above, the read value can be complemented by the processor or can be configured in a multi-bit manner, so that the low bit read value of the read bit is 0. The current of the read operation is the SOT current and its component current in the read operation.

[0152] In the embodiments of the present application, the semiconductor device described above can also perform an operation operation on the operated bit sequence and the operation bit sequence, and the operation operation can be a multiplication operation. When the operation operation is performed, the write operation of the operated bit sequence needs to be performed on the M MTJ units first. In a first application scenario, the operated bit sequence can have been recorded in the specified MTJ unit, and the write operation described above can be performed on the M MTJ units selected in addition to the specified MTJ unit; in a second application scenario, the operated bit sequence can have been recorded in the specified MTJ unit, and the write operation described above needs to be performed on M-1 units in addition to the idle (writable) or adjacent MTJ unit selected together with the specified MTJ unit to form M units; in a third application scenario, the operated bit sequence is not recorded, and the write operation described above is performed on the M idle units. Wherein, M is the number of bits of the operation bit sequence.

[0153] In the embodiments of the present application, the operation operation is based on the selective on / off (whether gated) and gating time locking of the transistors in the control unit to compare the value of the current flowing out of the MTJ unit with the value of the reference current to determine the operation result. Among the M MTJ units described above, the control duration of the injection current of the MTJ in each MTJ unit can be locked to increase or decrease exponentially by 2, that is, the locking value corresponding to the MTJ is configured to increase or decrease exponentially by 2; the control duration of the current flowing out of the M MTJ units can be locked to increase or decrease exponentially by 2, that is, the locking value corresponding to the MTJ unit is configured to increase or decrease exponentially by 2. The increase or decrease of the locking value corresponding to the MTJ can be configured according to the high-low order of the bits of the operated bit sequence stored in each MTJ, and the increase or decrease of the locking value corresponding to the MTJ unit can be configured according to the high-low order of the bits of the operation bit sequence that determines whether the transistors connected to the same word line are gated. It should be noted that the value of the current of the operation operation is smaller than the value of the current of the write operation described above, and the direction of the current of the operation operation can be the same as the direction of the current of the read operation described above.

[0154] The operation result is represented as the sum of the read values of the current flowing out of the M MTJ cells after the control duration of the current flowing out of the M MTJ cells is completely ended; in some other application scenarios, the sum of the read values of the current flowing out of the M MTJ cells and the value of the configured reference current can be compared, and the read value is the operation result. The operation result is composed of the sum of the first type of product values, and the first type of product value is the product value of the cell operation value of each MTJ cell in the M MTJ cells and the corresponding locking value. The cell operation value is composed of the sum of the second type of product values, and the second type of product value is the product value of the read value of the current flowing out of each MTJ in one MTJ cell in the M MTJ cells and the corresponding locking value.

[0155] On the basis of the above-mentioned write operation and read operation, the write operation and operation of the aforementioned bit sequence to be operated can be performed by the transistors in the first control transistor array and the transistors in the second control transistor array of the aforementioned control unit.

[0156] The specified transistor in the first control transistor array is used to selectively control the current flowing out of the bottom electrode of the M MTJ cells in the operation, and the on-off time of the specified transistor is locked to increase or decrease exponentially by 2. The specified transistor in the second control transistor array is used to selectively control the current flowing out of the top electrode of the specified MTJ in the M MTJ cells in the operation, and the on-off time of the specified transistor is locked to increase or decrease exponentially by 2. There are P groups of transistors in the specified transistor in the second control transistor array, and whether each group of transistors is on or off is controlled by the bit sequence to be operated, and P is the number of bits in the bit sequence to be operated. The same group of transistors is specifically used to selectively control the current flowing out of the top electrode of the MTJ in the M MTJ cells recording the same bit value in the operation, and the same bit value is the bit value on the same bit position in the bit sequence to be operated.

[0157] On the basis of the above, as an example of the operation operation disclosed by the present application, the operation operation of the semiconductor device can include:

[0158] A1) performing a write operation of a bit sequence to be operated on M MTJ cells, wherein the bit positions are aligned in each MTJ cell, and M is the number of bits in the bit sequence to be operated;

[0159] A2) locking the gating time of the transistors in the first control transistor array (the designated, i.e. currently used, transistors) corresponding to the M MTJ units, the gating times being exponentially increased or decreased by 2;

[0160] A3) locking the gating time of the transistors in the second control transistor array corresponding to the MTJ in each MTJ unit, the gating times being exponentially increased or decreased by 2, there being P groups of transistors in the second control transistor array, each group being controlled by the operation bit sequence to be transmitted on the word line, and the same group of transistors being used to control the injection of the current for the operation into the top electrode of the MTJ in the M MTJ units having the same bit value recorded therein, which is the bit value on the same bit position in the operation bit sequence (also because the bit positions have been aligned);

[0161] A4) simultaneously turning on the transistors in the first control transistor array and the transistors in the second control transistor array, and after the longest gating time ends, obtaining the readout value of the current flowing out of the M MTJ units through the PCSA, which is the operation result.

[0162] The gating times locked in the above steps A2) and A4) are the control durations of the injected or flowing current, and the locking manner conforms to the relationship between the locking values.

[0163] As an example of the operation operation of a 2x2 bit scale disclosed in the present application, as Figure 13 , the operation bit sequence is 01, the operation bit sequence bit 10 (at this time M is taken as 2), the operation bit sequence is recorded in the 2 MTJ units, for example, MTJU0, MTJU1, the MTJ 02 , MTJ 03 corresponding to the bit positions from high to low are C02, C03, and the bit values corresponding to the states of the MTJs are 0, 1, respectively, and the MTJ 12 , MTJ 13 corresponding to the bit positions from high to low are C12, C13, and the bit values corresponding to the states of the MTJs are 0, 1, respectively. The gating times of the transistors in the first control transistor array and the second control transistor array are in units of a clock period T. The gating times of the transistors Q0, Q1 in the first control transistor array can be locked as 2T1, T1 by configuring the WPD2 signals corresponding to the source lines SL0, SL1; the gating times of the transistors Q 02 , Q 12 corresponding to the word line WL2 are locked as 2T2, and the gating times of the transistors Q 03 , Q 13The gate time of the selected transistor is locked as T2 (P takes 2 at this time). Since the operation bit sequence is 10, the group of transistors Q 03 , Q 13 corresponding to the word line WL3 will be selected as the gate on and the gate off respectively. 02 , Q 12 corresponding to the word line WL2 will be selected as the gate on and the gate off respectively. The bit lines BL0~BL1 are pre-charged to the potential V DD .

[0164] At the beginning of the transistor gate (control), the transistors Q0, Q1 and the transistors Q 02 , Q 03 are simultaneously turned on, and the reading operation of each MTJ unit is started. After the first T1, the read value 01 is obtained by reading the current flowing out of the MTJU1, and the read value 00 is obtained by reading the current flowing out of the MTJU0, and 01 is superimposed on 00 to be 01, and the transistor Q1 is turned off at the end of the first T1; after the second T1, the read value 01 is obtained by reading the current flowing out of the MTJU1, and the read value 01 obtained after the first T is superimposed on the 01 after the second T to be 10, and the transistor Q0 is turned off at the end of the second T1, and the control is ended, and the final read value is 10, and the 10=01x10 at the same time, and therefore, the multiplication operation of the magnetic storage semiconductor device is realized. The superposition is realized by the continuous increment / decrement counting of the counter in the aforementioned PCSA within 2T time, and the result can be the operation result determined based on the read values of the current flowing out of the M MTJ units.

[0165] As an example of the 4x3-bit scale operation operation disclosed by the present application, as Figure 14 , the operation bit sequence is 1011 (decimal number 11), the operation bit sequence is 110 (decimal number 6), and M takes 3 at this time, and the operation bit sequence is written into 3 MTJ units, such as MTJU0, MTJU1, and MTJU2, and each MTJ unit can have or use 4 MTJs respectively, and the MTJs 00 , MTJ 01 , MTJ 02 , and MTJ 03 corresponding to the bit positions from high to low are C00, C01, C02, and C03 respectively, and the bit values corresponding to the states of the MTJs are 1, 0, 1, and 1 respectively. In this way, the writing operation of the operation bit sequence in the 3 MTJ units is completed, and the logical value record table 5 of the MTJ state corresponding to the operation bit sequence in each MTJ unit is obtained.

[0166] Table 5: Logical value record table of 3 MTJ units corresponding to the written operation bit sequence

[0167] Bit C00 C01 C02 C03 MTJU0 MTJ 00 ]]> MTJ 01 ]]> MTJ 02 ]] MTJ 03 ]]> Logical value 1 0 1 1 Bit C10 C11 C12 C13 MTJU1 MTJ 10 ]]> MTJ 11 ]]> MTJ 12 ]]> MTJ 13 ]]> Logical value 1 0 1 1 Bit C20 C21 C22 C23 MTJU2 MTJ 20 ]] MTJ 21 ]]> MTJ 22 ]] MTJ 23 ]] Logical value 1 0 1 1

[0168] In Table 5, the operation bit sequence can be considered as forming bit alignment in each MTJ cell. At this time, 3 transistors in the first control transistor array are used, and the transistors Q0, Q1, Q2 are used to control the current flowing out of the bottom electrodes BE0, BE1, BE2 of the MTJU0, MTJU1, MTJU2, respectively, and the bottom electrodes BE0, BE1, BE2 of the MTJU0, MTJU1, MTJU2 are connected to the source through the transistors Q0, Q1, Q2, and the readout value of the current of each MTJ cell is obtained through the SA. The on time of the transistors Q0, Q1, Q2 is locked as 4T1, 2T1, T1, respectively. The bit lines BL0~BL2 are precharged to the potential V DD .

[0169] In the second control transistor array, 12 transistors are used at this time, and the transistors Q 00 , Q 11 , Q 12 , Q 13 are used to control the current injection of the top electrodes of the MTJ 00 , MTJ 01 , MTJ 02 , MTJ 03 , respectively, and the on time of the transistors Q 00 , Q 11 , Q 12 , Q 13 is locked as 8T2, 4T2, 2T2, T2, respectively, and the transistors Q 00 , Q 11 , Q 12 , Q 13 are also controlled by the word lines WL0, WL1, WL2, WL3, respectively, and can be divided into 4 groups of transistors (P is taken as 4 at this time), and after the operation bit sequence is copied 4 times, the gate of the transistor corresponding to the specified bit position (in the second control transistor array) is transmitted through the word lines WL0, WL1, WL2, WL3, in this way, the configuration of the second control transistor array corresponding to the remaining MTJ cells is completed. Among them, the first group of transistors connected with the word line WL0 are the transistors Q 00 , Q 10 , Q 20 , which are selected as on, on, off; the second group of transistors connected with the word line WL1 are the transistors Q 01 , Q 11 , Q 21 , which are selected as on, on, off; the third group of transistors connected with the word line WL2 are the transistors Q 02 , Q 12 , Q 22Q0, Q1, Q2 are selected as on, on, on; the fourth group of transistors connected with the word line WL3 are transistors Q 03 , Q 13 , Q 23 are selected as on, on, off; the relationship between the operation bit sequence and whether the transistors in the second control transistor array are selected as on or off is shown in Table 6.

[0170] Table 6 Table of relationship between operation bit sequence and transistor selection in the second control transistor array

[0171]

[0172] At the beginning of the transistor selection, transistors Q0, Q1, Q2 are simultaneously turned on, and transistors Q 00 ~Q 03 , and transistors Q 10 ~Q 13 are turned on, and the reading operation on each MTJ unit is started. After the first T1, the readout value 0000 is obtained by reading the current flowing out of MTJU2, the readout value 1011 is obtained by reading the current flowing out of MTJU1, and the readout value 1011 is obtained by reading the current flowing out of MTJU0, and the sum is 10110, and transistor Q2 is turned off. After the second T1, the readout value 1011 is obtained by reading the current flowing out of MTJU1, and the readout value 1011 is obtained by reading the current flowing out of MTJU0, and the sum is 10110, and the 10110 obtained after the first T1 is added to the 10110 obtained after the second T1 to obtain 101100, and transistor Q1 is turned off. After the third T1, the readout value 1011 is obtained by reading the current flowing out of MTJU0, and the 101100 obtained after the second T1 is added to the 1011 obtained after the third T1 to obtain 110111. After the fourth T1, the readout value 1011 is obtained by reading the current flowing out of MTJU0, and the 110111 obtained after the third T1 is added to the 1011 obtained after the third T1 to obtain the final result 1000010, i.e., the decimal number 66, as shown in Table 7.

[0173] Table 7 Record table of selection time, readout value and result of the first control transistor array

[0174]

[0175] It should be noted that the current of the operation operation includes the current of the read operation of each MTJ unit selected in the operation operation, and can also include the outflow current of the MTJ unit not selected, the size of the outflow current can be 0 or a specified value, and the direction of the outflow current with the specified value can be consistent with the direction of the current of the read operation. The number of elements such as PCSA or counter and the configuration of the specific line connection can be adjusted according to the product characteristics, and the specific superposition time and superposition mode can also be adjusted, for example, the read values of each MTJ unit can be superimposed all at once after 4 T1, or the outflow current of each MTJ unit can be regarded as a current pulse wave lasting for 4 T1 within 4 T1, and the read value of the current pulse wave is obtained. The unit time T1 is greater than or equal to 2 (P-1) T2, the unit time T2 can be one clock period time, that is, T2 can be equal to the aforementioned 1 unit time T in the read operation, P is the number of bits of the operation bit sequence, for example, in the example of the operation operation of 4*3 bits, T1 is greater than or equal to 8T2. It can be noted that in the operation operation, the configuration of the second control transistor array transistor selection time in the read operation of each MTJ unit is consistent with the corresponding configuration in the independent read operation of the MTJ unit, and whether to select depends on the operation bit sequence. The operation operation, the write operation and the read operation can configure an enable signal corresponding to each operation to select the operation required to be performed by the MTJ unit.

[0176] In the aforementioned semiconductor device of the embodiment of the application, the control unit first performs the write operation on the operation bit sequence according to the number of bits of the operation bit sequence, locks the selection time or control duration of the transistor of the outflow current of the MTJ unit and the transistor of the injection current of the MTJ in each MTJ unit, then performs the read operation on the MTJ unit after the write operation, and reads the value, which is the operation result of the operation operation, so that the multiplication operation is completed in the aforementioned semiconductor device. It should be noted that the multiplication operation is realized by the above-mentioned write operation, read operation and selection time configuration of the transistor (embodied by the current of the operation operation), without the need to additionally introduce a device for multiplication logical operation in the aforementioned semiconductor device, and without the need to adjust the layout and / or size of the transistor in the control unit due to the realization of the multiplication operation, that is, the realization of the multiplication operation of the embodiment of the application does not additionally occupy the chip area, and does not use the transistor of the logical element outside the semiconductor device of the embodiment of the application to realize the operation, thereby breaking through the power consumption and chip area bottleneck of the semiconductor device under the same data storage capacity.

[0177] Embodiment 2

[0178] The embodiment of the application belongs to the same inventive concept as embodiment 1, and the embodiment of the application provides a semiconductor device, which can include the control unit and the MTJ unit in embodiment 1.

[0179] The control unit can include at least three transistors, each of which is formed on a substrate;

[0180] The MTJ unit can include at least two MTJs, each of which has a nanopillar structure and is grown in a region of at least two transistors of the at least three transistors, that is, any MTJ can be grown in a region of one transistor and does not occupy an additional unused region;

[0181] The at least two MTJs have a same bottom electrode, and each MTJ has an independent top electrode;

[0182] The top electrodes of the at least two MTJs are connected to the at least two transistors (one-to-one correspondence), and the bottom electrodes of the at least two MTJs are connected to one transistor of the at least three transistors (except the at least two transistors).

[0183] In the embodiment of the application, the nanopillar structure can be grown in the substrate region occupied by the transistor of the control unit by epitaxial growth technology, and the transistor can be the transistor in the second control transistor array in Embodiment 1. The nanopillar structure of the MTJ does not consume additional substrate area and does not separately occupy the area of the manufactured chip. At the same time, the embodiment of the application realizes the structure of "(q+1)T(q)MTJ", q is a positive integer, for example, the 8 MTJs in the embodiment of the application only need 9 control transistors to realize the read operation, the write operation and the operation operation, and only 2 unit times are needed to complete the write operation, while the existing storage device needs 16 control transistors for 8 storage units (such as transistors in SRAM) to realize the read and write operation, and needs 9 unit times to complete the write operation. The number of transistors has a great influence on the chip area, and the embodiment of the application improves the size of the chip area required to realize the same storage capacity, and improves the integration scale of the storage unit in the same chip area.

[0184] Embodiment 3

[0185] Embodiments 1 and 2 belong to the same inventive concept, and the embodiment of the application provides an operation method of a semiconductor device, wherein the semiconductor device can be the semiconductor device in Embodiment 1, the semiconductor device can include N MTJ units and a control unit, any MTJ unit includes at least two MTJs, and N is a positive integer; the control unit is used to perform a write operation and a read operation on the N MTJ units; the operation method is performed by the control unit, and the operation method can include:

[0186] AE1) selectively control the current of the write operation, write the operation bit sequence to the MTJ in the M MTJ units, M is the number of bits of the operation bit sequence;

[0187] AE2) based on the operation bit sequence, selectively control the current of the operation operation, inject the MTJ in the M MTJ units, and control the current flowing out of the M MTJ units, and the control duration of the injected or flowing current is the product value of the locking value and the specified unit time;

[0188] The control unit is configured to determine the operation result based on the read value of the current flowing out of the M MTJ units.

[0189] In the embodiment of the application, step AE1) can perform write operation on each MTJ unit in the manner of "double cycle 1 / 0" write operation in embodiment 1. Step AE2) can control the current and obtain the read value in the manner of operation operation in embodiment 1.

[0190] Specifically, the operation method can include: performing write operation and read operation of the semiconductor device.

[0191] Specifically, the control unit includes a CMOS logic unit; performing write operation of the semiconductor device can include:

[0192] In the first cycle, the top electrode of the MTJ corresponding to the selected bit to be written in the specified MTJ unit is applied with a first VCMA voltage, and the first type of bit value in the bit sequence to be written is written into the specified MTJ unit by the CMOS logic unit and the configured SOT current.

[0193] In the second cycle, the top electrode of the MTJ corresponding to the selected bit to be written in the specified MTJ unit is applied with a second VCMA voltage, and the second type of bit value in the bit sequence to be written is written into the specified MTJ unit by the CMOS logic unit and the configured SOT current.

[0194] Specifically, performing read operation of the semiconductor device can include:

[0195] The top electrode of the MTJ corresponding to the bit to be read is applied with a VCMA voltage, the configured SOT current is injected into the MTJ, and the read value of the current flowing out of the MTJ unit where the MTJ is located is determined.

[0196] Specifically, performing read operation of the semiconductor device can further include:

[0197] applying a VCMA voltage to a top electrode of an MTJ corresponding to at least two bits to be read in a designated MTJ cell, controlling SOT current injection into the MTJ, and determining a readout value of current flowing out of the designated MTJ cell,

[0198] The control duration of the injected current exponentially increases or decreases by 2 between the at least two bits.

[0199] Embodiment 4

[0200] Embodiments of the present application and embodiments 1 to 3 belong to the same inventive concept, and the embodiments of the present application provide a memory and computing chip, or a spin memory and computing integrated chip, which can include the semiconductor device described in embodiments 1 and 2. In some application scenarios, the aforementioned control unit can only include the first control transistor array, the second control transistor array and the CMOS logic unit, and the memory and computing chip can further include peripheral circuits (which can be used to generate enable signals, clock signals and pulse width controlled current / voltage signals, etc.) responsive to instructions of the read-write controller, row-column decoders, pre-charge amplifiers, word lines, bit lines, source lines, bus interfaces and other elements of memory chips. The memory and computing chip can have chip particles, and each chip particle can have a specified storage capacity.

[0201] Embodiments of the present application also provide integrated circuit products. In a first example, referring to Figure 15 , the integrated circuit product can include a plurality of the aforementioned memory and computing chips 403, and the integrated circuit product can further include a chip bus 402 and a read-write controller chip 401, and the read-write controller chip 401 is connected to the memory and computing chips 403 through the chip bus 402. The read-write controller chip 401 and any memory and computing chip are different chip particles with independent packaging, and the chip bus 402 is implemented on a circuit board 400, and the circuit board 400 is provided with bus interfaces of the read-write controller chip 401 and the memory and computing chips 403. The circuit board 400 can also be provided with other interfaces, which can be used for power supply and for connection or communication with devices using the integrated circuit product, such as servers, industrial computers, embedded devices, detection terminal devices, metering terminal devices, etc.

[0202] In a second example, referring to Figure 16The integrated circuit product can include at least one processor 411 and the semiconductor device 412 described in Embodiments 1 and 2, the semiconductor device 412 being connected to the at least one processor 411 through an in-chip bus 414, and the at least one processor 411 and the semiconductor device 412 can be disposed in the same chip package 410. The integrated circuit product can be a System on Chip (SoC) or a Micro-Controller Unit (MCU), and the integrated circuit product can further include a commonly integrated memory 413, the memory 413 being connected to the at least one processor 411 through the bus 414, and the commonly integrated memory 413 can include a Read-Only Memory (ROM), a Static Random Access Memory (SRAM), a Flash memory, etc. Figure 15 and Figure 16 The actual chip or product size and layout, etc. can be adjusted according to the product characteristics of the demand for the purpose of showing the exemplary product module.

[0203] The integrated circuit product of the embodiment of the present application uses the aforementioned semiconductor device, effectively solves the problem of memory wall and power wall in the transmission and processing of massive data, and improves the stability, reliability and processing efficiency of the data storage and processing system.

[0204] The above describes the optional implementation manners of the embodiment of the present application in detail in combination with the drawings, but the embodiment of the present application is not limited to the specific details in the above implementation manners, and various simple modifications can be made to the technical solutions of the embodiment of the present application within the technical concept range of the embodiment of the present application, and these simple modifications all belong to the protection range of the embodiment of the present application.

[0205] In addition, it should be noted that each specific technical feature described in the above specific implementation manners can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present application does not further describe various possible combinations.

[0206] Those skilled in the art can understand that all or part of the steps of the methods in the above embodiments can be completed by a program instructing relevant hardware, the program is stored in a storage medium, and the storage medium includes a plurality of instructions for enabling a single-chip microcomputer, a chip or a processor to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium can be non-transient, and the storage medium can include a read-only memory, a flash memory and various program code storage media. The foregoing CMOS is the abbreviation of Complementary Metal Oxide Semiconductor, that is, complementary metal oxide semiconductor.

[0207] In addition, various different embodiments of the embodiments of the present application can also be combined arbitrarily, as long as they do not deviate from the idea of the embodiments of the present application, and they should also be considered as disclosed in the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: N MTJ units and a control unit, where N is a positive integer; Any MTJ unit includes at least two MTJs, all MTJs in any MTJ unit share the same bottom electrode, and each MTJ has an independent top electrode; The control unit is used to perform write and read operations on the N MTJ units; The control unit is used to selectively control the current of the write operation, and write the bit sequence to be operated into the MTJ of M MTJ units, where M is the number of bits in the bit sequence to be operated; The control unit is used to selectively control the current of the operation based on the operation bit sequence, inject the current into the top electrode of the MTJ in the M MTJ units, and control the current flowing out of the bottom electrode of the M MTJ units. The control duration of the injected or outflowing current is the product of the lock value corresponding to the injected or outflowing current MTJ and a specified unit time, wherein the lock value is a power of 2. The control unit is used to determine the calculation result based on the read values ​​of the outflow current of the M MTJ units.

2. The semiconductor device according to claim 1, characterized in that, In the M MTJ units, the control duration of the injection current of the MTJ in each MTJ unit is locked to increase or decrease exponentially by 2. The control duration of the outflow current of the M MTJ units is locked between periods that increase or decrease exponentially by 2.

3. The semiconductor device according to claim 2, characterized in that, The calculation result is represented as the sum of the readout current values ​​of the M MTJ units after the control duration of the current flowing out of the M MTJ units has completely ended.

4. The semiconductor device according to claim 2 or 3, characterized in that, The calculation result is composed of the sum of the first type of product values, which are the product of the unit operation value of each MTJ unit and its corresponding locking value in the M MTJ units. The unit operation value is composed of the sum of the second type of product value, which is the product of the read value of the outflow current of each MTJ in one of the M MTJ units and its corresponding lock value.

5. The semiconductor device according to claim 2, characterized in that, The control unit includes a first control transistor array and a second control transistor array; The transistors specified in the first control transistor array are used to selectively control the current flowing out of the bottom electrode of the M MTJ cells, wherein the turn-on time of the specified transistors is locked to increase or decrease in an exponential multiple of 2. The transistors specified in the second control transistor array are used to selectively control the current injected into the top electrode of the specified MTJ in the M MTJ units for the operation, wherein the turn-on time of the specified transistor is locked to increase or decrease in an exponential multiple of 2.

6. The semiconductor device according to claim 5, characterized in that, The second control transistor array has P groups of transistors, and whether each group of transistors is selected is controlled by the operation bit sequence, where P is the number of bits in the operation bit sequence. Specifically, the same group of transistors is used to selectively control the injection of the current of the operation into the top electrode of the MTJ in the M MTJ cells that have the same bit value recorded, where the same bit value is the bit value at the same bit position in the bit sequence being operated on.

7. The semiconductor device according to claim 5, characterized in that, Of the M MTJ units, the first j The turn-on time of the current flowing out of each MTJ unit is 2. j-1 T1, j Take the number of bits from 1 to the number of bits in the operation bit sequence, where T1 is the specified unit time; With the first j The lock value corresponding to each MTJ unit is 2. j-1 .

8. The semiconductor device according to claim 7, characterized in that, In any one of the M MTJ units, inject with the first i The turn-on time of the MTJ current corresponding to each bit is 2. i-1 T2, i Take the number of bits from 1 to the number of bits in the bit sequence being operated on, where T2 is the specified unit time. The lock value corresponding to this MTJ is 2. i-1 .

9. The semiconductor device according to claim 5, characterized in that, The first control transistor array r A transistor, connected to the bottom electrode of any of the MTJ units and also connected to the first transistor. p A source line connection is used to selectively control the current flowing out of any of the MTJ units. r , p It is a positive integer.

10. The semiconductor device according to claim 9, characterized in that, The second control transistor array c The transistor is connected to the top electrode of the corresponding MTJ in any MTJ unit, and is also connected to the first transistor. n bar lines and the first m The bar-shaped connection is used to selectively control the current injected into the corresponding MTJ. c , n, m It is a positive integer.

11. The semiconductor device according to claim 1, characterized in that, This semiconductor device is a spin magnetic storage unit; The current value of the arithmetic operation is less than the current value of the write operation, and the direction of the current of the arithmetic operation is the same as the direction of the current of the read operation.

12. The semiconductor device according to claim 2, characterized in that, The control unit includes a CMOS logic unit; The control unit is used to apply a first VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the designated MTJ cell during the first cycle of the write operation, and to write the first type of bit value in the bit sequence to be written into the designated MTJ cell bit by bit through the CMOS logic cell and the configured SOT current. The control unit is used to apply a second VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the designated MTJ cell during the second cycle of the write operation, and to write the second type bit value in the bit sequence to be written into the designated MTJ cell bit by bit through the CMOS logic cell and the configured SOT current.

13. The semiconductor device according to claim 12, characterized in that, The CMOS logic unit includes an XOR gate and an AND gate.

14. The semiconductor device according to claim 2, characterized in that, The control unit is used to apply a VCMA voltage to the top electrode of the MTJ corresponding to the bit to be read during the read operation, control the injection of the configured SOT current into the MTJ, and determine the read value of the current flowing out of the MTJ cell.

15. The semiconductor device according to claim 2, characterized in that, The control unit is used, during the read operation, to apply a VCMA voltage to the top electrode of the MTJ corresponding to at least two bits to be read in the specified MTJ cell, control the injection of the configured SOT current into the MTJ, and determine the readout value of the current flowing out of the specified MTJ cell. The duration of the injected current control increases or decreases exponentially by a factor of 2 between the at least two bits.

16. A semiconductor device, characterized in that, The semiconductor device includes: The control unit includes at least three transistors, all of which are formed on a substrate; The MTJ unit includes at least two MTJs, each of which has a nanopillar structure, and the nanopillar structures are respectively grown in the regions of at least two of the at least three transistors; The at least two MTJs have the same bottom electrode, and each MTJ has an independent top electrode; The top electrodes of the at least two MTJs are respectively connected to the at least two transistors, and the bottom electrodes of the at least two MTJs are connected to one of the at least three transistors; The control unit is used to perform write and read operations on the MTJ unit, including: The current of the write operation is selectively controlled to write the bit sequence to be processed into the MTJ in the MTJ cell; Based on the operational bit sequence, the current of the operational operation is selectively controlled, the current injected into the top electrode of the MTJ is controlled, and the current flowing out of the bottom electrode of the MTJ is controlled. The control duration of the injected or flowing out current is the product of the lock value corresponding to the injected or flowing out current of the MTJ and a specified unit time, wherein the lock value is a power of 2. The calculation result is determined based on the reading of the outflow current of MTJ.

17. A method of operating a semiconductor device, characterized in that, The semiconductor device includes N MTJ units and a control unit. Each MTJ unit includes at least two MTJs, where N is a positive integer. All MTJs in any MTJ unit share the same bottom electrode, and each MTJ has an independent top electrode. The control unit is used to perform write and read operations on the N MTJ units. This operation method is executed by the control unit and includes: The current of the write operation is selectively controlled to write the bit sequence to be operated on into the MTJ of M MTJ units, where M is the number of bits in the bit sequence to be operated on. Based on the operational bit sequence, the current of the operational operation is selectively controlled, injected into the top electrode of the MTJ in the M MTJ units, and the current flowing out of the bottom electrode of the M MTJ units is controlled. The control duration of the injected or outflowing current is the product of the lock value corresponding to the injected or outflowing MTJ and a specified unit time, where the lock value is a power of 2. The calculation result is determined based on the readout values ​​of the outflow current of the M MTJ units.

18. A memory computing chip, characterized in that, The memory chip includes the semiconductor device as described in any one of claims 1 to 16.

19. An integrated circuit product, the integrated circuit product comprising: At least one processor and a semiconductor device as described in any one of claims 1 to 16, wherein the semiconductor device is connected to the at least one processor; or, The integrated circuit product includes: the memory chip as described in claim 18.

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