Embedded component substrate and method for manufacturing the same

Abstract

The application discloses an embedded component substrate and a manufacturing method thereof. The manufacturing method of the embedded component substrate drills a composite inner layer circuit structure to form a chip accommodating groove, and makes the component contact end of the circuit layer protrude from the side wall in the groove. Then, the chip component is placed in the groove and the surface contact is connected with the component contact end. Alternatively, two composite inner layer circuit structures are provided, the component contact end of the circuit layer protrudes from the side of the first composite inner layer circuit structure, the surface contact of the chip component is connected with the component contact end, and then the second composite inner layer circuit structure is bonded with another surface of the chip component. The manufacturing method makes the chip component directly penetrate at least two circuit layers, and the surface contact is connected with at least one component contact end. The occupied area of the chip component in a single circuit layer is reduced, the setting space of the circuit and the settable number of the chip component are increased.

Description

TECHNICAL FIELD

[0001] A substrate and a method for manufacturing the same, in particular, an embedded component substrate and a method for manufacturing the same. BACKGROUND

[0002] Referring to FIG. 8 As shown, the setting direction of the chip component 90 of the existing embedded component substrate 80 is parallel to the substrate 80 and the line structure 81 therein, that is, the top surface 91 and the bottom surface 92 of the chip component 90 are respectively oriented in the same direction as the upper surface 82 and the lower surface 83 of the line substrate 80, and are embedded in one line layer structure 81. Compared with the conventional line substrate with the chip component arranged on the surface, the embedded component substrate 80 with the chip component embedded in the inner line structure has the advantages of saving the surface area of the substrate, flexible line arrangement, and stable connection between the chip component and the line.

[0003] The setting mode of the embedded chip component 90 makes the chip component 90 occupy a large area of the line layer structure 80, and the complete area for setting the chip component must be reserved in the line layer structure 80 for setting the chip component 90, which limits the design flexibility of the line arrangement. In addition, since the surface contact 93 of the chip component 90 is located on the top surface 91 or the bottom surface 92 of the chip (for example, the surface contact 93 is on the top surface 91 as shown), the surface contact 93 must be electrically connected to the line layer 812 in another line layer structure 81 through the conductive blind hole 813 of the line layer structure 81. FIG. 8 As shown, if two embedded chip components 90 and 90A need to be connected, the surface contact 93 of the chip component 90 and the surface contact 93A of the other chip component 90A must be electrically connected through the path of the conductive blind hole 813A-line layer 812B-conductive blind hole 813B. In this way, the conduction path between the two chip components 90 and 90A is long, which easily leads to more noise and consumes more connection line arrangement space, reducing the line design space flexibility of the line substrate with embedded chip components. SUMMARY

[0004] In view of the prior art, the chip element is horizontally embedded in one line structure, which occupies the line arrangement area of the line structure, reduces the line design flexibility, and causes long connection path between elements, resulting in more energy loss and signal-to-noise. The present application provides an embedded element substrate and a manufacturing method thereof. The embedded element substrate includes a composite inner layer line structure, which includes a plurality of line layers and at least one element contact end in the plurality of line layers; a chip element embedded in the composite inner layer line structure and penetrating at least two line layers in the plurality of line layers, the chip element having a top surface and a bottom surface opposite to the top surface, the chip element having at least one surface contact on the bottom surface; and the chip element being directly connected to the at least one element contact end in the plurality of line layers through the at least one surface contact.

[0005] In an embodiment, the composite inner layer line structure has a chip accommodating groove penetrating at least two line layers in the plurality of line layers, the chip accommodating groove having a setting side wall, the at least one element contact end protruding from the setting side wall of the chip accommodating groove; the chip element is arranged in the chip accommodating groove, the bottom surface of the chip element facing the setting side wall in the chip accommodating groove, and the surface contact being directly connected to the element contact end of the at least two line layers.

[0006] In an embodiment, the embedded element substrate further includes an additional layer line structure arranged in a stack with the composite inner layer line structure and enclosing a groove opening of the chip accommodating groove.

[0007] In an embodiment, the chip accommodating groove has a bottom wall and a ring wall, wherein the setting side wall is a part of the ring wall; the embedded element substrate further includes a metal shielding layer covering the bottom wall of the chip accommodating groove and the part of the ring wall outside the setting side wall, and the metal shielding layer being connected to the additional layer line structure and electrically connected to a ground terminal through the additional layer line structure.

[0008] The embedded element substrate of the present application embeds a chip element penetrating at least two line layers in a composite inner layer line structure, and directly connects the element contact end of the line layer to the surface contact of the bottom surface of the chip element. That is, the chip element is not horizontally embedded in the dielectric layer of a single line structure, but is directly connected to the line layer to be embedded in the composite inner layer line structure.

[0009] The method for manufacturing an embedded component substrate of the present application comprises the following steps: providing a composite inner layer circuit structure, the composite inner layer circuit structure comprising a plurality of circuit layers; performing a drilling procedure on the composite inner layer circuit structure to form a chip accommodating slot, the chip accommodating slot penetrating at least two circuit layers of the plurality of circuit layers, and the chip accommodating slot having a set sidewall; performing a residue removing procedure on the chip accommodating slot, so that at least one component contact end of the plurality of circuit layers protrudes from the set sidewall; disposing a chip component in the chip accommodating slot, so that the chip component is embedded in the composite inner layer circuit structure and penetrates at least two circuit layers of the plurality of circuit layers, and a surface contact of the chip component is aligned with the at least one component contact end; and directly connecting the surface contact of the chip component and the component contact end of the circuit layer.

[0010] In an embodiment, the method further comprises: performing a circuit layer adding procedure to dispose an added layer circuit structure on the composite inner layer circuit structure, the added layer circuit structure enclosing a slot opening of the chip accommodating slot.

[0011] In an embodiment, after the chip accommodating slot is formed, the method further comprises the following steps: performing an electroplating procedure on the chip accommodating slot to form a metal shielding layer on a bottom wall and a ring wall of the chip accommodating slot; performing a grinding procedure on part of the ring wall to remove the metal shielding layer covering the part of the ring wall, and to expose part of the ring wall and the component contact end of the circuit layer; wherein the exposed part of the ring wall is the set sidewall; and performing a residue removing procedure on the set sidewall, so that at least one component contact end of the plurality of circuit layers protrudes from the set sidewall.

[0012] In an embodiment, the circuit layer adding procedure comprises the following steps: disposing an added layer dielectric layer on the composite inner layer circuit structure, the added layer dielectric layer enclosing a slot opening of the chip accommodating slot; performing a drilling procedure on the added layer dielectric layer to form a groove, the groove communicating with an upper edge of the metal shielding layer; and disposing an added layer circuit layer on the added layer dielectric layer and in the groove, the added layer circuit layer comprising a shielding layer cover portion, the shielding layer cover portion being a planar circuit, a vertical projection of the shielding layer cover portion on the composite inner layer circuit structure covering the slot opening of the chip accommodating slot, and the shielding layer cover portion engaging with the upper edge of the metal shielding layer in the groove; wherein the metal shielding layer is electrically connected to a ground end through the added layer circuit layer.

[0013] In an embodiment, in the step of directly connecting the surface contact of the chip component and the component contact end of the circuit layer, the surface contact of the chip component and the component contact end of the circuit layer are joined by temperature rising diffusion welding or ultrasonic welding.

[0014] Another method of manufacturing an embedded component substrate of the present application includes the following steps: providing a first composite inner-layer structure, the first composite inner-layer structure including a plurality of first circuit layers, and having a first side surface, at least one component contact end of the plurality of first circuit layers protruding from the first side surface; providing a chip component, the chip component having a top surface and a bottom surface opposite the top surface, the chip component having at least one surface contact on the bottom surface; facing the bottom surface of the chip component toward the first side surface of the first composite inner-layer structure, and directly connecting the at least one surface contact with at least one component contact end of the first composite inner-layer structure; providing a second composite inner-layer structure, the second composite inner-layer structure having a second side surface, and bonding the second side surface of the second composite inner-layer structure with the second surface of the chip component; and performing a circuit build-up process to dispose two build-up circuit structures outside the first composite inner-layer structure and the second composite inner-layer structure, so as to fix the first composite inner-layer structure, the chip component, and the second composite inner-layer structure between the two build-up circuit structures.

[0015] In one embodiment, the first composite inner-layer structure has a first upper surface and a first lower surface opposite the first upper surface; the second composite inner-layer structure has a second upper surface and a second lower surface opposite the second upper surface; the first upper surface and the second upper surface are parallel and face in the same direction, and the first lower surface and the second lower surface are parallel and face in the same direction; when performing the circuit build-up process, the following sub-steps are further included: covering a first build-up dielectric layer on the first upper surface of the first composite inner-layer structure and the second upper surface of the second composite inner-layer structure, and covering a second build-up dielectric layer outside the first lower surface of the first composite inner-layer structure and the second lower surface of the second composite inner-layer structure; disposing a first build-up circuit layer on the first build-up dielectric layer, and disposing a second build-up circuit layer on the second build-up dielectric layer.

[0016] The embedded component substrate of the present application has a chip accommodating groove penetrating through at least two circuit layers in the composite inner-layer structure, and the component contact end of the circuit layer protrudes from the setting side wall of the chip accommodating groove. When the chip component is disposed in the chip accommodating groove, the bottom surface faces the setting side wall, so that the surface contact of the chip component directly engages with the component contact end of the circuit layer. That is, the chip component is not horizontally embedded in the dielectric layer of a single circuit structure, but vertically intersects with the dielectric layer and the circuit layer, and is embedded in the multi-layer circuit structure. The surface contact on the bottom surface of the chip component directly engages with at least one component contact end of the circuit layer protruding from the chip accommodating groove.

[0017] Thus, the required setting space of the chip element occupies less planar area of any circuit layer, so that each circuit layer has more area for setting circuit, and relatively, the circuit setting area affected by a single chip element is small, so that more chip elements can be effectively placed in the circuit substrate of the same size, and the setting density of the chip elements in the embedded element substrate is improved. Meanwhile, when multiple chip elements that need to be connected with each other are set, the chip elements do not need to be connected with the circuit layer through the conductive blind hole, but are directly connected with the circuit in the circuit layer, and the two chip elements can also be directly connected through the circuit layer without the need of connection through the conductive blind hole-circuit-conductive blind hole, so that the connection path between the two chip elements is short, and the signal loss and signal noise are reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a side view cross-sectional schematic diagram of an embedded element substrate of the present application;

[0019] FIGS. 2A-2H is a manufacturing flow cross-sectional schematic diagram of a manufacturing method of an embedded element substrate of the first embodiment of the present application;

[0020] FIGS. 3A-3L is a manufacturing flow cross-sectional schematic diagram of a manufacturing method of an embedded element substrate of the second embodiment of the present application;

[0021] FIG. 4 is a partial top view schematic diagram of one step of the manufacturing method of the embedded element substrate of the second embodiment of the present application;

[0022] FIGS. 5A-5F is a manufacturing flow cross-sectional schematic diagram of a manufacturing method of an embedded element substrate of the third embodiment of the present application;

[0023] FIG. 6 is another side view cross-sectional schematic diagram of an embedded element substrate of the present application;

[0024] FIG. 7 is another side view cross-sectional schematic diagram of an embedded element substrate of the present application;

[0025] FIG. 8 is a side view cross-sectional schematic diagram of an existing embedded element substrate. DETAILED DESCRIPTION

[0026] Please refer to FIG. 1As shown, the embedded component substrate of the present invention includes a composite inner layer circuit structure 10 and a chip element 20. The composite inner layer circuit structure 10 includes a plurality of circuit layers 11, wherein the plurality of circuit layers 11 have at least one component contact terminal 111. The chip element 20 is embedded in the composite inner layer circuit structure 10 and penetrates at least two of the plurality of circuit layers 11. The chip element 20 has a top surface 22 and a bottom surface 21, and at least one surface contact 23 located on the bottom surface 21. The at least one surface contact 23 of the chip element 20 is directly bonded to the at least one component contact terminal 111.

[0027] The embedded component substrate of the present invention can be manufactured by at least the following two embedded component substrate manufacturing methods.

[0028] Please see FIGS. 2A-2E As shown, in the first embodiment of the embedded component substrate fabrication method of the present invention, the fabrication method includes the following steps:

[0029] like FIG. 2A As shown, a composite inner layer circuit structure 10 is provided, which includes a plurality of circuit layers 11; the plurality of circuit layers 11 have at least one component contact terminal 111.

[0030] like FIG. 2B As shown, a drilling process is performed on the composite inner layer circuit structure 10 to form a chip receiving groove 100. The chip receiving groove 100 penetrates at least two of the plurality of circuit layers 11, and the chip receiving groove 100 has a sidewall 101.

[0031] like FIG. 2C As shown, a desmearing process is performed on the chip receiving groove 100 so that the at least one component contact end 111 protrudes from the setting side wall 101;

[0032] like FIG. 2D As shown, a chip element 20 is disposed in the chip receiving groove 100, such that the chip element 20 is embedded in the composite inner layer circuit structure 10 and penetrates at least two of the multiple circuit layers 11, and at least one surface contact 23 of the chip element 20 is aligned with the at least one element contact end 111.

[0033] like FIG. 2E As shown, the surface contact 23 of the chip element 20 is directly connected to the element contact terminal 111 of the circuit layer 11.

[0034] In this embodiment, a composite inner layer circuit structure 10 having a plurality of circuit layers 11 is prepared first, and a drilling process is performed on the surface of the composite inner layer circuit to form a chip accommodating groove 100 for embedding a chip component 20, and the component contact end 111 of the plurality of circuit layers 11 is exposed in the chip accommodating groove 100. It should be noted that the component contact end 111 of the at least two circuit layers 11 and the space of the chip accommodating groove 100 are provided with pre-reserved and arranged through the circuit layers 11, so that the component contact end 111 is located at the edge of the reserved space of the chip accommodating groove 100. In this way, when the drilling process is performed on the composite inner layer circuit structure 10, the component contact end 111 of the circuit layer 11 will be extremely close to or just exposed on the set side wall 101 of the chip accommodating groove 100, and FIG. 2B is taken as an example that the component contact end 111 is just exposed on the chip accommodating groove 100; after the drilling is completed, desmear is performed in the chip accommodating groove 100 to remove the dielectric residue remaining in the chip accommodating groove 100, and this process will also erode the inner wall of the chip accommodating groove 100, so that the component contact end 111 extremely close to or exposed on the surface of the set side wall 101 protrudes from the set side wall 101 for the surface contact 23 of the chip component 20 to connect. Preferably, the surface contact 23 of the chip component 20 and the component contact end 111 of the circuit layer 11 are directly joined by thermal diffusion welding or ultrasonic welding.

[0035] In this embodiment, the composite inner layer circuit structure 10 has the chip accommodating groove 100, the chip accommodating groove 100 penetrates the at least two circuit layers 11 and has a set side wall 101. The component contact end 111 of the plurality of circuit layers 11 protrudes from the set side wall 101 of the chip accommodating groove 100. The chip component 20 is arranged in the chip accommodating groove 100, penetrates the at least two circuit layers 11, and the chip component 20 faces the set side wall 101 in the chip accommodating groove 100 with the bottom surface 21, and the surface contact 23 is directly connected with the component contact end 111 of the circuit layer 11.

[0036] Please refer to FIGS. 2F-2H In the first embodiment, after the surface contact 23 of the chip component 20 is directly connected with the component contact end 111 of the circuit layer 11, the following steps are further included:

[0037] A circuit build-up process is performed to arrange a build-up circuit structure 30 on the composite inner layer circuit structure 10, the build-up circuit structure 30 closes a groove opening 102 of the chip accommodating groove 100, and the embedded component substrate is completed.

[0038] The build-up line structure 30 comprises at least one build-up dielectric layer 31 and at least one build-up line layer 32. In the embodiment, a single build-up dielectric layer 31 and a single build-up line layer 32 are used, but the present application is not limited thereto. The procedure for forming the build-up line structure 30 comprises the following steps:

[0039] As shown in FIG. 2F , a build-up dielectric layer 31 is laminated on the composite inner layer line structure 10. The build-up dielectric layer 31 seals the slot opening 102 of the chip accommodating slot 100. The slot opening 102 is an opening formed on the surface of the composite inner layer line structure 10 during the drilling procedure for forming the chip accommodating slot 100. Preferably, when the build-up dielectric layer 31 is laminated, the dielectric material of the build-up dielectric layer 31 is extruded into the chip accommodating slot 100 and fills the chip accommodating slot 100.

[0040] As shown in FIG. 2G , a build-up line layer 32 is formed on the build-up dielectric layer 31.

[0041] As shown in FIG. 2H , a solder resist layer 40 is formed on the build-up line layer 32. The solder resist layer 40 has at least one solder resist opening to expose part of the build-up line layer 32.

[0042] When the build-up dielectric layer 31 is laminated on the composite inner layer line structure 10, the dielectric material of the build-up dielectric layer 31 is extruded into the chip accommodating slot 100 through the slot opening 102 on the surface of the composite inner layer line structure 10, so that the dielectric material of the build-up dielectric layer 31 fills the chip accommodating slot 100. In other embodiments, a glue filling procedure can be performed in the chip accommodating slot 100 before the build-up dielectric layer 31 is laminated, so as to prefill the chip accommodating slot 100 with dielectric material.

[0043] After the build-up dielectric layer 31 is laminated, a build-up line layer 32 and a solder resist layer 40 are further formed on the build-up dielectric layer 31. The formation of the build-up line layer 32 and the solder resist layer 40 can further comprise the common procedures such as drilling, exposure and development, electroplating, etching, lamination of the solder resist layer 40, etc., which are not described herein.

[0044] Please refer to FIGS. 3A-3EAs shown in a second embodiment, preferably, the chip accommodating groove 100 further has a metal shielding layer 12. In more detail, the chip accommodating groove 100 has a bottom wall 103 and a ring wall 104, the setting side wall 101 is a part of the ring wall 104, and the metal shielding layer 12 covers the ring wall 104 except the part of the bottom wall 103 and the setting side wall 101 of the chip accommodating groove 100. The manufacturing method of the embedded component substrate with the metal shielding layer 12 comprises the following steps:

[0045] As shown in FIG. 3A , a composite inner layer circuit structure 10 is provided, which comprises a plurality of circuit layers 11;

[0046] As shown in FIG. 3B , a drilling procedure is performed on the composite inner layer circuit structure 10 to form a chip accommodating groove 100, which penetrates at least two circuit layers 11 of the plurality of circuit layers 11; the chip accommodating groove 100 has the bottom wall 103 and the ring wall 104, and part of the ring wall 104 is the setting side wall 101;

[0047] As shown in FIG. 3C , after the chip accommodating groove 100 is formed, a plating procedure is further performed on the chip accommodating groove 100 to form the metal shielding layer 12 on the bottom wall 103 and the ring wall 104 of the chip accommodating groove 100;

[0048] Then, as shown in FIG. 3D , a grinding procedure is performed on the part of the ring wall 104 of the chip accommodating groove 100, which is the setting side wall 101, to remove the metal shielding layer 12 covering the part of the ring wall 104 and expose part of the ring wall 104 and the component contact end 111 of the circuit layer 11; wherein the exposed part of the ring wall 104 is the setting side wall 101;

[0049] As shown in FIG. 3E , a desmear procedure is performed on the setting side wall 101 so that at least one component contact end 111 of the circuit layer 11 protrudes from the setting side wall 101.

[0050] In this way, the metal shielding layer 12 in the chip accommodating groove 100 is completed. Please refer to FIG. 3F and FIG. 3G , after the metal shielding layer 12 is completed, the steps of setting the chip component 20 in the chip accommodating groove 100 are performed, which are similar to the steps of setting and connecting the chip component 20 in the first embodiment, and are not described here.

[0051] Please refer to FIGS. 3H-3JAs shown, in this embodiment, after the chip element 20 is set, similarly, the add-on circuit structure 30 will be further added to the composite inner layer circuit structure 10. It should be noted that in this embodiment, the add-on circuit structure 30 further includes a shielding layer cover 321. The metal shielding layer 12 covers the surface of the chip receiving groove 100 except for the sidewall 101. The shielding layer cover 321 is a planar circuit, corresponding to the groove opening 102 of the chip receiving groove 100, to cover the top of the chip element 20. The steps for adding the add-on circuit structure 30 are as follows:

[0052] like FIG. 3H As shown, an additional dielectric layer 31 is first covered on the composite inner layer circuit structure 10, and the additional dielectric layer 31 closes the slot opening 102 of the chip receiving slot 100.

[0053] like FIG. 3I As shown, a drilling process is performed on the added dielectric layer 31 to form a trench 310, which connects to an upper edge of the metal shielding layer 12.

[0054] like FIG. 3J As shown, an augmented circuit layer 32 is provided on the augmented dielectric layer 31 and in the trench 310. The augmented circuit layer 32 includes a shielding layer cover portion 321, which is a planar circuit. A vertical projection on the composite inner layer circuit structure 10 covers the slot opening 102 of the chip receiving slot 100 and is joined to the upper edge of the metal shielding layer 12 in the trench 310.

[0055] Please see FIG. 3K and FIG. 3L As shown, the augmented circuit structure 30 may also include multiple augmented dielectric layers 31 and multiple augmented circuit layers 32. A ground terminal 33 may be provided in the outermost augmented circuit layer 32, and the metal shielding layer 12 and the shielding layer cover 321 are electrically connected to the ground terminal 33. Finally, a solder resist layer 40 is provided on the outermost augmented circuit layer 32 to complete the embedded component substrate. When the combination of the metal shielding layer 12 and the shielding layer cover 321 is connected to the ground terminal 33, it forms a metal shielding cover with electromagnetic shielding function for the chip component 20 disposed in the chip receiving groove 100.

[0056] For a better option, please refer to FIG. 4 As shown, FIG. 4This is a plan view from above the added dielectric layer 31 after drilling to form the trench 310. Since the metal shielding layer 12 is disposed along the annular wall 104 within the chip receiving groove 100, only not covering the side wall 101, one upper edge of the metal shielding layer 12 is U-shaped. The shape and position of the trench 310 correspond to the upper edge of the metal shielding layer 12, such that the bottom of the trench 310 connects to the entire upper edge of the metal shielding layer 12. In this way, the shielding layer cover 321 can completely engage with the upper edge of the metal shielding layer 12 within the trench 310, forming a complete metal shielding cover enclosing the chip element 20 embedded in the composite inner layer circuit structure 10, and providing good shielding when connected to the ground terminal 33.

[0057] Please see FIGS. 5A-5C As shown, in a third embodiment of the present invention, another method for manufacturing the embedded component substrate is provided. The steps of this manufacturing method are as follows.

[0058] like FIG. 5A As shown, a first composite inner layer circuit structure 10A is provided, which includes a plurality of first circuit layers 11A and has a first side surface 105A. At least two component contact ends 111A of at least two of the plurality of first circuit layers 11A protrude from the first side surface 105A. A chip element 20 is also provided, which has a bottom surface 21 and a top surface 22 opposite to the bottom surface 21. The chip element 20 has at least one surface contact 23 on the bottom surface 21.

[0059] like FIG. 5B As shown, the bottom surface 21 of the chip element 20 faces the first side surface 105A of the first composite inner layer circuit structure 10A, and the at least two surface contacts 23 are directly connected to the at least two component contact ends 111A of the first composite inner layer circuit structure 10A; preferably, the surface contacts 23 of the chip element 20 and the component contact ends 111A of the first circuit layer 11A are joined by thermal diffusion soldering or ultrasonic soldering.

[0060] like FIG. 5C As shown, a second composite inner layer circuit structure 10B is provided, which includes a plurality of second circuit layers 11B. The second composite inner layer circuit structure 10B has a second side surface 105B, and the second side surface 105B of the second composite inner layer circuit structure 10B is bonded to the top surface 22 of the chip element 20. Preferably, the second side surface 105B of the second composite inner layer circuit structure 10B and the top surface 22 of the chip element 20 are bonded together with an adhesive layer 13.

[0061] Please see FIGS. 5D-5FAs shown, further performing a first build-up process to form a first build-up structure 30A on the first inner layer structure 10A and a second build-up structure 30B on the second inner layer structure 10B, so as to fix the first inner layer structure 10A, the chip element 20 and the second inner layer structure 10B between the first build-up structure 30A and the second build-up structure 30B.

[0062] wherein the first inner layer structure 10A has a first upper surface 106A and a first lower surface 107A opposite to the first upper surface 106A; the second inner layer structure 10B has a second upper surface 106B and a second lower surface 107B opposite to the second upper surface 106B; the first upper surface 106A and the second upper surface 106B are parallel and face the same direction, and the first lower surface 107A and the second lower surface 107B are parallel and face the same direction. Further, the above-mentioned build-up process comprises the following steps:

[0063] As shown in FIG. 5D a first build-up dielectric layer 31A is formed on the first upper surface 107A of the first inner layer structure 10A and the second upper surface 107B of the second inner layer structure 10B, and a second build-up dielectric layer 31B is formed on the first lower surface 108A of the first inner layer structure 10A and the second lower surface 108B of the second inner layer structure 10B.

[0064] As shown in FIG. 5E a first build-up circuit layer 32A is formed on the first build-up dielectric layer 31A, and a second build-up circuit layer 32B is formed on the second build-up dielectric layer 31B.

[0065] Preferably, as shown in FIG. 5F after the first build-up circuit layer 32A and the second build-up circuit layer 32B are formed, a first anti-welding layer 40A and a second anti-welding layer 40B are formed on the first build-up circuit layer 32A and the second build-up circuit layer 32B, so as to complete the embedded element substrate.

[0066] In the third embodiment, a method for forming the embedded component substrate of the present application by combining two sets of composite inner layer circuit structures with a chip component is provided. In the first inner layer composite circuit structure 10A, the first circuit layer 11A has component contact ends 111A protruding from the first side surface 105A for the chip component 200 to connect with the surface contact 23 of the bottom surface 21. After the chip component 20 is connected with the first composite inner layer circuit structure 10A, the second composite inner layer circuit structure 10B is then adhered to the top surface 22 of the chip component 20 away from the first composite inner layer circuit structure 10A to form a combined composite inner layer circuit structure with the chip component 20 sandwiched therebetween. Then, the build-up circuit structure 30A and the build-up circuit structure 30B are respectively formed on the upper surface and the lower surface of the combined composite inner layer circuit structure by a build-up circuit structure process. The build-up circuit structures 30A and 30B make the combination of the first and second composite inner layer circuit structures 10A and 10B and the chip component 20 stable. The first and second composite inner layer circuit structures 10A and 10B can also be electrically connected through the first build-up circuit layer 31A and the second build-up circuit layer 31B in the build-up circuit structures 30A and 30B.

[0067] Referring to FIG. 6 As shown in the figure, the embedded component substrate of the present application makes the chip component 20 occupy less horizontal area of the circuit layer 11, and the surface contact of the chip component 20 is directly connected with the component contact end 111 in the circuit layer 11, so the chip component 20 does not need to be connected with the circuit layer 11 through the conductive blind via perpendicular to the circuit direction of the circuit layer 11. In addition, as shown in the figure, FIG. 7 When two or more chip components 20 are provided, both of the chip components 20 can be directly connected through the component contact ends 111 at both ends of a circuit layer 11, without the need to pass through the conductive blind via, the circuit layer and the conductive blind via as in the prior art to achieve the connection, thus shortening the connection path between the two chip components 20.

[0068] The above description is only an embodiment of the present application and does not limit the present application in any form. Although the present application has been disclosed as above, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the technical solution of the present application to obtain equivalent embodiments with equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application shall still fall within the scope of the technical solution of the present application.

Claims

1. A substrate for embedded components, characterized in that, Include: A composite inner layer circuit structure comprising multiple circuit layers, wherein each of the multiple circuit layers has at least one component contact terminal; A chip element is embedded within the composite inner layer circuit structure and penetrates at least two of the plurality of circuit layers. The chip element has a top surface and a bottom surface opposite the top surface. The chip element has at least one surface contact on the bottom surface. The chip element is directly connected to at least one component contact terminal in the plurality of circuit layers via the at least one surface contact. The composite inner layer circuit structure has a chip receiving slot that penetrates at least two of the plurality of circuit layers. The chip receiving slot has a sidewall, and at least one component contact end protrudes from the sidewall of the chip receiving slot. The chip element is disposed in the chip receiving slot, the bottom surface of the chip element faces the side wall of the chip receiving slot, and the surface contact is directly connected to the component contact end of the at least two circuit layers.

2. The embedded component substrate according to claim 1, characterized in that, Include: An add-in circuit structure is superimposed on the composite inner layer circuit structure and closes one opening of the chip accommodating slot.

3. The embedded component substrate according to claim 2, characterized in that, The chip accommodating groove has a bottom wall and an annular wall, wherein the sidewall is a portion of the annular wall; the embedded component substrate further comprises: A metal shielding layer covers the bottom wall of the chip receiving slot and part of the annular wall outside the side wall of the mounting slot. The metal shielding layer is connected to the augmentation circuit structure and is electrically connected to a ground terminal through the augmentation circuit structure.

4. A method for fabricating an embedded component substrate, characterized in that, Includes the following steps: A composite inner layer circuit structure is provided, the composite inner layer circuit structure comprising multiple circuit layers; A drilling process is performed on the composite inner layer circuit structure to form a chip receiving slot, the chip receiving slot penetrating at least two of the plurality of circuit layers, and the chip receiving has a sidewall. A desmearing process is performed on the chip receiving slot so that at least one component contact end of the plurality of circuit layers protrudes from the sidewall of the mounting. A chip element having a top surface and a bottom surface opposite the top surface is disposed in the chip receiving groove, such that the chip element is embedded in the composite inner layer circuit structure and penetrates at least two of the plurality of circuit layers, and a surface contact of the chip element on the bottom surface is aligned with the at least one element contact end. The surface contacts of the chip element are directly connected to the component contact terminals of the circuit layer.

5. The method for fabricating an embedded component substrate according to claim 4, characterized in that, Include: A circuit layer addition process is performed to set an addition circuit structure on the composite inner layer circuit structure, the addition circuit structure closing a slot opening of the chip accommodating slot.

6. The method for fabricating an embedded component substrate according to claim 5, characterized in that, After the chip receiving slot is formed, the following steps are also included: An electroplating process is performed on the chip receiving tank to form a metal shielding layer on a bottom wall and a ring wall of the chip receiving tank; A grinding process is performed on a portion of the annular wall to remove the metal shielding layer covering the portion of the annular wall and expose the portion of the annular wall, as well as the component contact terminals of the circuit layer; wherein, the exposed portion of the annular wall is the sidewall on which the circuit is installed. A descaling process is performed on the sidewall of the mounting structure, causing at least one component contact end of the circuit layer to protrude from the sidewall of the mounting structure.

7. The method for fabricating an embedded component substrate according to claim 6, characterized in that, The line layer addition procedure includes the following steps: An additional dielectric layer is covered on the composite inner layer circuit structure, and the additional dielectric layer closes one slot opening of the chip accommodating slot. A drilling process is performed on the added dielectric layer to form a trench that connects to an upper edge of the metal shielding layer; An augmentation circuit layer is disposed on the augmentation dielectric layer and in the trench. The augmentation circuit layer includes a shielding layer cover portion, which is a planar circuit. A vertical projection of the shielding layer cover portion onto the composite inner layer circuit structure covers the slot opening of the chip receiving slot and is joined to the upper edge of the metal shielding layer in the trench. The metal shielding layer is electrically connected to a ground terminal through the augmentation circuit layer.

8. The method for fabricating an embedded component substrate according to claim 5, characterized in that, In the step of directly connecting the surface contacts of the chip element to the component contacts of the circuit layer, the surface contacts of the chip element and the component contacts of the circuit layer are joined by a heat diffusion soldering or ultrasonic soldering process.

9. A method for manufacturing an embedded component substrate, characterized in that, Includes the following steps: A first composite inner layer circuit structure is provided, the first composite inner layer circuit structure includes a plurality of first circuit layers and has a first side surface, wherein at least one component contact end of the plurality of first circuit layers protrudes from the first side surface. A chip element is provided, the chip element having a top surface and a bottom surface opposite the top surface, the chip element having at least one surface contact on the bottom surface; The bottom surface of the chip element faces the first side surface of the first composite inner layer circuit structure, and the at least one surface contact is directly connected to the at least one component contact end of the first composite inner layer circuit structure. A second composite inner layer circuit structure is provided, the second composite inner layer circuit structure having a second side surface, and the second side surface of the second composite inner layer circuit structure is bonded to the second surface of the chip element; A circuit layer addition process is performed, in which two additional circuit structures are set outside the first composite inner layer circuit structure and the second composite inner layer circuit structure, so that the first composite inner layer circuit structure, the chip element and the second composite inner layer circuit structure are fixed between the two additional circuit structures.

10. The method for fabricating an embedded component substrate according to claim 9, characterized in that, The first composite inner layer circuit structure has a first upper surface and a first lower surface opposite to the first upper surface; the second composite inner layer circuit structure has a second upper surface and a second lower surface opposite to the second upper surface; the first upper surface and the second upper surface are parallel and face the same direction, and the first lower surface and the second lower surface are parallel and face the same direction; The line layer addition procedure includes the following steps: A first additive dielectric layer is covered on the first upper surface of the first composite inner layer circuit structure and the second upper surface of the second composite inner layer circuit structure, and a second additive dielectric layer is covered on the outside of the first lower surface of the first composite inner layer circuit structure and the second lower surface of the second composite inner layer circuit structure. A first layer of circuitry is provided on the first layer of dielectric layer, and a second layer of circuitry is provided on the second layer of dielectric layer.

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