Three-dimensional memory device

Abstract

The application provides a three-dimensional memory device, comprising: a substrate; a stack structure formed on the substrate, the stack structure having a core array region and a step region arranged along a first direction; a first wall structure arranged in the step region along the first direction; and a second wall structure arranged in the step region along a second direction different from the first direction and intersecting the first wall structure. According to the three-dimensional memory device of the application, the support in the step region can be increased, the stress deformation of the step region can be reduced, and the yield and reliability of the three-dimensional memory device can be improved.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202110243809.7, filed on March 5, 2021, entitled "Three-dimensional storage device". Technical Field

[0002] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory device having reduced stress deformation in the step region. Background Technology

[0003] The increase in storage density of memory devices is closely related to advancements in semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes shrinks, the storage density of memory devices increases. To further improve storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. 3D memory devices consist of multiple memory cells stacked along a vertical direction, which can significantly increase integration density on a unit area of ​​wafer and reduce costs.

[0004] To achieve higher storage density, the number of layers stacked in 3D memory devices has increased significantly, for example, from 32 layers to 64 layers, then to 96 layers and even 128 layers. However, as the number of layers in 3D memory devices increases, the problem of stress in the step region becomes more and more serious, which can lead to deformation of the gate lines and deformation of the step region.

[0005] Therefore, it is desirable to further improve the structure of three-dimensional storage devices in order to improve their yield and reliability.

[0006] It should be understood that this background section is intended to provide some useful context for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were not part of what a person skilled in the art knew or understood prior to the relevant valid application date of the subject matter disclosed herein. Summary of the Invention

[0007] This application provides a three-dimensional storage device that can at least partially solve the aforementioned problems existing in the prior art.

[0008] Embodiments of this application aim to provide a three-dimensional storage device, which may include: a substrate; a stacked structure formed on the substrate, the stacked structure having a core array region and a step region disposed along a first direction; a first wall structure disposed in the step region along the first direction; and a second wall structure disposed in the step region along a second direction different from the first direction and intersecting with the first wall structure.

[0009] In an exemplary embodiment, the first direction may be perpendicular to the second direction.

[0010] In an exemplary embodiment, the three-dimensional memory device may further include a plurality of gate line gap structures that extend through the stacked structure along a direction perpendicular to the substrate.

[0011] In an exemplary embodiment, the plurality of gate line gap structures may include a plurality of first gate line gap structures, a plurality of second gate line gap structures, and a plurality of third gate line gap structures arranged alternately along a second direction, wherein the first gate line gap structures and the third gate line gap structures may extend through the core array region and the step region along a first direction, and the second gate line gap structures may extend within the core array region along the first direction.

[0012] In an exemplary embodiment, there may be at least one second gate gap structure and at least one third gate gap structure between two adjacent first gate gap structures; and there may be at least one third gate gap structure between two adjacent second gate gap structures.

[0013] In an exemplary embodiment, the third gate gap structure may extend through the first wall structure to electrically connect the core array region and the step region.

[0014] In an exemplary embodiment, the core array region may include a first core array region and a second core array region, and the step region may be located between the first core array region and the second core array region.

[0015] In an exemplary embodiment, the three-dimensional storage device may further include a polysilicon layer formed between the substrate and the stacked structure.

[0016] In an exemplary embodiment, the three-dimensional storage device may further include a plurality of channel structures and a plurality of virtual channel structures, wherein each channel structure may include: a channel hole penetrating the stacked structure along a direction perpendicular to the substrate, and a multilayer functional layer structure stacked sequentially from the outside to the inside along the sidewall of the channel hole, wherein each virtual channel structure may include: a virtual channel hole penetrating the stacked structure along a direction perpendicular to the substrate, and an oxide layer formed along the sidewall of the virtual channel hole.

[0017] In an exemplary embodiment, a channel structure may be provided in the core array region, and a virtual channel structure may be provided in the step region and / or the core array region.

[0018] In an exemplary embodiment, a channel structure may be provided in the core array region, and a channel structure may be provided in the first wall structure.

[0019] In an exemplary embodiment, a virtual channel structure may be provided in the remaining portion of the stepped area, excluding the first wall structure.

[0020] In an exemplary embodiment, a channel structure may be provided in the core array region, and a channel structure may be provided in the second wall structure.

[0021] In an exemplary embodiment, a virtual channel structure may be provided in the remaining portion of the stepped area, excluding the second wall structure.

[0022] In an exemplary embodiment, a channel structure may be provided in the core array region, and a channel structure may be provided in the first wall structure and the second wall structure.

[0023] In an exemplary embodiment, a virtual channel structure may be provided in the remaining portion of the stepped area, excluding the first wall structure and the second wall structure.

[0024] Embodiments of this application also aim to provide a three-dimensional storage device, which may include: a substrate; a stacked structure formed on the substrate, the stacked structure may have a core array region and a step region disposed along a first direction, and the stacked structure may be provided with a plurality of channel structures and a plurality of virtual channel structures penetrating the stacked structure along a direction perpendicular to the substrate; and a first wall structure disposed in the step region along the first direction, the first wall structure may be provided with channel structures.

[0025] In an exemplary embodiment, the three-dimensional memory device may further include a plurality of gate line gap structures that can penetrate the stacked structure along a direction perpendicular to the substrate.

[0026] In an exemplary embodiment, the plurality of gate line gap structures may include a plurality of first gate line gap structures, a plurality of second gate line gap structures, and a plurality of third gate line gap structures arranged alternately along a second direction perpendicular to the first direction, wherein the first gate line gap structures and the third gate line gap structures may extend along the first direction through the core array region and the step region, and the second gate line gap structures may extend along the first direction within the core array region.

[0027] In an exemplary embodiment, there may be at least one second gate gap structure and at least one third gate gap structure between two adjacent first gate gap structures; and there may be at least one third gate gap structure between two adjacent second gate gap structures.

[0028] In an exemplary embodiment, the third gate gap structure may extend through the first wall structure to electrically connect the core array region and the step region.

[0029] In an exemplary embodiment, the core array region may include a first core array region and a second core array region, and the step region may be located between the first core array region and the second core array region.

[0030] In an exemplary embodiment, each channel structure may include: a channel hole penetrating the stacked structure along a direction perpendicular to the substrate, and an oxide-nitride-oxide-polysilicon-oxide structure stacked sequentially from the outside to the inside along the sidewall of the channel hole; and each virtual channel structure may include: a virtual channel hole penetrating the stacked structure along a direction perpendicular to the substrate, and an oxide layer formed along the sidewall of the virtual channel hole.

[0031] In an exemplary embodiment, the three-dimensional storage device may further include a polysilicon layer formed between the substrate and the stacked structure.

[0032] In an exemplary embodiment, a channel structure may be provided in the core array region, and a virtual channel structure may be provided in the portion of the step region other than the first wall structure.

[0033] In an exemplary embodiment, the three-dimensional storage device may further include a second wall structure, which may be disposed in the stepped area along a second direction and intersect with the first wall structure.

[0034] In an exemplary embodiment, a channel structure may be provided in the core array region, and a virtual channel structure may be provided in the remaining part of the stepped region except for the first wall structure.

[0035] In an exemplary embodiment, a channel structure may be provided in the core array region, and a channel structure may be provided in the second wall structure.

[0036] Compared with the prior art, the beneficial effects of this application are mainly reflected in:

[0037] 1) The first wall in the stepped area is equipped with a channel structure, which can effectively strengthen the support of the first wall and reduce stress deformation;

[0038] 2) The stepped area has a second wall structure located in the Y direction, which can effectively strengthen the support in the Y direction, reduce stress deformation, and does not add any additional processing steps; and

[0039] 3) The first wall in the stepped area is provided with a channel structure, and the stepped area also has a second wall structure located in the Y direction, which can effectively strengthen the support of the first wall structure and the support in the Y direction, reduce stress deformation, and not add any additional process. Attached Figure Description

[0040] The above and other advantages and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings.

[0041] Figure 1 This is a cross-sectional schematic diagram showing a portion of a three-dimensional storage structure according to an embodiment of this application;

[0042] Figure 2 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to an embodiment of this application;

[0043] Figure 3 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to another embodiment of this application;

[0044] Figure 4 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to yet another embodiment of this application;

[0045] Figure 5 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to yet another embodiment of this application; and

[0046] Figure 6 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to yet another embodiment of this application. Specific Implementation

[0047] Exemplary embodiments of the invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are illustrated. However, the invention may be embodied in various forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0048] It should also be understood that when a component or layer is referred to as being "on" another component or layer, "connected to," or "attached to" another component or layer, it may be directly on or directly connected to the other component or layer, or there may be a component or layer between them. However, when a component or layer is referred to as being "directly on" another component or layer, "directly connected to," or "directly attached to" another component or layer, there is no intermediate component or layer. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without an intermediary element.

[0049] Throughout the specification, the same reference numerals denote the same components. In the accompanying drawings, the thickness of layers and regions is exaggerated for clarity.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the term "comprising" specifies the presence of the described features, areas, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Therefore, depending on the specific orientation of the figure, the exemplary term “down” may encompass both “down” and “up” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Therefore, the exemplary term “below” or “under” may encompass both “up” and “down” orientations.

[0052] As used herein, “about” or “approximately” includes the value as well as the average of the values ​​within an acceptable range of deviations from the particular value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the relevant field and in the context of this invention, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0054] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0055] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Further, a layer may be a region of a uniform or non-uniform continuous structure, wherein the non-uniform continuous structure has a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers. For example, an interconnect layer may comprise one or more conductor and contact layers (forming interconnect lines and / or via contacts in the contact layers) and one or more dielectric layers.

[0056] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND memory strings) on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0057] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0058] This application may be presented in various forms, some of which will be described below.

[0059] Example 1

[0060] Figure 1 This is a cross-sectional schematic diagram showing a portion of a three-dimensional storage device according to an embodiment of this application. Figure 2 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to an embodiment of this application. Figure 1 and Figure 2 The diagram shown is a partial view of the three-dimensional storage device and does not represent the complete structure of the three-dimensional storage device.

[0061] like Figure 1 and Figure 2As shown, the three-dimensional storage device 100 according to this embodiment may include a substrate 10, a stacked structure 20, a first wall structure 30, and a second wall structure 40. The stacked structure 20 may be formed on the substrate 10. The stacked structure 20 may have a core array region C and a step region SS disposed along the X direction. The first wall structure 30 may be disposed along the X direction in the step region SS. The second wall structure 40 may be disposed along a Y direction different from the X direction in the step region SS, and may intersect the first wall structure 30. The X direction may, for example, be perpendicular to the Y direction.

[0062] In this embodiment, the substrate 10 may be a semiconductor substrate. The substrate 10 may be, for example, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 10 may also be, for example, a P-type doped substrate or an N-type doped substrate, but is not limited thereto. Those skilled in the art can select a suitable material as the substrate 10 according to actual needs. For example, in other embodiments, the material of the substrate 10 may also be a semiconductor or compound including other elements. For example, the substrate 10 may be a gallium arsenide substrate, an indium phosphide substrate, or a silicon carbide substrate. Further, the substrate 10 may include, for example, a high-voltage P-type well region (HVPW), a high-voltage N-type well region (HVNW), and a deep N-well (DNW). In addition, other additional layers may exist between the substrate 10 and the stacked structure 20. For the sake of simplicity, Figure 1 The aforementioned well region and additional layer are not shown in the diagram.

[0063] In this embodiment, the stacked structure 20 includes an insulating layer 23 and a gate layer 24 that are continuously and alternately disposed along a direction perpendicular to the substrate 10. The stacked structure 20 with a multilayer structure can be formed by the continuous and alternating stacking of the insulating layer 23 and the gate layer 24. It should be understood that the number and thickness of the insulating layer 23 and the gate layer 24 are not limited to... Figure 1 The number and thickness are shown. In a three-dimensional memory device, the number of layers in the stacked structure 20 determines the number of memory cells in the vertical direction. The number of layers in the stacked structure 20 can be, for example, 32, 64, 96, 108, etc. The more layers in the stacked structure 20, the higher the integration density. Without departing from the concept of this application, those skilled in the art can provide any number and thickness of insulating layers 23 and gate layers 24 as needed. As an example, insulating layer 23 may be made of any material including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof; and gate layer 24 may be made of conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped polycrystalline Si (polycrystalline silicon), doped single-crystal Si, silicides, or any combination thereof.

[0064] In this embodiment, the core array region C may include a first core array region C10 and a second core array region C20 disposed along the X direction. The core array region C is used to form array memory cell strings for information storage. These memory cell strings are multiple interconnected memory cells formed perpendicular to the substrate direction. The memory cell strings are arranged in an array in the column and row directions within the substrate plane. The row direction can be the word line direction, and the column direction can be the bit line direction. The step region SS may be located between the first core array region C10 and the second core array region C20. Figure 1 As shown, the stepped region SS is covered by a dielectric insulating layer SS10 and a dielectric filling layer SS20, and a dielectric overlay layer is also formed over the entire region. In other embodiments, the stepped region SS may not be covered by the dielectric insulating layer SS10. A word line connection circuit is formed in the stepped region SS for transmitting control information to the core array region C, so as to realize the reading and writing of information in the core array region C. The driving mode of the three-dimensional storage device 100 according to this embodiment is center driving, that is, the stepped region SS is located between two adjacent core array regions C10 and C20. However, this application is not limited to this. For example, the three-dimensional storage device 100 according to this embodiment may include a stepped region, a core array region and a stepped region arranged sequentially along the X direction. In this case, the driving mode of the three-dimensional storage device 100 is word line end driving.

[0065] Reference Figure 2 The first wall structure 30 can be arranged along the X direction in the step area SS. The first wall structure 30 can be a partially stacked structure that is completely preserved during the process of forming the step by etching and trimming. The first wall structure 30 can have the same number of layers and stacking order as the stacked structure 20.

[0066] The second wall structure 40 may be arranged along the Y direction in the step area SS and may intersect with the first wall structure 30. The second wall structure 40 may be a partially stacked structure that is fully preserved during the process of forming the steps by etching and trimming, and the second wall structure 40 may have the same number of layers and stacking order as the stacked structure 20.

[0067] The three-dimensional memory device 100 may further include a plurality of gate line gap structures 50 that extend through the stacked structure 20 in a direction perpendicular to the substrate 10. The gate line gap structures 50 may extend in the X direction to divide the stacked structure 20 into a plurality of memory blocks. Gate line separation structures may be formed in the gate line gap structures 50 by filling, and these separation structures may include conductive walls and insulating layers surrounding the sidewalls of the conductive walls. The bottom end of the conductive walls may be connected to the substrate 10. The conductive walls may be, for example, an array common source structure (ACS) (not shown). For example, the array common source structure may consist of a lower polysilicon layer and an upper tungsten metal layer.

[0068] In this embodiment, the plurality of gate line gap structures 50 may include a plurality of first gate line gap structures 501, a plurality of second gate line gap structures 502, and a plurality of third gate line gap structures 503 arranged alternately along the Y direction. The first gate line gap structures 501 and the third gate line gap structures 503 may extend along the X direction through the first core array region C10, the step region SS, and the second core array region C20. The second gate line gap structures 502 may extend along the X direction within the first core array region C10 and the second core array region C20.

[0069] Additionally, at least one second gate gap structure 502 and at least one third gate gap structure 503 may be present between two adjacent first gate gap structures 501; and at least one third gate gap structure 503 may be present between two adjacent second gate gap structures 502. Specifically, as Figure 2 As shown in the figure, in this embodiment, there may be three second gate gap structures 502 and two third gate gap structures 503 between two adjacent first gate gap structures 501; and there may be one third gate gap structure 503 between two adjacent second gate gap structures 502.

[0070] In addition, the third grid gap structure 503 can extend through the first wall structure 30 to electrically connect the first core array region C10, the step region SS, and the second core array region C20.

[0071] The three-dimensional memory device 100 may further include multiple channel structures 60 and multiple virtual channel structures 70. The three-dimensional memory device 100 implements data storage functionality through the channel structures 60. Each channel structure 60 contacts the gate layer 24 from its sidewall and forms a memory cell structure, with a drain leading out at its top and connected to a bit line, and a source leading out at its bottom. Each channel structure 60 may include: a channel via penetrating the stacked structure 20 along a direction perpendicular to the substrate 10, and a multilayer functional layer structure stacked sequentially from the outside to the inside along the sidewall of the channel via. This multilayer functional layer may be a barrier insulating layer, a charge trapping layer, a tunneling insulating layer, a channel layer, and a dielectric layer structure. The multilayer functional layer structure stacked sequentially from the outside to the inside may, for example, be an oxide-nitride-oxide-polysilicon (ONOP) structure. The insulating layer, charge trapping layer, and tunneling insulating layer constitute the memory functional layer to realize the memory function. An exemplary material for the barrier insulating layer and tunneling insulating layer is silicon oxide, and an exemplary material for the charge trapping layer is silicon nitride, forming a silicon oxide-silicon nitride-silicon oxide (ONO) structure. An exemplary material for the channel layer is polycrystalline silicon. However, it will be understood that these layers may be made of other materials. For example, the material of the barrier insulating layer may include a high-k (dielectric constant) oxide layer. The charge trapping layer may be a floating gate structure, for example, comprising polycrystalline silicon. The material of the channel layer may include semiconductor materials such as monocrystalline silicon, monocrystalline germanium, SiGe, Si:C, SiGe:C, and SiGe:H. An exemplary material for the dielectric layer is silicon oxide. It should be understood that the channel structure 60 may also include other layers known in the art.

[0072] Each virtual channel structure 70 may include: a virtual channel via penetrating the stacked structure 20 along a direction perpendicular to the substrate 10, and a virtual channel material layer formed along the sidewall of the virtual channel via. The virtual channel structure 70 does not actually serve as a memory cell, but rather functions to, for example, support the stacked structure 20 or implement process variation control during fabrication to ensure the safe and efficient execution of various steps in the formation of the internal structure of the three-dimensional memory device 100. The virtual channel structure 70 may contain a virtual channel material layer penetrating the stacked structure 20. This virtual channel material layer is not removed when the sacrificial layer is removed, thus supporting the stacked structure 20 and preventing the structure of the three-dimensional memory device 100 from collapsing. An exemplary material for the virtual channel material layer is silicon oxide. According to an exemplary embodiment of this disclosure, the virtual channel structure 70 may also have a structure similar to the channel structure 60, such as an ONOP structure formed within a virtual channel via. In other embodiments, the virtual channel structure 70 may have the same dimensions as the channel structure 60.

[0073] A polysilicon layer 80 may also be formed on the substrate 10. The bottom of the array common-source structure in the channel structure 60 and the gate gap structure 50 is electrically connected to the polysilicon layer 80. The array common-source structure can bring out the source of the channel structure 60 through the polysilicon layer 80.

[0074] like Figure 2 As shown in this embodiment, a channel structure 60 may be provided in the first core array region C10 and the second core array region C20, and a virtual channel structure 70 may be provided in the step region SS. In other embodiments, the virtual channel structure 70 may also exist in both the step region SS and the core array region.

[0075] According to this embodiment, the three-dimensional storage device 100 can increase the support in the Y direction of the step region SS by setting a second wall structure 40 extending in the Y direction in the step region SS, which can reduce the stress deformation of the step region SS and improve the yield and reliability of the three-dimensional storage device 100.

[0076] Example 2

[0077] Figure 3 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to another embodiment of this application. (See attached diagram.) Figure 3 As shown, the three-dimensional storage device 200 according to this embodiment may include a substrate, a stacked structure, and a first wall structure 30. The stacked structure may be formed on the substrate. The stacked structure may have a first core array region C10, a step region SS, and a second core array region C20 disposed along the X direction. The first wall structure 30 may be disposed in the step region SS along the X direction.

[0078] The difference between this embodiment and Embodiment 1 is that the step area SS only has the first wall structure 30 and does not include the second wall structure set along the Y direction, so it will not be described again.

[0079] Reference Figure 3 The first wall structure 30 can be disposed along the X direction in the step region SS. The first wall structure 30 can be a partially stacked structure that is fully preserved during the process of forming the step by etching and trimming. The first wall structure 30 can have the same number of layers and stacking order as the stacked structure. Furthermore, the third gate gap structure 503 can extend through the first wall structure 30 to electrically connect the first core array region C10, the step region SS, and the second core array region C20.

[0080] In this embodiment, a channel structure 60 may be provided in the first core array region C10 and the second core array region C20, and a channel structure 60 may be provided in the first wall structure 30, and a virtual channel structure 70 may be provided in the remaining part of the step region SS other than the first wall structure 30.

[0081] It should be noted that, according to this embodiment, the three-dimensional storage device 200 arranges a channel structure 60 in the first wall structure 30 in the step region SS. Since the ONOP structure filled in the channel structure 60 is harder than the oxide layer filled in the virtual channel structure 70, it can provide better support. Therefore, the stress deformation of the step region SS can be reduced, which is beneficial to improving the yield and reliability of the three-dimensional storage device 200.

[0082] Example 3

[0083] Figure 4 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to yet another embodiment of this application. Figure 4 As shown, the three-dimensional storage device 300 according to this embodiment may include a substrate, a stacked structure, a first wall structure 30, and a second wall structure 40. The stacked structure may be formed on the substrate. The stacked structure may have a first core array region C10, a step region SS, and a second core array region C20 disposed along the X direction. The first wall structure 30 may be disposed in the step region SS along the X direction. The second wall structure 40 may be disposed in the step region SS along the Y direction and may intersect with the first wall structure 30.

[0084] The difference between this embodiment and embodiment 1 is that a channel structure 60 is arranged in the first wall structure 30, so it will not be described again.

[0085] Reference Figure 4 The first wall structure 30 can be disposed along the X direction in the step region SS. The first wall structure 30 can be a partially stacked structure that is fully preserved during the process of forming the step by etching and trimming. The first wall structure 30 can have the same number of layers and stacking order as the stacked structure. Furthermore, the third gate gap structure 503 can extend through the first wall structure 30 to electrically connect the first core array region C10, the step region SS, and the second core array region C20.

[0086] The second wall structure 40 can be arranged along the Y direction in the step area SS and can intersect with the first wall structure 30. The second wall structure 40 can be a partially stacked structure that is completely preserved during the process of forming the steps by etching and trimming. The second wall structure 40 can have the same number of layers and stacking order as the stacked structure 20, or it can be different.

[0087] In this embodiment, a channel structure 60 may be provided in the first core array region C10 and the second core array region C20, and a channel structure 60 may be provided in the first wall structure 30, and a virtual channel structure 70 may be provided in the remaining part of the step region SS other than the first wall structure 30.

[0088] It should be noted that, according to this embodiment, the three-dimensional storage device 300 arranges a channel structure 60 in the first wall structure 30 in the step region SS and arranges a second wall structure 40 extending along the Y direction. Since the ONOP structure filled in the channel structure 60 is harder than the oxide layer filled in the virtual channel structure 70, it can provide better support. Therefore, it can effectively strengthen the support of the first wall structure 30 and the support in the Y direction, reduce stress deformation, and does not increase the additional process. This can reduce the stress deformation in the step region SS, which is beneficial to improving the yield and reliability of the three-dimensional storage device 300.

[0089] Example 4

[0090] Figure 5 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to yet another embodiment of this application. Figure 5 As shown, the three-dimensional storage device 400 according to this embodiment may include a substrate, a stacked structure, a first wall structure 30, and a second wall structure 40. The stacked structure may be formed on the substrate. The stacked structure may have a first core array region C10, a step region SS, and a second core array region C20 disposed along the X direction. The first wall structure 30 may be disposed in the step region SS along the X direction. The second wall structure 40 may be disposed in the step region SS along the Y direction and may intersect with the first wall structure 30.

[0091] The difference between this embodiment and embodiment 1 is that a channel structure 60 is arranged in the second wall structure 40, so it will not be described again.

[0092] Reference Figure 5 The first wall structure 30 can be disposed along the X direction in the step region SS. The first wall structure 30 can be a partially stacked structure that is fully preserved during the process of forming the step by etching and trimming. The first wall structure 30 can have the same number of layers and stacking order as the stacked structure. Furthermore, the third gate gap structure 503 can extend through the first wall structure 30 to electrically connect the first core array region C10, the step region SS, and the second core array region C20.

[0093] The second wall structure 40 can be arranged along the Y direction in the step area SS and can intersect with the first wall structure 30. The second wall structure 40 can be a partially stacked structure that is completely preserved during the process of forming the steps by etching and trimming. The second wall structure 40 can have the same number of layers and stacking order as the stacked structure 20, or it can be different.

[0094] In this embodiment, a channel structure 60 may be provided in the first core array region C10 and the second core array region C20, and a channel structure 60 may be provided in the second wall structure 40, and a virtual channel structure 70 may be provided in the remaining part of the step region SS other than the second wall structure 40.

[0095] It should be noted that, according to this embodiment, the three-dimensional storage device 400 arranges a second wall structure 40 extending along the Y direction and arranges a channel structure 60 in the second wall structure 40. Since the ONOP structure filled in the channel structure 60 is harder than the oxide layer filled in the virtual channel structure 70, it can provide better support effect. Therefore, the support in the Y direction can be further strengthened, stress deformation can be reduced, and no additional process is added. This can reduce the stress deformation in the step area SS, which is beneficial to improving the yield and reliability of the three-dimensional storage device 400.

[0096] Example 5

[0097] Figure 6 This is a top view schematic diagram illustrating a portion of a three-dimensional storage structure according to yet another embodiment of this application. Figure 6 As shown, the three-dimensional storage device 500 according to this embodiment may include a substrate, a stacked structure, a first wall structure 30, and a second wall structure 40. The stacked structure may be formed on the substrate. The stacked structure may have a first core array region C10, a step region SS, and a second core array region C20 disposed along the X direction. The first wall structure 30 may be disposed in the step region SS along the X direction. The second wall structure 40 may be disposed in the step region SS along the Y direction and may intersect with the first wall structure 30.

[0098] The difference between this embodiment and embodiment 1 is that both the first wall structure 30 and the second wall structure 40 are provided with a channel structure 60, so it will not be described again.

[0099] Reference Figure 6 The first wall structure 30 can be disposed along the X direction in the step region SS. The first wall structure 30 can be a partially stacked structure that is fully preserved during the process of forming the step by etching and trimming. The first wall structure 30 can have the same number of layers and stacking order as the stacked structure. Furthermore, the third gate gap structure 503 can extend through the first wall structure 30 to electrically connect the first core array region C10, the step region SS, and the second core array region C20.

[0100] The second wall structure 40 may be arranged along the Y direction in the step area SS and may intersect with the first wall structure 30. The second wall structure 40 may be a partially stacked structure that is fully preserved during the process of forming the steps by etching and trimming, and the second wall structure 40 may have the same number of layers and stacking order as the stacked structure 20.

[0101] In this embodiment, a channel structure 60 may be provided in the first core array region C10 and the second core array region C20, and a channel structure 60 may be provided in the first wall structure 30 and the second wall structure 40, and a virtual channel structure 70 may be provided in the remaining part of the step region SS other than the first wall structure 30 and the second wall structure 40.

[0102] It should be noted that, according to this embodiment, the three-dimensional storage device 500 arranges a channel structure 60 in the first wall structure 30 in the step region SS, and arranges a second wall structure 40 extending along the Y direction and arranges the channel structure 60 in the second wall structure 40. Since the ONOP structure filled in the channel structure 60 is harder than the oxide layer filled in the virtual channel structure 70, it can provide better support. Therefore, it can further strengthen the support of the first wall structure 30 and the support in the Y direction, reduce stress deformation, and without adding additional processes. This can reduce the stress deformation in the step region SS, which is beneficial to improving the yield and reliability of the three-dimensional storage device 500.

[0103] Those skilled in the art should understand that other configurations and functions of the three-dimensional storage devices and their formation methods in the embodiments of this application are known to those skilled in the art, and will not be described in detail in order to reduce redundancy.

[0104] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the invention. Therefore, the preferred embodiments disclosed herein are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A three-dimensional storage device, comprising: A stacked structure having a core array region and a stepped region arranged along a first direction; the stacked structure includes a first wall structure and a second wall structure located in the stepped region, the first wall structure extending along the first direction; the second wall structure extending along a second direction, and the first direction and the second direction intersecting; as well as A channel structure that penetrates the stacked structure in a direction perpendicular to the stacked structure; The first wall structure and / or the second wall structure are provided with the channel structure; each channel structure includes a multi-layer functional layer structure.

2. The three-dimensional memory device of claim 1, wherein, The multilayer functional layer structure includes: a barrier insulating layer, a charge trapping layer, a tunneling insulating layer, a channel layer, and a dielectric layer structure stacked sequentially from the outside to the inside along the thickness direction perpendicular to the stacked structure.

3. The three-dimensional memory device of claim 1, wherein, The first direction is perpendicular to the second direction.

4. The three-dimensional memory device of claim 3, wherein, The three-dimensional storage device further includes a plurality of gate line gap structures that penetrate the stacked structure along a direction perpendicular to the stacked structure.

5. The three-dimensional memory device of claim 4, wherein, The plurality of gate line gap structures include a plurality of first gate line gap structures, a plurality of second gate line gap structures, and a plurality of third gate line gap structures arranged alternately along the second direction, wherein the first gate line gap structures and the third gate line gap structures extend through the core array region and the step region along the first direction, and the second gate line gap structures extend within the core array region along the first direction.

6. The three-dimensional memory device of claim 5, wherein, There is at least one second gate line gap structure and at least one third gate line gap structure between two adjacent first gate line gap structures; as well as There is at least one of the third gate gap structures between two adjacent second gate gap structures.

7. The three-dimensional memory device of claim 5, wherein, The third gate gap structure extends through the first wall structure to electrically connect the core array region and the step region.

8. The three-dimensional memory device of claim 1, wherein, The core array region includes a first core array region and a second core array region, and the step region is located between the first core array region and the second core array region.

9. The three-dimensional memory device of claim 1, wherein, The first wall structure and the second wall structure include an insulating layer and a gate layer that are continuously and alternately arranged in a direction perpendicular to the stacked structure.

10. The three-dimensional memory device of any one of claims 1-9, wherein, The three-dimensional storage device also includes multiple virtual channel structures; Each of the virtual channel structures includes: a virtual channel hole penetrating the stack structure along a direction perpendicular to the stack structure, and an oxide layer formed along the sidewall of the virtual channel hole.

11. The three-dimensional memory device of claim 10, wherein, The channel structure is provided in the core array region, and the virtual channel structure is provided in the step region and / or the core array region.

12. The three-dimensional memory device of claim 10, wherein, The channel structure is provided in the core array area, and the channel structure is also provided in the first wall structure.

13. The three-dimensional memory device of claim 12, wherein, The virtual channel structure is provided in the remaining part of the stepped area, excluding the first wall structure.

14. The three-dimensional memory device of claim 10, wherein, The channel structure is provided in the core array region, and the channel structure is also provided in the second wall structure.

15. The three-dimensional memory device of claim 14, wherein, The virtual channel structure is provided in the remaining part of the stepped area, excluding the second wall structure.

16. The three-dimensional memory device of claim 10, wherein, The channel structure is provided in the core array area, and the channel structure is also provided in the first wall structure and the second wall structure.

17. The three-dimensional memory device of claim 16, wherein, The virtual channel structure is provided in the remaining part of the stepped area, excluding the first wall structure and the second wall structure.

18. A three-dimensional storage device, comprising: A stacked structure having a core array region and a stepped region arranged along a first direction; as well as Multiple channel structures and multiple virtual channel structures, wherein the channel structures and the virtual channel structures penetrate the stacked structure along a direction perpendicular to the stacked structure; The stacked structure includes a first wall structure located in the stepped area. The first wall structure extends along the first direction and has the same number of layers and stacking order as the portion of the stacked structure located in the core array area. The first wall structure is provided with the channel structure. The core array region includes a first core array region and a second core array region arranged in a first direction. The step region is located between the first core array region and the second core array region. The step region is a continuous region and contacts the first core array region and the second core array region.

19. The three-dimensional memory device of claim 18, wherein, The three-dimensional storage device further includes a plurality of gate line gap structures that penetrate the stacked structure along a direction perpendicular to the stacked structure.

20. The three-dimensional memory device of claim 19, wherein, The plurality of gate line gap structures include a plurality of first gate line gap structures, a plurality of second gate line gap structures, and a plurality of third gate line gap structures arranged alternately along a second direction perpendicular to the first direction, wherein the first gate line gap structures and the third gate line gap structures extend along the first direction through the core array region and the step region, and the second gate line gap structures extend along the first direction within the core array region.

21. The three-dimensional memory device of Claim 20, wherein, There is at least one second gate line gap structure and at least one third gate line gap structure between two adjacent first gate line gap structures; as well as There is at least one of the third gate gap structures between two adjacent second gate gap structures.

22. The three-dimensional memory device of Claim 20, wherein, The third gate gap structure extends through the first wall structure to electrically connect the core array region and the step region.

23. The three-dimensional memory device of Claim 18, wherein, The first wall structure includes an insulating layer and a gate layer that are continuously and alternately arranged in a direction perpendicular to the stacked structure.

24. The three-dimensional storage device according to claim 18, wherein, Each of the channel structures includes: a channel hole penetrating the stacked structure along a direction perpendicular to the stacked structure, and oxide-nitride-oxide-polysilicon-oxide structures stacked sequentially from the outside to the inside along the sidewalls of the channel hole; and Each of the virtual channel structures includes: a virtual channel hole penetrating the stack structure along a direction perpendicular to the stack structure, and an oxide layer formed along the sidewall of the virtual channel hole.

25. The three-dimensional memory device of claim 18, wherein, The core array region is provided with the channel structure, and the step region, excluding the first wall structure, is provided with the virtual channel structure.

26. The three-dimensional memory device of any one of claims 18-24, wherein, The stacked structure further includes a second wall structure located in the stepped area, the second wall structure extending along a second direction; and The first wall structure and the second wall structure intersect.

27. The three-dimensional memory device of claim 26, wherein, The channel structure is disposed in the core array region, and the dummy channel structure is disposed in the rest of the step region except the first wall structure.

28. The three-dimensional memory device of claim 26, wherein, The channel structure is disposed in the core array region, and the channel structure is disposed in the second wall structure.

Images