Display panel and manufacturing method thereof

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a preparation method thereof. The display panel comprises a display part, a bending part and a binding part connected in sequence, the binding part is bent to a non-display side of the display part through the bending part; the display panel further comprises a substrate and a third conductive layer on one side of the substrate, the substrate comprises a first substrate film layer, a second substrate film layer and a fourth conductive layer arranged in sequence, the second substrate film layer covers the fourth conductive layer, the fourth conductive layer comprises at least one adapter line, the adapter line extends from the display part to the binding part; the third conductive layer comprises at least one first signal line on the display part and at least one second signal line on the binding part, the adapter line is connected to the corresponding first signal line and second signal line through a via, and the fourth conductive layer is located in a stress neutral layer of the bending part.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a method for manufacturing the same. Background Technology

[0002] With the development of display technology, display devices can perform more and more functions. For example, display devices can automatically collect ambient light and adjust the display color temperature and brightness according to the ambient light. However, in related technologies, due to the accuracy limitations of the ambient light sensing devices, these devices occupy a large area, which affects the realization of other functions of the display screen. Summary of the Invention

[0003] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and a method for manufacturing the same.

[0004] According to one aspect of this disclosure, a display panel is provided, comprising a display portion, a bending portion, and a bonding portion connected in sequence, wherein the bonding portion is bent to the non-display side of the display portion via the bending portion; the display panel further comprises: a substrate, the substrate comprising: a first substrate film layer; a second substrate film layer located on one side of the first substrate film layer; a fourth conductive layer located between the first substrate film layer and the second substrate film layer, wherein the second substrate film layer covers the fourth conductive layer, the fourth conductive layer comprising: at least one adapter line extending from the display portion to the bonding portion; a third conductive layer located on the side of the second substrate film layer opposite to the first substrate film layer, the third conductive layer comprising: at least one first signal line located in the display portion; at least one second signal line located in the bonding portion; wherein the adapter line is connected to the corresponding first signal line and the second signal line respectively via vias, and the fourth conductive layer is located in the stress neutral layer of the bending portion.

[0005] In an exemplary embodiment of this disclosure, the thickness of the first substrate film layer at the bend is greater than the thickness of the second substrate film layer at the bend.

[0006] In an exemplary embodiment of this disclosure, the thickness of the second substrate film at the bend is less than 10 μm, and the ratio of the thickness of the second substrate film at the bend to the thickness of the first substrate film at the bend is 0.5 to 0.7.

[0007] In an exemplary embodiment of this disclosure, the thickness of the second substrate film at the bend is greater than or equal to 5 μm and less than or equal to 7 μm.

[0008] In an exemplary embodiment of this disclosure, the thickness of the first substrate film layer at the bend is greater than 10 μm, and the ratio of the thickness of the first substrate film layer at the bend to the thickness of the second substrate film layer at the bend is 0.66 to 0.78.

[0009] In an exemplary embodiment of this disclosure, the thickness of the first substrate film layer at the bend is greater than or equal to 13 μm and less than or equal to 15 μm.

[0010] In an exemplary embodiment of this disclosure, the display panel further includes: a second conductive layer located between the third conductive layer and the second substrate film layer, the second conductive layer including: a first bridging wire located in the display portion and corresponding to the first signal line, the first bridging wire being connected to the adapter wire and the first signal line respectively through vias; and a second bridging wire located in the bonding portion and corresponding to the second signal line, the second bridging wire being connected to the adapter wire and the second signal line respectively through vias.

[0011] In an exemplary embodiment of this disclosure, the display panel further includes: a first conductive layer located between the third conductive layer and the second substrate film layer; the first conductive layer includes: a third bridging wire located in the display portion, the third bridging wire being connected to the first signal line and the adapter wire respectively through vias; and a fourth bridging wire located in the bonding portion, the fourth bridging wire being connected to the second signal line and the adapter wire respectively through vias.

[0012] In an exemplary embodiment of this disclosure, the substrate further includes: a first isolation layer located between the first substrate film layer and the fourth conductive layer, the first isolation layer extending from the display portion to the bonding portion; the display panel further includes: a first planarization layer located between the substrate and the third conductive layer, the first planarization layer extending from the display portion to the bonding portion, and the portion of the first planarization layer located at the bend portion covering the second substrate film layer; a second planarization layer located on the side of the first planarization layer opposite to the substrate, the second planarization layer extending from the display portion to the bonding portion, and the portion of the second planarization layer located at the bend portion covering the first planarization layer; a pixel defining layer located on the side of the second planarization layer opposite to the substrate, the pixel defining layer extending from the display portion to the bonding portion, the pixel defining layer having a pixel opening in the display portion, an organic light-emitting layer covering the pixel opening, and the portion of the pixel defining layer located at the bend portion covering the second planarization layer.

[0013] According to a second aspect of this disclosure, a method for manufacturing a display panel is also provided, for manufacturing the display panel described in any embodiment of this disclosure, the method comprising: S110, forming a first substrate film layer, wherein the first substrate film layer includes a display portion, a bending portion, and a bonding portion connected in sequence; S120, forming a fourth conductive layer on one side of the first substrate film layer, wherein the fourth conductive layer includes at least one adapter line extending from the display portion to the bonding portion; S130, forming a second substrate film layer on the side of the fourth conductive layer opposite to the first substrate film layer; S140, forming a third conductive layer on the side of the second substrate film layer opposite to the first substrate film layer, the third conductive layer including at least one first signal line and at least one second signal line, the first signal line being located in the display portion and the second signal line being located in the bonding portion; the adapter line being connected to the corresponding first signal line and the second signal line respectively through vias, and the fourth conductive layer being located in the stress neutral layer of the bending portion.

[0014] The display panel provided in this disclosure has a fourth conductive layer disposed between a first substrate film layer and a second substrate film layer. A transition line in the fourth conductive layer connects a first signal line of the third conductive layer located in the display section and a second signal line located in the bonding section. This adjusts the relative positional relationship between the second substrate film layer and the conductive layer in the bending section, so that the second substrate film layer is located on the side of the bending section away from the center of the conductive layer. By setting the fourth conductive layer, the relative positions of the films affecting the stress distribution in the bending section are changed. Furthermore, by adjusting the thickness of the first substrate film layer and / or the thickness of the second substrate film layer, the stress distribution on both sides of the conductive layer in the bending section is adjusted, so that the transition line in the fourth conductive layer is located in the stress neutral layer of the bending section. Therefore, it is no longer necessary to set a UV adhesive layer on the side of the bending section away from the center of the bending section, which reduces costs and allows for a reduction in the size of the bottom bezel of the display panel.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 This is a schematic diagram of the structure of a display panel before bending in related technologies;

[0018] Figure 2 for Figure 1A schematic diagram of the structure of the display panel after bending;

[0019] Figure 3 This is a schematic diagram of the structure of a display panel according to one embodiment of the present disclosure;

[0020] Figure 4 for Figure 3 The diagram shown is a schematic representation of the display panel before it is bent.

[0021] Figure 5 According to another embodiment of this disclosure Figure 3 The diagram shown is a structural schematic of the display panel before it is bent.

[0022] Figure 6 In another embodiment according to this disclosure Figure 3 The diagram shown is a structural schematic of the display panel before it is bent.

[0023] Figures 7-1 Figure 4 shows the manufacturing process flow diagram of the display panel. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0025] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0026] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0027] Figure 1 This is a schematic diagram of the structure of a display panel before bending in related technologies. Figure 2 for Figure 1 A schematic diagram of the structure of the display panel after bending is shown, as follows: Figure 1 and Figure 2 As shown, the metal traces of the SD1 layer are located on the side of the second substrate film layer PI2 away from the first substrate film layer PI1. Therefore, after the display panel is bent, in the bent portion of the display panel, the outer structure of the SD1 layer includes the pixel defining layer PDL, the second planarization layer PLN2, and the first planarization layer PLN1, while the inner structure of the SD1 layer includes the second substrate film layer PI2, the first isolation layer Barrier1, and the first substrate film layer PI1. The thickness of the outer film layer is much smaller than that of the inner film layer. According to Hooke's Law, the stress in the inner structure of the SD1 layer is much greater than that in the outer structure. Therefore, by coating the pixel defining layer PDL with UV adhesive to reinforce the outer structure of the SD1 layer, the stress in the inner and outer structures of the SD1 layer is made the same. The inventors found the following shortcomings in this solution:

[0028] 1. Because additional UV adhesive needs to be applied, corresponding process equipment and BOM costs are required.

[0029] 2. The process accuracy of UV adhesive coating is within ±30μm. The thickness accuracy of UV adhesive will cause the SD layer to fluctuate near the stress neutral layer, making it impossible for the inner and outer structures of the SD1 layer to achieve an ideal stress balance.

[0030] 3. Under current process conditions, by coating with UV adhesive to compensate for the external stress of the SD1 layer, the bending radius of the SD1 layer can only reach 300μm and cannot be further reduced. As a result, the bottom bezel size L of the display panel cannot be further reduced, thus failing to meet the requirements for ultra-narrow bezels.

[0031] Therefore, this disclosure provides a novel display panel to solve the above-mentioned problems.

[0032] Figure 3 This is a schematic diagram of the structure of a display panel according to one embodiment of the present disclosure. Figure 4 for Figure 3 The diagram shown is a structural illustration of the display panel before it is bent. Figure 3 and Figure 4As shown, the display panel disclosed herein may include a display section AA, a bending section BED, and a bonding section BOD connected in sequence. The bonding section BOD is bent to the non-display side of the display section AA via the bending section BED. The display panel may also include a substrate and a third conductive layer SD1. The substrate may include a first substrate film layer PI1, a second substrate film layer PI2, and a fourth conductive layer SD0. The second substrate film layer PI2 is located on one side of the first substrate film layer PI1, and the fourth conductive layer SD0 is located between the first substrate film layer PI1 and the second substrate film layer PI2. The second substrate film layer PI2 covers the fourth conductive layer SD0. The fourth conductive layer SD0 may include... At least one adapter cable SD0-1 extends from the display part AA to the bonding part BOD; the third conductive layer SD1 is located on the side of the second substrate film layer PI2 away from the first substrate film layer PI1, and the third conductive layer SD1 may include at least one first signal line SD1-1 and at least one second signal line SD1-2, the first signal line SD1-1 is located in the display part AA, and the second signal line SD1-2 is located in the bonding part BOD; wherein, the adapter cable SD0-1 is connected to the corresponding first signal line SD1-1 and second signal line SD1-2 through vias respectively, and the fourth conductive layer SD0 is located in the stress neutral layer of the bending part BED.

[0033] The display panel disclosed herein has a fourth conductive layer SD0 disposed between a first substrate film layer PI1 and a second substrate film layer PI2. A transition line SD0-1 in the fourth conductive layer SD0 connects a first signal line SD1-1 of the third conductive layer SD1 located in the display section AA and a second signal line SD1-2 located in the bonding section BOD. This adjusts the relative positional relationship between the second substrate film layer PI2 and the conductive layer in the bending section BED, so that the second substrate film layer PI2 is located on the side of the bending section BED away from the center of the conductive layer. By setting the fourth conductive layer SD0, the relative positions of the films affecting stress distribution in the bending section BED are changed. Furthermore, by adjusting the thickness of the first substrate film layer PI1 and / or the thickness of the second substrate film layer PI2, the stress distribution on both sides of the conductive layer in the bending section BED is adjusted, so that the transition line SD0-1 in the fourth conductive layer SD0 is located in the stress neutral layer of the bending section BED. Therefore, it is no longer necessary to set a UV adhesive layer on the side of the bending section BED away from the center of the bending section BED, which reduces costs and allows for a reduction in the bottom bezel size L of the display panel.

[0034] The substrate disclosed herein can be a flexible substrate, and the first substrate film layer PI1 and the second substrate film layer PI2 can be flexible organic materials, such as polyimide layers.

[0035] like Figure 3As shown, the binding part BOD is bent to the non-display side of the display part AA via the bending part BED, so that the binding part BOD is set opposite to the display part AA on the back side of the display panel.

[0036] Combination Figure 3 and Figure 4 It can be seen that after the bending portion BED is bent, it forms an arc-shaped structure. The first substrate film layer PI1 is located on the side of the adapter line SD0-1 closer to the center of the arc of the bending structure, while the second substrate film layer PI2 is located on the side of the adapter line SD0-1 away from the center of the arc of the bending structure. It can be seen that compared to Figure 1 In the related technology, the display panel structure uses a fourth conductive layer SD0 to transfer the signal lines in the third conductive layer SD1, adjusting the stress position of the second substrate film layer PI2 in the bending section BED. The stress is changed from being generated on the inner side of the conductive layer to being generated on the outer side of the conductive layer. Thus, the stress distribution in the bending section BED can be balanced by adjusting the thickness of the first substrate film layer PI1 and the second substrate film layer PI2, so that the stress on the inner and outer structures of the fourth conductive layer SD0 is balanced, without the need for additional UV adhesive to balance the stress distribution in the bending section BED. This makes the fourth conductive layer SD0 located in the stress neutral layer of the bending section BED, so that the stress on the transfer line SD0-1 in the fourth conductive layer SD0 is zero. This approach saves on the cost of UV adhesive and the equipment used for applying it. Furthermore, since UV adhesive is not required, the bending radius r of the bent portion BED can be further reduced, thereby allowing for a further reduction in the bottom bezel size L of the display panel. It also enables precise control over the thickness of the first substrate film layer PI1 and the second substrate film layer PI2, ensuring complete stress balance between the inner and outer structures of the fourth conductive layer SD0. The third conductive layer SD1 in this disclosure can be a first source / drain metal layer.

[0037] It should be understood that the inner structure of the fourth conductive layer SD0 described in this disclosure can be understood as the film layers located on the side of the fourth conductive layer SD0 near the center of the arc-shaped structure formed by the bending portion BED. The outer structure of the fourth conductive layer SD0 can be understood as the film layers located on the side of the fourth conductive layer SD0 away from the center of the arc-shaped structure formed by the bending portion BED.

[0038] The center of the arc of the arc structure formed by the bending portion BED of this disclosure can be determined by the following method: select any two non-repeating points on the arc structure formed by the bending portion BED, and the intersection of the normals passing through these two points is the center of the arc structure.

[0039] It should be understood that the fourth conductive layer SD0 is located in the stress neutral layer of the bending section BED. In other words, the stress generated by the outer structure of the fourth conductive layer SD0 in the bending section BED is balanced with the stress generated by the inner structure of the fourth conductive layer SD0, so the stress on the fourth conductive layer SD0 is zero.

[0040] The structure and principle of the display panel of this disclosure will be further described below with reference to the accompanying drawings.

[0041] like Figure 4 As shown, in an exemplary embodiment, the substrate may further include a first isolation layer Barrier 1, and the display panel may further include a first planarization layer PLN1, a second planarization layer PLN2, and a pixel boundary layer PDL, wherein:

[0042] The first isolation layer Barrier1 is located between the first substrate film layer PI1 and the fourth conductive layer SD0, and the first isolation layer Barrier1 extends from the display part AA to the bonding part BOD;

[0043] The first planarization layer PLN1 is located between the substrate and the third conductive layer SD1. The first planarization layer PLN1 extends from the display part AA to the bonding part BOD, and the portion of the first planarization layer PLN1 located at the bending part BED covers the second substrate film layer PI2.

[0044] The second planarization layer PLN2 is located on the side of the first planarization layer PLN1 away from the substrate. The second planarization layer PLN2 extends from the display part AA to the bonding part BOD, and the portion of the second planarization layer PLN2 located at the bending part BED covers the first planarization layer PLN1.

[0045] The pixel defining layer PDL is located on the side of the second planarization layer PLN2 away from the substrate. The pixel defining layer PDL extends from the display part AA to the bonding part BOD. The pixel defining layer PDL has a pixel opening in the display part AA. An organic light-emitting layer is covered in the pixel opening. The portion of the pixel defining layer PDL located in the bending part BED is covered by the second planarization layer PLN2.

[0046] Therefore, the bending portion (BED) of the display panel may include a first substrate film layer PI1, a first isolation layer Barrier1, a fourth conductive layer SD0, a second substrate film layer PI2, a first planarization layer PLN1, a second planarization layer PLN2, and a pixel defining layer PDL, which are stacked sequentially. Thus, the stress on the outer structure of the fourth conductive layer SD0 in the bending portion (BED) is the stress generated by the second substrate film layer PI2, the first planarization layer PLN1, the second planarization layer PLN2, and the pixel defining layer PDL. The stress on the inner structure of the fourth conductive portion in the bending portion (BED) is the stress generated by the first substrate film layer PI1 and the first isolation layer Barrier1. Therefore, the stress on the outer and inner structures of the fourth conductive layer SD0 can be balanced by adjusting the thickness of the first substrate film layer PI1 and / or the thickness of the second substrate film layer PI2.

[0047] Table 1

[0048]

[0049] Table 1 shows the thickness distribution of each film layer in the bent portion BED of a display panel according to an embodiment of this disclosure (the molecular structure of the pixel defining layer PDL, the first planarization layer PLN1, and the second planarization layer PLN2 shown in the table may be different from the molecular structure of the first substrate film layer PI1 and the second substrate film layer PI2, thus their Young's moduli are different). The thickness of the first substrate film layer PI1 is the same as the thickness of the second substrate film layer PI2. According to Hooke's Law:

[0050]

[0051] It can be known that:

[0052]

[0053] Where: h is the thickness of the adapter cable SD0-1, a is the thickness of the outer structure of the bending section BED, b is the thickness of the inner structure of the bending section BED, σ 外侧结构 For the stress on the outer structure of the bend, σ 内侧结构 Let E be the stress on the inner side of the bent section, and E be the Young's modulus.

[0054] According to Hooke's Law, when the thickness of the first substrate film layer PI1 is the same as the thickness of the second substrate film layer PI2, the stress on the outer structure of the bent portion BED is greater than the stress on the inner structure.

[0055] Therefore, in this exemplary embodiment, the stress on the outer structure can be reduced by thinning the outer structure, making the stress on the outer and inner structures of the bent portion BED equal. Alternatively, the stress on the inner structure can be increased by increasing the thickness of the inner structure, making the stress on the outer and inner structures of the bent portion BED the same.

[0056] In an exemplary embodiment, the thickness of the first substrate film layer PI1 at the bending portion BED is greater than the thickness of the second substrate film layer PI2 at the bending portion BED. That is, by thinning the second substrate film layer PI2, the thickness of the outer structure of the bending portion BED is reduced, thereby reducing the stress on the outer structure and making the stress on the outer structure of the bending portion BED the same as the stress on the inner structure.

[0057] like Figure 4 As shown, in an exemplary embodiment, the thickness of the first substrate film layer PI1 at the bending portion BED is d1, and the thickness of the second substrate film layer PI2 at the bending portion BED is d2. The ratio of d2 to d1 can be 0.5 to 0.7, for example, 0.5, 0.6, 0.62, 0.65, 0.7, etc.

[0058] For example, the thickness d1 of the first substrate film layer PI1 can be 10 μm, and the thickness of the second substrate film layer PI2 can be 6.2 μm. It can be seen that, compared with the thickness of the first substrate film layer PI1 and the second substrate film layer PI2 in the related technologies shown in Table 1, the thickness of the second substrate film layer PI2 is reduced, thereby reducing the stress on the outer structure of the bent portion BED, and thus making the stress on the outer structure the same as the stress on the inner structure.

[0059] Because the thickness of the second substrate film layer PI2 is reduced, the bending radius r of the bending portion BED can be further reduced. For example, when the thickness of the second substrate film layer PI2 is reduced from 10 μm as shown in Table 1 to 6.2 μm, the bending radius r of the bending portion BED can be reduced from 300 μm to 100 μm, thereby further reducing the bottom bezel size L of the display panel.

[0060] Specifically, such as Figure 3 As shown, the bottom bezel dimension L of the display panel includes the sum of the thickness D1 of the first structural part, the dimension r of the second structural part, and the dimension D2 of the third structural part. The thickness D1 of the first structural part is the sum of the thickness of the outer structure of the bending part BED and half the thickness of the fourth conductive layer SD0. The dimension r of the second structural part is the bending radius of the bending part BED. The dimension D2 of the third structural part is the bezel wiring width of the display panel.

[0061] Clearly, by reducing the dimensions of the outer structure of the bending section BED and the bending radius r of the bending section BED, the bottom bezel size L of the display panel can be further reduced.

[0062] For example, as shown in Table 2,

[0063] Table 2

[0064]

[0065] With the bending portion BED having the above dimensions, the bottom bezel size L of the display panel can be reduced from 1024.88μm (corresponding to the film thickness in Table 1) to 711.08μm, a reduction of 30.62%. This can improve the display panel to achieve a high screen-to-body ratio and enhance the product's competitiveness.

[0066] In other embodiments of this disclosure, while keeping the thickness of the second substrate film layer PI2 constant, the thickness d1 of the first substrate film layer PI1 can be increased, and the thickness d1 of the first substrate film layer PI1 can be greater than the thickness d2 of the second substrate film layer PI2, thereby making the stress on the outer structure of the bent portion BED the same as the stress on the inner structure.

[0067] In an exemplary embodiment, the ratio of the thickness d1 of the first substrate film layer PI1 at the bending portion BED to the thickness d2 of the second substrate film layer PI2 at the bending portion BED is 0.66 to 0.78, for example, it can be 0.66, 0.67, 0.7, 0.75, 0.76, 0.77, 0.78, etc.

[0068] The specific thickness d1 of the first substrate film layer PI1 can be calculated according to Hooke's Law. For example, the thickness d2 of the second substrate film layer PI2 can be 10 μm, and the thickness d1 of the first substrate film layer PI1 can be 13 to 15 μm, such as 13 μm, 14 μm, 15 μm, etc., to satisfy the stress balance between the outer structure and the inner structure of the bent portion BED.

[0069] It should be understood that the thickness of a certain structure in the bending portion BED described in this disclosure can be understood as the thickness value of the structure in the thickness direction of the first substrate film layer P1 of the display panel before the display panel is bent.

[0070] Furthermore, it should be understood that the above embodiments only balance the stress of the outer structure and the inner structure of the bent portion BED by increasing the thickness of the second substrate film layer PI2 or only decreasing the thickness of the first substrate film layer PI1. In other embodiments of this disclosure, the thickness of the first substrate film layer PI1 and the thickness of the second substrate film layer PI2 can also be adjusted simultaneously to balance the stress of the outer structure and the inner structure of the bent portion BED, which will not be described in detail here.

[0071] The connection method between the adapter cable SD0-1 and the first signal line SD1-1 and the second signal line SD1-2 will be further described below with reference to the accompanying drawings.

[0072] like Figure 4 As shown, in an exemplary embodiment, the adapter cable SD0-1 can connect the first signal line SD1-1 and the second signal line SD1-2 respectively through vias. Specifically, each signal line extending from the display unit AA to the bonding unit BOD in the third conductive layer SD1 is disconnected at the bend portion BED and then connected through the adapter cable SD0-1 of the fourth conductive layer SD0. Thus, the first signal line SD1-1 of the display unit AA and the second signal line SD1-2 of the bonding unit BOD are connected via the first conductive block, the adapter cable SD0-1, and the second conductive block to form a signal transmission path.

[0073] Figure 5 According to another embodiment of this disclosure Figure 3 The diagram shown is a structural illustration of the display panel before it is bent. Figure 5 As shown, in an exemplary embodiment, the display panel may further include a second conductive layer Gate2, which is located between the third conductive layer SD1 and the second substrate film layer PI2. The second conductive layer Gate2 may include a first bridging wire GAT2-1 and a second bridging wire GAT2-2. The first bridging wire GAT2-1 is located in the display section AA and is correspondingly disposed with respect to the first signal line SD1-1. The first bridging wire GAT2-1 can be connected to the adapter wire SD0-1 and the first signal line SD1-1 respectively through vias. The second bridging wire GAT2-2 is located in the bonding section BOD and is correspondingly disposed with respect to the second signal line SD1-2. The second bridging wire GAT2-2 can be connected to the adapter wire SD0-1 and the second signal line SD1-2 respectively through vias.

[0074] The second conductive layer Gate2 can be a second gate metal layer. The first bridging wire GAT2-1 is located in the display unit AA and is configured to correspond one-to-one with the first signal line SD1-1. That is, each first signal line SD1-1 has a corresponding first bridging wire GAT2-1 connected to it. The first bridging wire GAT2-1 then extends to the position of the corresponding adapter wire SD0-1 and connects to the adapter wire SD0-1 through a via, thereby achieving the connection between the adapter wire SD0-1 and the first signal line SD1-1. Similarly, the second bridging wire GAT2-2 is configured to correspond one-to-one with the second signal line SD1-2, connecting the adapter wire SD0-1 and the second signal line SD1-2 accordingly. Thus, the first signal line SD1-1, the first bridging portion, the adapter wire SD0-1, the second bridging portion, and the second signal line SD1-2 form a conductive path, transmitting relevant signals between the display unit AA and the bonding unit BOD. For example, signals from the chip IC of the bonding unit BOD can be transmitted to the display unit AA through this conductive path.

[0075] Figure 6In another embodiment according to this disclosure Figure 3 The diagram shown is a structural illustration of the display panel before it is bent. Figure 6 As shown, in an exemplary embodiment, the display panel may further include a first conductive layer Gate1, which is located between a second conductive layer Gate2 and a second substrate film layer PI2. The first conductive layer Gate1 may include a third bridging wire GAT1-1 and a fourth bridging wire GAT1-2. The third bridging wire GAT1-1 is located in the display section AA and is connected to the first signal line SD1-1 and the adapter wire SD0-1 through vias, respectively. The fourth bridging wire GAT1-2 is located in the bonding section BOD and is connected to the second signal line SD1-2 and the adapter wire SD0-1 through vias, respectively.

[0076] The first conductive layer, Gate1, can be, for example, a first gate metal layer (Gate1 layer). The third bridge wire, GAT1-1, is configured to correspond one-to-one with the first signal line, SD1-1, so that the first signal line SD1-1 of the display unit AA is connected to the adapter wire SD0-1 through the third bridge wire, GAT1-1. The fourth bridge wire, GAT1-2, is configured one-to-one with the second signal line SD1-2, so that the second signal line SD1-2 of the bonding unit BOD is connected to the adapter wire SD0-1 through the fourth bridge wire, GAT1-2. Thus, the first signal line SD1-1, the third bridge wire, GAT1-1, the adapter wire SD0-1, the fourth bridge wire, GAT1-2, and the second signal line SD1-2 form a conductive path, transmitting relevant signals between the display unit AA and the bonding unit BOD.

[0077] Furthermore, it is understood that since the display unit AA has transistors, the display unit AA may also include an active layer Polly. The active layer Polly is located between the second substrate film layer PI2 and the first conductive layer Gate1. The active layer Polly is used to form the channel region and source / drain electrodes of the transistor. The drain electrodes of the transistor are connected to the corresponding signal lines in the third conductive layer SD1 through vias.

[0078] Furthermore, a first gate insulating layer GI1 may be present between the active layer Polly and the first conductive layer Gate1, and a second gate insulating layer GI2 may be present between the first conductive layer Gate1 and the second conductive layer Gate2. The first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed in the same layer in the bonding portion BOD.

[0079] Furthermore, the display unit AA may also include an interlayer insulating layer (ILD) and a passivation layer (PVX). The interlayer insulating layer (ILD) is located on the side of the second gate insulating layer (GI2) facing away from the substrate and covers the second conductive layer (Gate2). The passivation layer (PVX) is located on the side of the interlayer insulating layer (ILD) facing away from the substrate and covers the third conductive layer (SD1). Moreover, the interlayer insulating layer (ILD) and the passivation layer (PVX) may be formed in the same layer as the bonding portion (BOD).

[0080] The first planarization layer PLN1 and the second planarization layer PLN2 are stacked on the side of the passivation layer PVX away from the substrate. The first substrate film layer PI1 to the second planarization layer PLN2 form a driving backplate. A light-emitting layer structure can be further formed on the driving backplate, which will not be described in detail here.

[0081] This disclosure also provides a method for manufacturing a display panel, which may include the following steps:

[0082] like Figure 7 As shown, in step S110, the first substrate film layer PI1 is formed.

[0083] The first substrate film layer PI1 may include a display part AA, a bending part BED, and a bonding part BOD connected in sequence.

[0084] like Figure 8 As shown, in S120, a fourth conductive layer SD0 is formed on one side of the first substrate film layer PI1, wherein the fourth conductive layer SD0 includes at least one adapter line SD0-1, which extends from the display part AA to the bonding part BOD.

[0085] like Figure 8 As shown, in an exemplary embodiment, before forming the fourth conductive layer SD0, a first isolation layer Barrier1 may be formed on the first substrate film layer PI1, and the first isolation layer Barrier1 extends from the display portion AA to the bonding portion BOD.

[0086] like Figure 9 As shown, in S130, a second substrate film layer PI2 is formed on the side of the fourth conductive layer SD0 that is away from the first substrate film layer PI1.

[0087] The first substrate film layer PI1, the fourth conductive layer SD0, and the second substrate film layer PI2 form the substrate of the display panel. That is, this disclosure is equivalent to forming a fourth conductive layer SD0 between the two organic layers of the substrate, and connecting the corresponding signal lines in the third conductive layer SD1 in the driving circuit layer through the adapter line SD0-1 in the fourth conductive layer SD0.

[0088] In an exemplary embodiment, such as Figure 9As shown, after forming the second substrate film layer PI2, a second isolation layer Barrier2 and an active layer Polly can be formed on the second substrate film layer PI2. The second isolation layer Barrier2 is located between the display part AA and the bonding part BOD, that is, the second isolation layer Barrier2 is broken at the bending part BED. For example, the second isolation layer Barrier2 can be broken at the bending part BED through a patterning process. The active layer Polly is used to form the channel region and source / drain electrodes of the transistor.

[0089] S140, a third conductive layer SD1 is formed on the side of the second substrate film layer PI2 that is opposite to the first substrate film layer PI1.

[0090] In an exemplary embodiment, such as Figure 12a As shown, the third conductive layer SD1 may include at least one first signal line SD1-1 and at least one second signal line SD1-2. The first signal line SD1-1 is located in the display part AA, and the second signal line SD1-2 is located in the bonding part BOD. The first signal line SD1-1 and the second signal line SD1-2 are respectively connected to the corresponding adapter line SD0-1 through vias, and the fourth conductive layer SD0 is located in the stress neutral layer of the bending part BED.

[0091] In some embodiments of this disclosure, such as Figure 10a As shown, before forming the third conductive layer SD1, a first gate insulating layer GI1 and a first conductive layer Gate1 can be formed on the second substrate film layer PI2 by a deposition process. The first gate insulating layer GI1 can be deposited in its entirety, and then a portion of the bending portion BED is etched away using a patterning process, so that the first gate insulating layer GI1 is located in the display portion AA and the bonding portion BOD.

[0092] like Figure 11a As shown, after the first conductive layer Gate1 is formed, a second gate insulating layer GI2 can be formed on the first conductive layer Gate1 and the first gate insulating layer GI1 by a deposition process, and a second conductive layer Gate2 can be formed on the second gate insulating layer GI2. Similarly, the portion of the second gate insulating layer GI2 located at the bend portion BED can be etched away by an etching process, and only the display portion AA and the bonding portion BOD are retained.

[0093] like Figure 12a As shown, after forming the second conductive layer Gate2, an interlayer insulating layer ILD can be formed on the second conductive layer Gate2 and the second gate insulating layer GI2 by a deposition process. Then, the portion of the interlayer insulating layer ILD located at the bend portion BED is etched away by an etching process, leaving only the display portion AA and the bonding portion BOD.

[0094] like Figure 12aAs shown, a third conductive layer SD1 is formed on the interlayer insulating layer ILD by deposition process, and corresponding signal lines are formed by patterning process. The signal lines that need to be connected to the bonding part BOD are connected to the adapter wire SD0-1 of the fourth conductive layer SD0 through vias. The adapter wire SD0-1 connects the first signal lines SD1-1 of the display part AA to the second signal lines SD1-2 corresponding to the bonding part BOD.

[0095] like Figure 13a As shown, a passivation layer PVX, a first planarization layer PLN1, and a fifth conductive layer SD2 are sequentially formed on the interlayer insulating layer (ILD) using a deposition process. The passivation layer PVX is located at the display area AA and the bonding area BOD, meaning that the passivation layer PVX is disconnected at the bend area BED. The first planarization layer PLN1 extends from the display area AA to the bonding area BOD, and the first planarization layer PLN1 covers the passivation layer PVX at the display area AA and the bonding area BOD, and covers the second substrate film layer PI2 at the bend area BED. The fifth conductive layer SD2 is located on the first planarization layer PLN1, and the signal lines in the fifth conductive layer SD2 can be connected to the corresponding signal lines in the third conductive layer SD1 through vias.

[0096] like Figure 14a As shown, a second planarization layer PLN2 is deposited on the fifth conductive layer SD2 and the first planarization layer PLN1, and the second planarization layer PLN2 covers the fifth conductive layer SD2 and the first planarization layer PLN1.

[0097] An anode layer and a pixel defining layer (PDL) are then formed on the second planarization layer PLN2. The pixel defining layer (PDL) extends from the display portion AA to the bonding portion BOD. The pixel defining layer (PDL) has a pixel opening in the display portion AA, and the pixel opening may include an anode and an organic light-emitting layer. The portion of the pixel defining layer (PDL) located at the bending portion BED covers the second planarization layer PLN2.

[0098] In another embodiment of this disclosure, such as Figure 10b As shown, before forming the third conductive layer SD1, a first gate insulating layer GI1 and a first conductive layer Gate1 can be formed on the second substrate film layer PI2 by a deposition process. The first gate insulating layer GI1 can be deposited in its entirety, and then a portion of the bending portion BED is etched away using a patterning process, so that the first gate insulating layer GI1 is located in the display portion AA and the bonding portion BOD.

[0099] In addition, a third bridge wire GAT1-1 and a fourth bridge wire GAT1-2 can be formed in the first conductive layer Gate1. The third bridge wire GAT1-1 is located in the display part AA, and the fourth bridge wire GAT1-2 is located in the bonding part BOD. The third bridge wire GAT1-1 is connected to the corresponding adapter wire SD0-1 in the fourth conductive layer SD0 through a via, and the fourth bridge wire GAT1-2 is connected to the corresponding adapter wire SD0-1 through a via. Furthermore, by connecting the third bridge wire GAT1-1 and the first signal line SD1-1 in the third conductive layer SD1, and connecting the fourth bridge wire GAT1-2 and the second signal line SD1-2 in the third conductive layer SD1, the first signal line SD1-1 located in the display section AA in the third conductive layer SD1 is connected to the second signal line SD1-2 located in the bonding section BOD in the third conductive layer SD1 through the third bridge wire GAT1-1 of the first conductive layer Gate1, the adapter wire SD0-1 of the fourth conductive layer SD0, and the fourth bridge wire GAT1-2 in the first conductive layer Gate1, thus forming a signal conduction path.

[0100] like Figure 11b As shown, after the first conductive layer Gate1 is formed, a second gate insulating layer GI2 can be formed on the first conductive layer Gate1 and the first gate insulating layer GI1 by a deposition process, and a second conductive layer Gate2 can be formed on the second gate insulating layer GI2. Similarly, the portion of the second gate insulating layer GI2 located at the bend portion BED can be etched away by an etching process, and only the display portion AA and the bonding portion BOD are retained.

[0101] like Figure 12b As shown, after forming the second conductive layer Gate2, an interlayer insulating layer ILD can be formed on the second conductive layer Gate2 and the second gate insulating layer GI2 by a deposition process. Then, the portion of the interlayer insulating layer ILD located at the bend portion BED is etched away by an etching process, leaving only the display portion AA and the bonding portion BOD.

[0102] Then, as Figure 12b As shown, a third conductive layer SD1 is formed on the interlayer insulating layer ILD by deposition process, and corresponding signal lines are formed by patterning process. The signal lines that need to be connected to the bonding part BOD are connected to the adapter wire SD0-1 of the fourth conductive layer SD0 through vias. The adapter wire SD0-1 connects the first signal lines SD1-1 of the display part AA to the second signal lines SD1-2 corresponding to the bonding part BOD.

[0103] like Figure 13bAs shown, a passivation layer PVX, a first planarization layer PLN1, and a fifth conductive layer SD2 are sequentially formed on the interlayer insulating layer (ILD) using a deposition process. The passivation layer PVX is located at the display area AA and the bonding area BOD, meaning that the passivation layer PVX is disconnected at the bend area BED. The first planarization layer PLN1 extends from the display area AA to the bonding area BOD, and the first planarization layer PLN1 covers the passivation layer PVX at the display area AA and the bonding area BOD, and covers the second substrate film layer PI2 at the bend area BED. The fifth conductive layer SD2 is located on the first planarization layer PLN1, and the signal lines in the fifth conductive layer SD2 can be connected to the corresponding signal lines in the third conductive layer SD1 through vias.

[0104] like Figure 14b As shown, a second planarization layer PLN2 is deposited on the fifth conductive layer SD2 and the first planarization layer PLN1, and the second planarization layer PLN2 covers the fifth conductive layer SD2 and the first planarization layer PLN1.

[0105] An anode layer and a pixel defining layer (PDL) are then formed on the second planarization layer PLN2. The pixel defining layer (PDL) extends from the display portion AA to the bonding portion BOD. The pixel defining layer (PDL) has a pixel opening in the display portion AA, and the pixel opening may include an anode and an organic light-emitting layer. The portion of the pixel defining layer (PDL) located at the bending portion BED covers the second planarization layer PLN2.

[0106] In yet another embodiment of this disclosure, such as Figure 10c As shown, before forming the third conductive layer SD1, a first gate insulating layer GI1 and a first conductive layer Gate1 can be formed on the second substrate film layer PI2 by a deposition process. The first gate insulating layer GI1 can be deposited in its entirety, and then a portion of the bending portion BED is etched away using a patterning process, so that the first gate insulating layer GI1 is located in the display portion AA and the bonding portion BOD.

[0107] like Figure 11c As shown, after the first conductive layer Gate1 is formed, a second gate insulating layer GI2 can be formed on the first conductive layer Gate1 and the first gate insulating layer GI1 by a deposition process, and a second conductive layer Gate2 can be formed on the second gate insulating layer GI2. Similarly, the portion of the second gate insulating layer GI2 located at the bend portion BED can be etched away by an etching process, and only the display portion AA and the bonding portion BOD are retained.

[0108] Furthermore, a first bridging wire GAT2-1 and a second bridging wire GAT2-2 can be formed on the second conductive layer Gate2. The first bridging wire GAT2-1 is located in the display section AA, and the second bridging wire GAT2-2 is located in the bonding section BOD. The first bridging wire GAT2-1 and the second bridging wire GAT2-2 can be connected to the corresponding adapter wire SD0-1 through vias. The first bridging wire GAT2-1 can also be connected to the first signal line SD1-1 of the third conductive layer SD1 through vias, and the second bridging wire GAT2-2 can also be connected to the second signal line SD1-2 of the third conductive layer SD1 through vias. Thus, the first signal line SD1-1 located in the display section AA and the second signal line SD1-2 located in the bonding section BOD in the third conductive layer SD1 form a conductive path through the first bridging wire GAT2-1, the second bridging wire GAT2-2, and the adapter wire SD0-1 to transmit signals between the display section AA and the bonding section BOD.

[0109] like Figure 12c As shown, after forming the second conductive layer Gate2, an interlayer insulating layer ILD can be formed on the second conductive layer Gate2 and the second gate insulating layer GI2 by a deposition process. Then, the portion of the interlayer insulating layer ILD located at the bend portion BED is etched away by an etching process, leaving only the display portion AA and the bonding portion BOD.

[0110] Then, as Figure 12c As shown, a third conductive layer SD1 is formed on the interlayer insulating layer ILD by deposition process, and corresponding signal lines are formed by patterning process. The signal lines that need to be connected to the bonding part BOD are connected to the adapter wire SD0-1 of the fourth conductive layer SD0 through vias. The adapter wire SD0-1 connects the first signal lines SD1-1 of the display part AA to the second signal lines SD1-2 corresponding to the bonding part BOD.

[0111] like Figure 13c As shown, a passivation layer PVX, a first planarization layer PLN1, and a fifth conductive layer SD2 are sequentially formed on the interlayer insulating layer (ILD) using a deposition process. The passivation layer PVX is located at the display area AA and the bonding area BOD, meaning that the passivation layer PVX is disconnected at the bend area BED. The first planarization layer PLN1 extends from the display area AA to the bonding area BOD, and the first planarization layer PLN1 covers the passivation layer PVX at the display area AA and the bonding area BOD, and covers the second substrate film layer PI2 at the bend area BED. The fifth conductive layer SD2 is located on the first planarization layer PLN1, and the signal lines in the fifth conductive layer SD2 can be connected to the corresponding signal lines in the third conductive layer SD1 through vias.

[0112] like Figure 14cAs shown, a second planarization layer PLN2 is deposited on the fifth conductive layer SD2 and the first planarization layer PLN1, and the second planarization layer PLN2 covers the fifth conductive layer SD2 and the first planarization layer PLN1.

[0113] An anode layer and a pixel defining layer (PDL) are then formed on the second planarization layer PLN2. The pixel defining layer (PDL) extends from the display portion AA to the bonding portion BOD. The pixel defining layer (PDL) has a pixel opening in the display portion AA, and the pixel opening may include an anode and an organic light-emitting layer. The portion of the pixel defining layer (PDL) located at the bending portion BED covers the second planarization layer PLN2.

[0114] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A display panel, characterized in that, It includes a display section, a bending section, and a binding section connected in sequence, wherein the binding section is bent to the non-display side of the display section via the bending section; The display panel also includes: The substrate includes: First substrate film layer; The second substrate film layer is located on one side of the first substrate film layer. The thickness of the first substrate film layer at the bend is greater than the thickness of the second substrate film layer at the bend. The thickness of the second substrate film layer at the bend is less than 10 μm, and the ratio of the thickness of the second substrate film layer at the bend to the thickness of the first substrate film layer at the bend is 0.5 to 0.

7. A fourth conductive layer is located between the first substrate film layer and the second substrate film layer, and the second substrate film layer covers the fourth conductive layer. The fourth conductive layer includes: At least one adapter cable extends from the display unit to the bonding unit; A third conductive layer is located on the side of the second substrate film layer that faces away from the first substrate film layer. The third conductive layer includes: At least one first signal line is located in the display unit; At least one second signal line is located at the bonding portion; The adapter cable is connected to the first signal line and the second signal line respectively through vias, and the fourth conductive layer is located in the stress neutral layer of the bend. The bending portion forms an arc-shaped structure after bending. The first substrate film layer is located on the side of the adapter line closer to the center of the arc-shaped structure, and the second substrate film layer is located on the side of the adapter line away from the center of the arc-shaped structure.

2. The display panel according to claim 1, characterized in that, The thickness of the second substrate film at the bend is greater than or equal to 5 μm and less than or equal to 7 μm.

3. The display panel according to claim 1, characterized in that, The thickness of the first substrate film at the bend is greater than 10 μm, and the ratio of the thickness of the first substrate film at the bend to the thickness of the second substrate film at the bend is 0.66 to 0.

78.

4. The display panel according to claim 3, characterized in that, The thickness of the first substrate film at the bend is greater than or equal to 13 μm and less than or equal to 15 μm.

5. The display panel according to any one of claims 1-4, characterized in that, The display panel also includes: A second conductive layer is located between the third conductive layer and the second substrate film layer, and the second conductive layer includes: The first bridge wire is located in the display section and is correspondingly arranged to the first signal line. The first bridge wire is connected to the adapter wire and the first signal line through vias. The second bridge wire is located in the bonding part and is correspondingly arranged with the second signal line. The second bridge wire is connected to the adapter wire and the second signal line through vias.

6. The display panel according to any one of claims 1-4, characterized in that, The display panel also includes: A first conductive layer is located between the third conductive layer and the second substrate film layer, and the first conductive layer comprises: The third bridge connection is located in the display unit, and the third bridge connection is connected to the first signal line and the adapter cable respectively through vias; The fourth bridge wire is located in the bonding part, and the fourth bridge wire is connected to the second signal line and the adapter wire through vias.

7. The display panel according to claim 1, characterized in that, The substrate further includes: A first isolation layer is located between the first substrate film layer and the fourth conductive layer, and the first isolation layer extends from the display portion to the bonding portion; The display panel further includes: a first planarization layer located between the substrate and the third conductive layer, the first planarization layer extending from the display portion to the bonding portion, and the portion of the first planarization layer located at the bending portion covering the second substrate film layer; The second planarization layer is located on the side of the first planarization layer away from the substrate. The second planarization layer extends from the display portion to the bonding portion, and the portion of the second planarization layer located at the bend portion covers the first planarization layer. A pixel defining layer is located on the side of the second planarization layer opposite to the substrate. The pixel defining layer extends from the display portion to the bonding portion. The pixel defining layer has a pixel opening in the display portion. An organic light-emitting layer is covered in the pixel opening. The portion of the pixel defining layer located at the bend covers the second planarization layer.

8. A method for manufacturing a display panel, characterized in that, The method for preparing the display panel according to any one of claims 1-7 comprises: S110. Form a first substrate film layer, wherein the first substrate film layer includes a display portion, a bending portion and a bonding portion connected in sequence; S120. A fourth conductive layer is formed on one side of the first substrate film layer, wherein the fourth conductive layer includes at least one connecting line, the connecting line extending from the display portion to the bonding portion; S130. A second substrate film is formed on the side of the fourth conductive layer away from the first substrate film layer. The thickness of the first substrate film layer at the bend is greater than the thickness of the second substrate film layer at the bend. The thickness of the second substrate film layer at the bend is less than 10 μm, and the ratio of the thickness of the second substrate film layer at the bend to the thickness of the first substrate film layer at the bend is 0.5 to 0.

7. S140. A third conductive layer is formed on the side of the second substrate film layer away from the first substrate film layer. The third conductive layer includes at least one first signal line and at least one second signal line. The first signal line is located in the display part, and the second signal line is located in the bonding part. The adapter line is connected to the corresponding first signal line and second signal line through vias, and the fourth conductive layer is located in the stress neutral layer of the bending part. The bending portion forms an arc-shaped structure after bending. The first substrate film layer is located on the side of the adapter line closer to the center of the arc-shaped structure, and the second substrate film layer is located on the side of the adapter line away from the center of the arc-shaped structure.

Images