Control circuit of power conversion device

Abstract

A control circuit of a power conversion device is a control circuit of a power conversion device that converts a first direct-current voltage into a prescribed second direct-current voltage and outputs the second direct-current voltage as an output voltage. The control circuit of the power conversion device includes a reference voltage source that generates a prescribed reference voltage, an output voltage detection circuit that has a capacitor charged with the output voltage or a voltage corresponding to the output voltage, detects a decrease in the output voltage based on a voltage of the capacitor, and outputs a detection signal, a feedback voltage output circuit that includes two voltage dividing resistors connected in series with each other with a voltage dividing ratio set in correspondence with the reference voltage and the output voltage, and outputs a feedback voltage obtained by voltage dividing the output voltage, a voltage comparison circuit that compares the reference voltage with the feedback voltage and outputs a comparison result signal indicating a comparison result, and a drive control circuit that controls intermittent operation in correspondence with the comparison result signal and the detection signal.

Description

Technical Field

[0001] This invention relates to control circuits and control methods for power conversion devices such as DC-DC converters, as well as said power conversion devices. Background Technology

[0002] One control method for DC-DC converters is VFM (Variable Frequency Modulation) control. VFM control is a method that changes the switching frequency according to the magnitude of the load current. A known technique involves reducing the frequency when the load current is low, creating a switching stop interval. By stopping the power supply to unnecessary circuits during this period, the overall current consumption of the device is reduced, improving efficiency under light loads.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent No. 6460592 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] However, in conventional VFM-controlled DC-DC converters, in order to maintain the output voltage during the switching stop interval, it is necessary to detect the drop in output voltage caused by load current. This leads to the following problems: the power supply to the reference voltage source, feedback resistor, and VFM control comparator cannot be stopped, and their current consumption results in reduced efficiency under light loads.

[0008] The purpose of this invention is to solve the above-mentioned problems and provide a control circuit and control method for a power conversion device that can stop the power supply including a reference voltage source, a feedback resistor and a VFM control comparator, which are unnecessary circuits, and improve the efficiency of the power conversion device under light loads compared with the prior art.

[0009] Methods for solving problems

[0010] The control circuit of the power conversion device according to one aspect of the present invention is a control circuit of a power conversion device that converts a first DC voltage into a predetermined second DC voltage and outputs it as an output voltage, comprising:

[0011] A reference voltage source that generates a specified reference voltage;

[0012] An output voltage detection circuit includes a capacitor charged to the output voltage or a voltage corresponding to it, and detects a decrease in the output voltage based on the voltage of the capacitor and outputs a detection signal.

[0013] The feedback voltage output circuit includes two voltage dividing resistors connected in series with each other and having a voltage division ratio set accordingly to the reference voltage and the output voltage, and outputs a feedback voltage obtained by dividing the output voltage.

[0014] A voltage comparison circuit compares the reference voltage with the feedback voltage and outputs a comparison result signal representing the comparison result; and

[0015] The drive control circuit controls the intermittent operation in accordance with the comparison result signal and the detection signal.

[0016] Invention Effects

[0017] Therefore, by using a new output voltage detection circuit utilizing a capacitor, the control circuit of the power conversion device according to the present invention can stop the power supply to unnecessary circuits, including a reference voltage source, a feedback resistor, and a VFM control comparator, thereby improving efficiency under light loads compared to the prior art. Attached Figure Description

[0018] Figure 1 This is a circuit diagram illustrating a structural example of the boost DC-DC converter 1 and its control circuit 2 according to the embodiment.

[0019] Figure 2A It means Figure 1 The circuit includes a structural example of the output voltage detection circuit 20 and an example of the operation during the switching period of stage 1.

[0020] Figure 2B It means Figure 1 The circuit structure of the output voltage detection circuit 20 and the circuit operation example during the switching stop period of stage 2.

[0021] Figure 3 It means by Figure 1 The flowchart shows the control process of the boost DC-DC converter executed by the control circuit 2.

[0022] Figure 4 It means Figure 1 Timing diagram of the operation of boost DC-DC converter 1 and control circuit 2. Detailed Implementation

[0023] Hereinafter, embodiments and variations of the present invention will be described with reference to the accompanying drawings. Furthermore, the same reference numerals will be used for the same or identical structural elements.

[0024] (The inventor's knowledge and insights)

[0025] The embodiments of this invention concerning the structure and control operation of a boost DC-DC converter during the switching stop interval have the following characteristics: Specifically, a target output voltage is pre-held in the capacitor built into the output voltage detection comparator. During the switching stop interval, this held voltage is used as a reference voltage, and the output voltage is monitored directly without voltage division via a feedback resistor. This eliminates the need for a reference voltage source and the operation of the feedback resistor, allowing for the cessation of power supply to them. Therefore, it is characterized by the ability to further improve efficiency under light load conditions.

[0026] (Implementation Method)

[0027] Figure 1 This is a circuit diagram illustrating an example of the structure of the boost DC-DC converter 1 and its control circuit 2 according to the embodiment. Figure 1 In this configuration, the boost DC-DC converter 1 is a non-isolated boost DC-DC converter, configured with a P-channel MOS transistor Q1, an N-channel transistor Q2, and a gate driver circuit 14. Furthermore, the control circuit 2 of the DC-DC converter 1 includes a reference voltage source 11, a VFM control comparator 12, a drive control circuit 13, feedback voltage divider resistors R1 and R2, a switch 15, and an output voltage detection circuit 20. Here, the feedback voltage divider resistors R1 and R2 constitute a feedback voltage output circuit.

[0028] Here, comparator 12 compares the first voltage applied to the non-inverting input terminal with the second voltage applied to the inverting input terminal. When the first voltage is greater than or equal to the second voltage, it outputs an H-level output signal Sc1 as the comparison result signal. On the other hand, when the first voltage is less than the second voltage, it outputs an L-level output signal Sc1 as the comparison result signal. The output voltage detection circuit 20 is... Figure 2A as well as Figure 2B The circuit shown in the figure uses a switched capacitor circuit that includes built-in capacitors C1 and C2. Based on the voltage of the built-in capacitors C1 and C2, which are charged to the output voltage Vout or the corresponding voltage, the decrease in the output voltage Vout is detected, and an output signal Sc2 of H level or L level representing the detection result is generated and output.

[0029] The drive control circuit 13 is composed of a predetermined control logic circuit. Based on the input output signals Sc1 and Sc2, as described later, during boost operation, it outputs a drive control signal for controlling the on / off state of MOS transistors Q1 and Q2 to the gate driver circuit 14, and outputs an ON / OFF signal Sonoff at level H, representing the ON signal for performing boost operation. On the other hand, during non-boost operation, it outputs an ON / OFF signal Sonoff at level L, representing the OFF signal for stopping boost operation. Furthermore, based on the drive control signal from the drive control circuit 13, the gate driver circuit 14 applies a predetermined gate signal to the gate of MOS transistor Q1 or Q2, thereby performing on / off control.

[0030] Typical VFM-controlled boost DC-DC converters are mainly used in applications where efficiency is critical under light loads. They typically include a reference voltage source 11, a VFM-controlled comparator 12, a drive control circuit 13 (e.g., composed of control logic circuitry), a gate driver circuit 14 that amplifies and drives the gate voltage, MOS transistors Q1 and Q2, feedback voltage divider resistors R1 and R2, and an inductor 18. Furthermore, as an additional structure in this embodiment, it includes built-in capacitors C1 and C2 (see reference). Figure 2A , Figure 2B The circuit includes an output voltage detection circuit 20 and a switch 15. Here, a series circuit of inductor 18 and MOS transistor Q1 is inserted between input terminal T1 and output terminal T2. The connection point between inductor 18 and the drain of MOS transistor Q1 is grounded via the source and drain of MOS transistor Q2. Furthermore, it is preferable to connect, for example, a smoothing capacitor (not shown) between input terminal T1 and ground, and between output terminal T2 and ground.

[0031] First, the operation of a typical VFM-controlled boost DC-DC converter is explained below.

[0032] A DC-DC converter is an example of a voltage regulator that outputs a constant output voltage Vout even when the input voltage Vin and load current vary. Specifically, a boost DC-DC converter 1 is used when the output voltage is higher than the input voltage. As a prerequisite, switch 15 is set to the ON state, for example, with 1.5V applied as the input voltage Vin, and a set output voltage of 3V as the output voltage Vout. Furthermore, the reference voltage Vref of the reference voltage source 11 is set to 1V, and the voltage division ratio of the feedback voltage divider resistors R1 and R2 is R1:R2 = 2:1. One-third of the output voltage is output as the feedback voltage Vfb. The DC-DC converter 1 performs feedback control so that the reference voltage Vref = the feedback voltage Vfb. Thus, the reference voltage Vref × 3 = 3V becomes the set value of the output voltage. Here, as the initial state, MOS transistors Q1 and Q2 are set to the OFF state.

[0033] First, when the load of the load device or other device connected to the output terminal T2 of the output voltage Vout increases and the output voltage Vout decreases, the feedback voltage Vfb obtained by the voltage divider resistors R1 and R2 also decreases. For example, when the output voltage Vout decreases from 3V to 2.7V, the feedback voltage Vfb becomes 0.9V. At this time, the VFM control comparator 12 compares the feedback voltage Vfb = 0.9V with the reference voltage Vref = 1V, and finds that Vfb < Vref, determining that the output voltage Vout has decreased, and inverts the output signal Sc1 of the VFM control comparator 12 from H level to L level. Next, the drive control circuit 13 receives the inverted L level output signal Sc1 and begins the boost operation from the input voltage Vin to the output voltage Vout. Here, there are mainly three operation stages P1 to P3.

[0034] In stage P1, the MOS transistor Q2 is turned on by the gate signal from the gate driver circuit 14. At this time, with the input voltage Vin, current flows through the inductor 18 and the MOS transistor Q2 toward ground (GND), thereby generating a magnetic field in the inductor 18 and charging it.

[0035] In stage P2, the gate signal from the gate driver circuit 14 turns off MOS transistor Q2 and turns on MOS transistor Q1. At this time, a back electromotive force is generated in the inductor 18, and current flows from the input terminal T1 of the input voltage Vin to the output terminal T2 of the output voltage Vout through MOS transistor Q1, thereby increasing the reduced output voltage.

[0036] As stage P3, when the current based on the back electromotive force no longer flows, MOS transistor Q1 is turned off.

[0037] The drive control circuit 13 repeatedly performs the above actions. When the output voltage Vout rises above the desired 3V, the feedback voltage Vfb becomes above the reference voltage Vref, and the signal of the VFM control comparator 12 reverses again, the drive control circuit 13 stops the boost operation.

[0038] Generally, when the boost operation is stopped, the drive control circuit 13 outputs an L-level ON / OFF signal (Sonoff) representing an OFF signal for unnecessary circuit blocks, thereby suppressing the current consumption of the boost DC-DC converter and improving efficiency under light load. However, it is impossible to stop the operation of the reference voltage source 11, the VFM control comparator 12, and the feedback voltage divider resistors R1 and R2 used to detect the decrease in output voltage Vout.

[0039] In this embodiment, the characteristic is that when the boost operation stops, the operation of the output voltage detection circuit 20 is stopped, and the switch 15, on which the feedback voltage divider resistors R1 and R2 are set, is opened. Specifically, the configuration is as follows: after the boost operation stops and a certain period of time has elapsed, the drive control circuit 13 also outputs an L-level ON / OFF signal Sonoff, representing an OFF signal, to the reference voltage source 11, the VFM control comparator 12, and the switch 15. The output voltage detection circuit 20 detects the decrease in the output voltage Vout.

[0040] Figure 2A It means Figure 1 The circuit includes an example of the structure of the output voltage detection circuit 20 and an example of its operation during the switching period of stage 1. Furthermore, Figure 2B It means Figure 1 The circuit structure of the output voltage detection circuit 20 and the circuit operation example during the switching stop period of stage 2.

[0041] First, refer to the following Figure 2A as well as Figure 2B The structure of the output voltage detection circuit 20 will be explained.

[0042] The output voltage detection circuit 20 is a circuit using a switched capacitor circuit, configured to include DC voltage sources 21 and 22, a comparator 23, a buffer circuit 24 consisting of two inverters 31 and 32 connected in series, built-in capacitors C1 and C2, switches SW1 to SW4, and a control circuit 30. Here, switches SW1 to SW4 are, for example, composed of MOS transistors.

[0043] exist Figure 2A as well as Figure 2BIn this circuit, the output voltage detection circuit 20 is configured to include DC voltage sources 21 and 22, a comparator 23, a control circuit 30, a buffer circuit 24 composed of inverters 31 and 32, and built-in capacitors C1 and C2 as switched capacitors. The DC voltage source 21 has a voltage V LS DC voltage source 22 has a voltage V DRP .

[0044] The output voltage Vout is connected to the positive terminal of DC voltage source 21 and one end of the built-in capacitor C1. The negative terminal of DC voltage source 21 is connected to the other end of the built-in capacitor C1 and the non-inverting input terminal of comparator 23 via switch SW1. The positive terminal of DC voltage source 22 is connected to one end of switch SW4 and one end of the built-in capacitor C2 via switch SW2. The negative terminal of DC voltage source 22 and the other end of switch SW4 are grounded. The other end of the built-in capacitor C2 is connected to the inverting input terminal of comparator 23 and to the output terminal of comparator 23 via switch SW3. The output signal from the output terminal of comparator 23 is output as output signal Sc2 via buffer circuit 24.

[0045] Control circuit 30 generates inversely related control signals SS1 and SS2 to control the operation of the switched capacitor circuit. During the switching period of phase 1, control circuit 30 outputs the H-level control signal SS1 to switches SW1-SW3 to turn them on, and outputs the L-level control signal SS2 to switch SW4 to turn it off. Similarly, during the switching period of phase 2, control circuit 30 outputs the L-level control signal SS1 to switches SW1-SW3 to turn them off, and outputs the H-level control signal SS2 to turn it on. The switching period and the switching stop period alternate repeatedly.

[0046] In the output voltage detection circuit 20 configured as described above, Figure 2A During the switching period of phase 1, switches SW1 to SW3 are turned on, and switch SW4 is turned off. Here, the output voltage Vout is set to VOUT1. By feeding back the output signal of comparator 23 to the inverting input terminal via switch SW3, the two input terminals of comparator 23 become at the same potential. Correspondingly, the two built-in capacitors C1 and C2 are charged in a stable state. Figure 2A The voltage shown indicates that the built-in capacitor C1 is charged to a voltage V. LS The built-in capacitor C2 is charged to a voltage (VOUT1-V). LS -V DRP ).

[0047] Next, in Figure 2B During the switching stop period in phase 2, switches SW1 to SW3 are open, and switch SW4 is closed. Here, if we assume the output voltage Vout = VOUT2, and focus on the potentials at the two input terminals of comparator 23, then when it becomes the following equation:

[0048] [Number 1]

[0049] VOUT2-V LS <VOUT1-V LS -V DRP

[0050] Right now,

[0051] [Number 2]

[0052] VOUT2 < VOUT1 - V DRP

[0053] The output signal of comparator 23 is logically inverted. That is, the output voltage Vout decreases from the voltage VOUT1 during the switching period. DRP The moment reversed.

[0054] As explained above, in stage 2 of the output voltage detection circuit 20, the output voltage Vout decreases from the output voltage Vout = VOUT1 in stage 1 by a voltage V DRP At this time, the output signal of comparator 23 is inverted. Here, the voltage V is... LS The reason for the level shift in the output voltage of comparator 23 is that comparator 23 is easy to design by setting the non-inverting input level of comparator 23 to an arbitrary value. Furthermore, voltage V is not required in stage 2. DRP and voltage V LS To reduce current consumption, it is preferable to disconnect the power supply of DC voltage sources 21 and 22 to provide the reference voltage output.

[0055] In the output voltage detection circuit 20, the output voltage Vout is applied to the built-in capacitor C1, which is pre-charged. The voltage Vc1 across C1 is applied to the non-inverting input terminal of comparator 23 to detect a decrease in the output voltage Vout. That is, the built-in capacitor C2 is pre-charged to the desired output voltage Vout, for example, 3V, and this voltage is applied to the inverting input terminal of comparator 23 as its reference voltage. Therefore, the reference voltage source 11 is not required, and its operation can be stopped. On the other hand, by directly comparing the output voltage Vout, the voltage divider resistors R1 and R2 used for feedback are no longer needed, thus allowing switch 15 to be turned off. As a result, their current consumption can be suppressed, further improving efficiency under light loads.

[0056] Figure 3 It means by Figure 1 The flowchart illustrates the control process of the boost DC-DC converter executed by the control circuit 2. Here, for ease of explanation, the VFM-controlled boost DC-DC converter 1 is assumed to be in the initial state, where startup is complete and the output voltage has reached the set voltage. Furthermore, it is assumed that in the preprocessing step S1, the ON / OFF signal Sonoff, representing the H level of the ON signal, is output.

[0057] exist Figure 3 First, when the output voltage Vout decreases due to the load device connected to the output terminal T2, the feedback voltage Vfb, obtained by dividing the output voltage Vout by the feedback voltage divider resistors R1 and R2, also decreases. If the feedback voltage Vfb is lower than the reference voltage Vref (step S1: Yes), the MOS transistors Q2 and Q1 are turned on / off, and the boost operation begins (step S2). Next, when the output voltage Vout rises due to the boost operation, and the feedback voltage Vfb becomes higher than the reference voltage Vref (step S3: Yes), the boost operation stops (step 45).

[0058] Furthermore, if, after the boost voltage stops, the feedback voltage Vfb remains above the reference voltage Vref for a specified time (e.g., approximately 5 to 10 seconds), and it is determined to be a light load (step S5: Yes), then for the reference voltage source 11, VFM control comparator 12, switch 15, and other unnecessary circuit blocks, an L-level ON / OFF signal Sonoff (step S6) representing an OFF signal is output, and the process proceeds to step S7. On the other hand, if the result in step S5 is no, the process returns to step S1.

[0059] In step S7, if the output voltage Vout is detected by the output voltage detection circuit 20 as being less than the built-in capacitor Vc1 (step S7: Yes), the ON / OFF signal Sonoff (step S8) of the H level ON signal of each of the above-mentioned output blocks is returned to step S1. Thus, when the output voltage Vout has decreased, the operation of the reference voltage source 11 and the feedback voltage divider resistors R1 and R2 can be started and the voltage regulation operation can be restarted.

[0060] As explained above, by stopping the operation of the reference voltage source 11 or the feedback voltage divider resistors R1 and R2, which are not required circuit blocks, during the time when the boost operation stops, current consumption can be suppressed and efficiency under light load can be improved.

[0061] Figure 4 It means Figure 1 A timing diagram showing the operation of the boost DC-DC converter 1 and the control circuit 2. Figure 4In the diagram, the periods from t1 to t2 and from t3 to t4 are the switching periods T1, and the periods from t3 to t4 and from t5 to t6 are the switching stopping periods T2.

[0062] exist Figure 4 During the switching period T1, when the feedback voltage Vfb < the reference voltage Vref, the DC-DC converter 1 performs a switching operation, and the output voltage Vout rises (Vout1). At this time, the built-in capacitor C1 of the output voltage detection circuit 20 is charged, and the voltage of this capacitor Vc1 becomes the output voltage Vout or its corresponding voltage (nearby voltage) (Vc11). Furthermore, the switching operation (boost operation) continues until the feedback voltage Vfb ≥ the reference voltage Vref, and the output signal Sc1 of the VFM control comparator 12 reverses to the L level. During this period, the ON / OFF signal Sonoff output from the drive control circuit 13 is at the H level representing the ON signal, and the feedback voltage divider resistors R1 and R2, the reference voltage source 11, and the VFM control comparator 12 are in the active state (on state) (Sonoff1).

[0063] Next, if the feedback voltage Vfb ≥ the reference voltage Vref, the output signal Sc1 of the VFM control comparator 12 inverts to H level, and the DC-DC converter 1 stops switching (during switching stop T2). At this time, the output voltage Vout gradually decreases due to the load current. Its slope depends on the capacitance value connected to the output terminal T2 and the magnitude of the load current (Vout2). When the output signal Sc1 of the VFM control comparator 12 inverts to L level, the reference voltage Vref decreases due to hysteresis. However, this is one example, and there may also be cases without hysteresis. The built-in capacitors C1 and C2 of the output voltage detection circuit 20 stop charging, maintaining the reference voltage used to detect the decrease in output voltage. Although the voltage Vc1 of the built-in capacitor C1 gradually decreases due to leakage current, etc., it falls within a range that will not cause problems for detecting the decrease in output voltage (Vc12).

[0064] Furthermore, the cessation of charging of the built-in capacitors C1 and C2 and the start of the holding operation can also be performed when the OFF signal is output, as shown later. That is, the "OFF determination period" continues until the feedback voltage Vfb ≥ the reference voltage Vref, i.e., the output signal Sc1 of the VFM control comparator 12 does not reverse back to the L level again. Figure 4 In cases where T3 or higher, the drive control circuit 13 outputs an L-level ON / OFF signal, Sonoff, representing an OFF signal. This signal stops the operation of the comparator 12, which is controlled by the feedback voltage divider resistors R1 and R2, the reference voltage source 11, and VFM; only the output voltage detection circuit 20 operates. Therefore, the current consumption becomes very small. Figure 3(Sonoff2). In addition, if the output voltage Vout drops to the specified voltage value, the output signal Sc2 of the output voltage detection circuit 20 is reversed to H level, and an ON / OFF signal Sonoff of H level representing the ON signal is output to each circuit block, and the switching operation is started again.

[0065] As explained above, during the period when the boosting action has stopped ( Figure 4 During the switching stop period (T2), the operation of unnecessary circuit blocks such as the reference voltage source 11 or feedback voltage divider resistors R1 and R2 is stopped, which can suppress current consumption and improve efficiency under light load.

[0066] (Modified Example)

[0067] In the above embodiments, during the period when the boosting operation has stopped ( Figure 4 During the switching off period T2), an L-level ON / OFF signal Sonoff is output to stop the operation of unnecessary circuit blocks such as the reference voltage source 11, the VFM control comparator 12, and the feedback voltage divider resistors R1 and R2. This invention is not limited to this; it may also output an L-level ON / OFF signal Sonoff to stop the operation of one of the circuit blocks among the reference voltage source 11, the VFM control comparator 12, and the feedback voltage divider resistors R1 and R2.

[0068] (Differences from Patent Document 1)

[0069] Patent Document 1 discloses a method for improving power efficiency by maintaining a fixed potential in the capacitor while the timer is off, thereby stopping the bandgap reference, reference bias circuit, and reference voltage generation circuit. While similar to the embodiment described in this invention in that maintaining the capacitor voltage to stop the bandgap reference circuit or reference voltage source improves power efficiency, as described above, it fails to stop the feedback resistor, resulting in current consumption and thus failing to address the problem of still low power efficiency.

[0070] Based on the structure of a typical VFM-controlled DC-DC converter, a new output voltage detection circuit 20 with built-in capacitors C1 and C2 is provided. Here, during the switching period T1, the built-in capacitor C1 is biased to a target output voltage during switching operation, and maintained at a predetermined voltage value during the switching stop period T2. During the switching stop period T2, a decrease in the output voltage Vout can be detected using the maintained target output voltage as a reference voltage. Furthermore, since the monitoring of the output voltage Vout uses the target output voltage as a reference voltage, it can be done without the feedback voltage divider resistors R1 and R2. Therefore, the operation of the reference voltage source 11 and the feedback voltage divider resistors R1 and R2 can be stopped without the need for their operation. Thus, by using the new output voltage detection circuit 20 with built-in capacitors C1 and C2, not only the operation of the reference voltage source 11 but also the operation of the feedback voltage divider resistors R1 and R2 can be stopped, further improving efficiency under light loads compared to the prior art.

[0071] Industrial availability

[0072] As detailed above, the control circuit of the power conversion device according to the present invention, etc., by using a new output voltage detection circuit utilizing a capacitor, can stop the power supply to unnecessary circuits including a reference voltage source, a feedback voltage divider resistor, and a VFM control comparator, thereby improving efficiency under light loads compared to the prior art.

[0073] Label Explanation

[0074] 1. Boost DC-DC converter

[0075] 2. Control Circuit

[0076] 11. Reference Voltage Source

[0077] 12 VFM Control Comparator

[0078] 13 Drive control circuit

[0079] 14 Gate driver circuit

[0080] 15 Switches

[0081] 20 Output Voltage Detection Circuit

[0082] 21, 22 DC voltage sources

[0083] 23 Comparator

[0084] 24 Buffer Circuit

[0085] 30 Control Circuit

[0086] Inverters 31 and 32

[0087] C1, C2 built-in capacitors

[0088] Q1 and Q2 MOS transistors

[0089] R1 and R2 are voltage divider resistors used for feedback.

[0090] SW1~SW4 switches

[0091] T1 Input Terminal

[0092] T2 output terminal

Claims

1. A control circuit for a power conversion device, comprising: converting a first DC voltage into a predetermined second DC voltage and outputting it as an output voltage; and comprising: A reference voltage source that generates a specified reference voltage; An output voltage detection circuit includes a capacitor charged to the output voltage or a voltage corresponding to it, and detects a decrease in the output voltage based on the voltage of the capacitor and outputs a detection signal. The feedback voltage output circuit includes two voltage dividing resistors connected in series with each other and having a voltage division ratio set accordingly to the reference voltage and the output voltage, and outputs a feedback voltage obtained by dividing the output voltage. A voltage comparison circuit compares the reference voltage with the feedback voltage and outputs a comparison result signal representing the comparison result. as well as The drive control circuit controls intermittent operation in accordance with the comparison result signal and the detection signal of the output voltage detection circuit. Based on the comparison result signal, the drive control circuit stops the operation of one of the reference voltage source, the feedback voltage output circuit, and the voltage comparison circuit when the feedback voltage has been above the reference voltage for a specified time.

2. The control circuit of the power conversion device as described in claim 1, Based on the detection signal, the drive control circuit restarts the operation of the reference voltage source, the feedback voltage output circuit, and the voltage comparison circuit.

3. A power conversion device that converts a first DC voltage into a predetermined second DC voltage and outputs it as an output voltage. The power conversion device includes a control circuit. The control circuit includes: A reference voltage source that generates a specified reference voltage; An output voltage detection circuit includes a capacitor charged to the output voltage or a voltage corresponding to it, and detects a decrease in the output voltage based on the voltage of the capacitor and outputs a detection signal. The feedback voltage output circuit includes two voltage dividing resistors connected in series with each other and having a voltage division ratio set accordingly to the reference voltage and the output voltage, and outputs a feedback voltage obtained by dividing the output voltage. A voltage comparison circuit compares the reference voltage with the feedback voltage and outputs a comparison result signal representing the comparison result. as well as The drive control circuit controls intermittent operation in accordance with the comparison result signal and the detection signal of the output voltage detection circuit. The power conversion device is a boost DC-DC converter. Based on the comparison result signal, the drive control circuit stops the operation of one of the reference voltage source, the feedback voltage output circuit, and the voltage comparison circuit when the feedback voltage has been above the reference voltage for a specified time.

4. A control method for a power conversion device, comprising the following steps: (The method describes a power conversion device that converts a first DC voltage into a predetermined second DC voltage and outputs it as an output voltage.) The reference voltage source generates a specified reference voltage; The system has a capacitor that is charged to the output voltage or a voltage corresponding to it, and detects a decrease in the output voltage based on the voltage of the capacitor and outputs a detection signal. The feedback voltage output circuit uses two voltage divider resistors connected in series with each other and having a voltage division ratio set accordingly to the reference voltage and the output voltage, to output a feedback voltage obtained by dividing the output voltage; The voltage comparison circuit compares the reference voltage with the feedback voltage and outputs a comparison result signal representing the comparison result. as well as Intermittent control is performed in accordance with the comparison result signal and the detection signal. Based on the comparison result signal, when the feedback voltage has been above the reference voltage for a specified time, the operation of one of the reference voltage source, the feedback voltage output circuit, and the voltage comparison circuit is stopped.

5. The control method for the power conversion device as described in claim 4 further comprises the following steps: Based on the detection signal, the operation of the reference voltage source, the feedback voltage output circuit, and the voltage comparison circuit is restarted.

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