Command scheduling component for memory

Abstract

This application relates to command scheduling components for memory. A system includes a processing device that determines whether a bank is active and adds an activate command for a row of the bank accessed by an oldest command of the bank to a command scheduler in response to determining that the bank is not active. The processing device determines whether the row of the bank has a corresponding row command in response to determining that the bank is active. The processing device determines whether a close page mode is enabled on the row or whether an open row timer has expired and adds a precharge command to the command scheduler in response to determining that the close page mode is enabled or that the open row timer has expired. The processing device executes commands in the command scheduler based on a priority of commands included in the command scheduler.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to command scheduling components for memory. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] On one hand, this application relates to a system comprising: a memory component having a plurality of memory banks; and a processing means operatively coupled to the plurality of memory components, the processing means being configured to: determine whether a memory bank among the plurality of memory banks is active, wherein in response to determining that the memory bank is not active, an activation command for accessing a row of the memory bank by the oldest command of the memory bank is added to a command scheduler; and in response to determining that the memory bank is active, determine whether the row of the memory bank has a corresponding row command, wherein in response to determining that a row command corresponding to the row of the memory bank exists, the oldest row corresponding to the row of the memory bank is added to the command scheduler. A command is added to the command scheduler; it is determined whether a closed page mode is enabled or an open row timer has expired on the row of the memory, wherein a precharge command is added to the command scheduler in response to determining that the closed page mode is enabled or the open row timer has expired on the row of the memory; and after it has been determined whether the memory is active, whether the row of the memory has a corresponding row command, and whether the closed page mode is enabled or the open row timer has expired, and in response to determining that the command is executable, the command in the command scheduler is executed based on the priority of the commands contained in the command scheduler.

[0004] On the other hand, this application relates to a method comprising: determining whether a memory bank is active, wherein in response to determining that the memory bank is not active, an activation command for a row of the memory bank accessed by the oldest command of the memory bank is added to a command scheduler; in response to determining that the memory bank is active, determining whether the row of the memory bank has a corresponding row command, wherein in response to determining that there is a row command corresponding to the row of the memory bank, the oldest row command corresponding to the row of the memory bank is added to the command scheduler; determining whether a closed page mode is enabled or an open row timer has expired on the row of the memory bank, wherein in response to determining that the closed page mode is enabled or the open row timer has expired on the row of the memory bank, a precharge command is added to the command scheduler; and after determining whether the memory bank is active, whether the row of the memory bank has a corresponding row command, and whether the closed page mode is enabled or the open row timer has expired, and in response to determining that the command is executable, executing a command in the command scheduler based on the priority of commands contained in the command scheduler.

[0005] On the other hand, this application relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform the following operations: determining whether a storage bank is active; determining whether the storage bank has a corresponding read command in response to determining that the storage bank is not active; determining whether a row in the storage bank has a corresponding row command in response to determining that the storage bank is active; determining whether the active storage bank has a corresponding read command in response to determining that the active storage bank has a corresponding row command, wherein: in response to determining that the active storage bank does not have a corresponding read command, the oldest row command of the row in the active storage bank is added to a command scheduler; and in response to determining that the active storage bank does not have a corresponding read command, the oldest row command of the row in the active storage bank is added to a command scheduler; and in response to determining that the active storage bank has ... oldest row command of the row in the active storage bank has a corresponding read command, the The active memory has a corresponding read command, and the oldest read command is determined to correspond to the active row of the active memory, wherein: in response to determining that the oldest read command corresponds to the active row of the active memory, the oldest row command of the row of the active memory is added to the command scheduler; and in response to determining that the oldest read command does not correspond to the active row of the active memory, a precharge command is added to the command scheduler; it is determined whether the page close mode is enabled on the row of the active memory or whether the open row timer has expired on the row of the active memory; and in response to determining that the row command is executable, the row command is executed based on the command priority. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of an instance method for scheduling commands to be executed according to some embodiments of the present disclosure.

[0009] Figure 3 This is a block diagram of an instance command scheduling component according to several embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of an instance method for scheduling commands to be executed according to some embodiments of the present disclosure.

[0011] Figure 5 A block diagram illustrating an example command scheduling component according to several embodiments of the present disclosure.

[0012] Figure 6 This is a flowchart of an instance method for scheduling commands to be executed according to some embodiments of the present disclosure.

[0013] Figure 7 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0014] This disclosure relates to a command scheduling component for a memory, and more particularly, to a memory subsystem comprising the command scheduling component. The memory subsystem may be a memory system, a memory device, a memory module, or a combination thereof. The following is in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] The memory subsystem can receive and execute multiple commands. A scheduling strategy can be used by the memory subsystem to determine the order in which commands are executed. For example, the command scheduling component of the memory subsystem can iterate through each unprocessed command, consider its executableness, assign it a priority, and execute the command with the highest priority.

[0016] However, iterating through each command received by the memory subsystem and assigning it a priority can degrade the memory subsystem's performance. The performance degradation may occur because time and / or processing power that would otherwise be used to perform other functions of the memory subsystem are instead devoted to iterating through commands.

[0017] This disclosure addresses the above and other deficiencies by incorporating a memory subsystem that includes a command scheduling component that iteratively processes fewer commands than the total number of commands received by the memory subsystem to schedule commands for execution. By iteratively processing fewer commands than the total number of received commands, the memory subsystem can reduce the amount of time spent iterating through commands and scheduling commands for execution. Iteratively processing fewer commands than the total number of received commands also reduces the amount of processing power spent iterating through commands and assigning them priorities. The time and processing power saved by iterating through fewer commands than the total number of commands received by the memory subsystem can be used to perform other functions. This improves the performance of the memory subsystem.

[0018] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0019] The memory subsystem 110 may be a memory device, a memory module, or a hybrid of a memory device and a memory module. Examples of memory devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other vehicle), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or the computing device containing memory and processing device.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120, for example, uses the memory subsystem 110 to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes, for example, electrical, optical, magnetic connections.

[0022] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120, for example, uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0023] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. Host system 120 may further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130) when memory subsystem 110 is coupled to host system 120 via a PCIe interface. The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0024] The memory device may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be (but is not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell (e.g., a single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages that can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] Although described as a non-volatile memory component such as NAND flash memory, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory allows for in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells.

[0027] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The memory subsystem controller 115 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, discard item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical block addresses and physical block addresses associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) capable of receiving addresses from the memory subsystem controller 115 and decoding the addresses to access the memory devices 130 and / or 140.

[0032] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] The memory subsystem 110 includes a command scheduling component 113, which can schedule fewer commands than the total number of commands received by the memory subsystem 110 for execution. In some embodiments, the memory subsystem controller 115 includes at least a portion of the command scheduling component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the command scheduling component 113 is part of the host system 110, an application program, or an operating system.

[0034] Command scheduling component 113 can place commands received by memory subsystem 110 into an execution list based on the command type and the state of the line in which the command will be executed. Once a command is placed in the execution list, command scheduling component 113 can schedule the execution of the command based on the command's priority. The command priority can be determined by several factors, including (but not limited to) the scheduling policy used in the command scheduling component, the command type, and the command's expiration date. This allows command scheduling component 113 to iterate through the commands added to the execution list, rather than assigning priority to each command received by memory subsystem 110. Further details regarding the operation of command scheduling component 113 are described below.

[0035] Figure 2 This is a flowchart of an example method 258 for scheduling commands for execution according to some embodiments of the present disclosure. Method 258 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 258 is performed by… Figure 1The command scheduling component 113 executes the commands. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0036] At operation 260, the processing device may determine whether the memory bank is active, and in response to determining that the memory bank is not active, may add an activation command for the row of the memory bank accessed by the oldest command of the memory bank to the command scheduler. After the command scheduler receives the column command, it may add the column command to the command list. For example, the memory bank may be one of a plurality of memory banks included in the memory device 130.

[0037] At operation 262, the processing device may determine whether a row in the memory has a corresponding row command in response to determining that the memory is active, and may add the oldest row command corresponding to a row in the memory to the command scheduler in response to determining that a row command corresponding to a row in the memory exists. After the command scheduler receives the row command, it may add the row command to the command queue.

[0038] In operation 264, the processing apparatus may determine whether a closed paging mode is enabled or an open row timer has expired on a row of the memory bank, and may add a precharge command to the command scheduler in response to determining that a closed paging mode is enabled or an open row timer has expired on a row of the memory bank. After adding the activation command to the command scheduler, the precharge command may be added to the command queue.

[0039] At operation 266, after determining whether the memory bank is active, whether the rows of the memory bank have corresponding row commands, and whether closed page mode is enabled or open row timers have expired, and in response to determining that a command is executable, commands in the command scheduler are executed based on the priority of commands contained in the command scheduler. In some embodiments, a scheduling candidate list may be formed in the command scheduler. The scheduling candidate list may contain commands added to the command scheduler.

[0040] The processing device can execute commands in the scheduling candidate list based on command priority. The priority of a setup command may include prioritizing the execution of the oldest command in the scheduling candidate list over the execution of another command in the scheduling candidate list. The priority of a setup command may also include prioritizing the execution of a command in the scheduling candidate list over the execution of an activation command in the scheduling candidate list. Furthermore, the priority of a setup command may include prioritizing the execution of an activation command in the scheduling candidate list over the execution of a precharge command in the scheduling candidate list.

[0041] Figure 3 This is a block diagram of an example command scheduling component 313 according to several embodiments of the present disclosure. For example, the command scheduling component 313 may be a previously combined... Figure 1 The command scheduling component 313 is described. Command scheduling component 313 includes a command scheduler 301, a scheduling candidate list 303, a command list component 305, and a command queue component 311. Command scheduling component 313 may also include multiple input / output (I / O) lines 321-1, 321-2, ..., 321-N (individually or collectively referred to as I / O lines 321) to transfer data between the command scheduler 301 and the command list component 305, and between the command scheduler 301 and the command queue component 311.

[0042] When the memory subsystem (e.g., Figure 1 When the memory subsystem 110 receives a command, the command scheduling component 313 can determine whether to add the command to the scheduling candidate list 303. For example, if... Figure 4 and Figure 6 The description further explains that commands to be added to the scheduling candidate list can be determined by the scheduling policy of the command scheduling component 313. For example, after a command is added to the command scheduler 301, the command scheduling component 313 can add the activation command, the oldest command, and the precharge command to the command list and the command queue.

[0043] Command list component 305 may contain multiple command lists 307-1, 307-2, ..., 307-N (individually or collectively referred to as command list 307). For example, command list component 305 may contain a command list for each memory bank. As used herein, the term "memory bank" may refer to a portion (e.g., a subset) of a memory component in which information (e.g., data) is stored. In some embodiments, each command list 307 may contain multiple commands 309-1-1, ..., 309-1-N, 309-2-1, ..., 309-2-N, 309-N-1, ..., 309-NN (individually or collectively referred to as command 309). Entries to command list component 305 may be inserted at the end of command list component 305. Entries to command list component 305 may be removed in any order.

[0044] Command queue component 311 may include multiple command queues 312-1, 312-2, ..., 312-N (individually or collectively referred to as command queue 312). Command queue component 311 may include a command queue 314 for each row of the storage, having at least one unprocessed command 316-1-1, ..., 316-1-N, 316-2-1, ..., 316-2-N (individually or collectively referred to as command 316). In some embodiments, each command queue 314 may contain multiple commands 316. Entries may be removed in the order they entered the command queue 314 into the queue component 311. In some embodiments, command queue 314 may be sorted according to the age of the row commands 316 contained in command queue 312. Command scheduling component 313 may determine the age of the row command 316 based on the column command that will be executed after the row command 316.

[0045] Figure 4 This is a flowchart of an example method 422 for scheduling commands for execution according to some embodiments of the present disclosure. Method 422 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 422 is performed by… Figure 1 The command scheduling component 113 executes the commands. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0046] At operation 423, the processing device may wait for the start of a scheduling cycle. As used herein, the term "scheduling cycle" refers to a process that schedules at least one command for execution. The process for scheduling commands for execution may follow a scheduling policy. In some embodiments, the command scheduler may be an FR-FCFS command scheduler that follows a First-Come, First-Served (FR-FCFS) scheduling policy (e.g., Figure 3 (Command scheduler 303 in the example). The FR-FCFS scheduling strategy can be an algorithm that executes commands in the order they are received and ready for execution. For example, a command scheduler that schedules commands for execution based on the FR-FCFS scheduling strategy will execute the first command received by the command scheduler that is ready for execution before executing any subsequently received commands that are ready for execution.

[0047] At operation 425, the processing device may check the memory device (e.g., Figure 1Each bank of memory in a portion of the memory device 130. At operation 427, the processing device may determine whether a bank of memory among the plurality of banks of memory in the memory device is active. As used herein, the term "active bank" means a bank of memory that is being accessed by a command.

[0048] At operation 428, the processing device may, in response to determining that a memory bank is not active, add an activation command for the row of the memory bank accessed by the oldest command of the memory bank to the scheduling candidate list in the command scheduler. The activation command may open the row of the memory bank and allow the row of the memory bank to be accessed by subsequent commands. In some embodiments, the activation command for the row of the memory bank added to the command scheduler may be an activation command for the row of the memory bank accessed by the oldest command of the memory bank. The row will remain open until a precharge command is executed on the row of the memory bank. Once the activation command has been added to the scheduling candidate list, the processing device may again examine each memory bank in a portion of the memory device to determine whether the memory bank is active, as described with reference to operations 425 and 427.

[0049] At operation 429, the processing device may determine whether a row of the memory has a corresponding row command in response to determining that the memory is active. The row command may include an activation command and a precharge command. The activation command may open a row, and the precharge command may close a row.

[0050] At operation 431, the processing apparatus may add the oldest row command corresponding to a row in the memory bank to the scheduling candidate list of the command scheduler in response to determining that a row command corresponding to a row in the memory bank exists. In some embodiments, this can be achieved by determining which row command is in the command list (e.g., Figure 3 The oldest line command corresponding to a line in the memory is determined by the first line of the command list (305) in the memory. In some embodiments, the oldest line command corresponding to a line in the memory can be determined based on which command first enters the command queue (e.g., Figure 3 The timestamp of the command queue 311 in the memory device is used to determine the oldest command corresponding to the row of the memory bank. After adding the oldest command corresponding to the row of the memory bank to the scheduling candidate list, the processing device may again check each memory bank in a portion of the memory device to determine whether the memory bank is active, as described with reference to operations 425 and 427.

[0051] At operation 432, the processing device may, in response to determining that no row command corresponding to a row of the memory bank exists, determine whether a closed page mode is enabled or whether an open row timer has expired on a row of the memory bank. As used herein, the term "closed page mode" refers to a mode in which the memory bank is managed, wherein any open row of the memory bank is precharged immediately after access to said row. As used herein, the term "open row timer" refers to a mechanism in which a timer counts down with each clock tick of a clock cycle, and when the open row timer expires (e.g., when the open row timer reaches zero), a precharge command is issued for the open row. In response to determining that closed page mode is not enabled and the open row timer has not expired, the processing device may again examine each bank in a portion of the memory device to determine whether the bank is active, as described with reference to operations 425 and 427.

[0052] At operation 433, the processing device may add a precharge command to the command scheduler in response to determining that a closed page mode is enabled on a row of memory or that an open row timer has expired. After adding the precharge command to the command scheduler, the processing device may again examine each memory bank in a portion of the memory device to determine whether the memory bank is active, as described with reference to operations 425 and 427.

[0053] At operation 434, the processing apparatus may examine each command added to the scheduling candidate list in the command scheduler. At operation 436, the processing apparatus may determine whether a command in the command scheduler is executable. If the processing apparatus determines that a command cannot be executed, then the processing apparatus will examine the next command in the command scheduler to determine whether the command is executable, until all commands in the command scheduler have been examined.

[0054] At operation 437, after determining whether the memory bank is active, whether the rows of the memory bank have corresponding row commands, and whether closed page mode is enabled or the open row timer has expired, and in response to determining that the command is executable, the processing device may execute the command in the command scheduler based on the priority of the commands contained in the command scheduler. At operation 438, the processing device may dequeue the command from the command queue after the command has been executed. At operation 439, the processing device may remove the command from the command list after the command has been executed.

[0055] Figure 5 This illustration shows a block diagram of an example command scheduling component according to several embodiments of the present disclosure. The components of command scheduling component 513 may be similar to... Figure 3 The command scheduling component 313 is a component of the command scheduling component. For example, the command scheduler 501, the scheduling candidate list 503, the command list component 505, the command queue component 511, and the I / O line 512 can be respectively similar to Figure 3The command scheduler 301, candidate scheduling list 303, command list component 305, command queue component 311, and I / O line 312 are included.

[0056] Command scheduling component 513 can schedule commands for execution based on a FR-FCFS strategy, which prioritizes the execution of read commands over the execution of write commands. For example, with Figure 3 Corresponding to the command list component 305, the command list component 505 may include write command lists 541-1, 541-2, ..., 541-N (individually or collectively referred to as write command list 541) and read command lists 542-1, 542-2, ..., 542-N (individually or collectively referred to as read command list 542). Write command list 541 may include write commands 543-1-1, ..., 543-1-N, 543-2-1, ..., 543-2-N, 543-N-1, ..., 543-NN (individually or collectively referred to as write command 543). Read command list 542 may include read commands 544-1-1, ..., 544-1-N, 544-2-1, ..., 544-2-N, 544-N-1, ..., 544-NN (individually or collectively referred to as read command 545).

[0057] Command list component 505 may include separate write command list 541 and read command list 542, because in this embodiment, command scheduler 501 prioritizes executing read command 544 over executing write command 543. Separating read and write commands when determining which command to execute allows the command scheduler to select a command from a list containing only read commands. Command queue component 511 may include command queue 512 and line command 516, which is similar to Figure 3 Command queue 312 and line command 316 in the middle.

[0058] Command scheduling component 513 can schedule various types of memory devices (e.g., Figure 1 The components used for execution in the memory device 130. For example, in some embodiments, the command scheduling component 513 can schedule components in the memory device that do not require line commands 516 (e.g., activation commands and precharge commands) for execution. In this embodiment, the oldest read command 544 and the oldest write command 543 can each be candidates for execution.

[0059] In these embodiments, the read priority of the FRFCFS command scheduler 501 can be disabled. Furthermore, an I / O line (e.g., I / O line 521) coupling the command scheduler 501 to the command list component 505 can be added to the command scheduling component 513 to transfer the oldest command without parent dependencies from the command scheduler 501 to the command list component 505. As used herein, the term "command without parent dependencies" refers to the first command read from command list 542 and / or the first command written to command list 541. The command scheduler 501 may add each command without parent dependencies to the scheduling candidate list 503.

[0060] Furthermore, in these embodiments, the read priority of the FRFCFS command scheduler 501 can be enabled. When the read priority of the FRFCFS command scheduler is enabled, if the oldest read command 544 of the storage bank is not the oldest read command 544 of the row of the storage bank, then the oldest read command 544 of the row of the storage bank, instead of the oldest read command 544 of the storage bank, can be added to the scheduling candidate list 503.

[0061] Figure 6 This is a flowchart of an example method 646 for scheduling commands for execution according to some embodiments of the present disclosure. Method 646 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 646 is executed by… Figure 1 The command scheduling component 113 executes the commands. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0062] At operation 623, the processing device may wait for the start of a scheduling cycle. In some embodiments, the command scheduling component executing the scheduling cycle may prioritize the execution of read commands over the execution of write commands. Prioritizing the execution of read commands over write commands may cause the command scheduling component to search for read commands corresponding to rows of memory to add to the command scheduler before searching for write commands corresponding to rows of memory to add to the command scheduler.

[0063] At operation 625, the processing device may check the memory device (e.g., Figure 1Each memory bank in a portion of the memory device 130. In some embodiments, each memory bank may be checked sequentially. In some embodiments, multiple memory banks may be checked in parallel. At operation 627, the processing means may determine whether a memory bank among the multiple memory banks of the memory device is active.

[0064] At operation 648, the processing device may determine whether the memory bank has a corresponding read command (e.g., a read command to be executed on the memory bank) in response to determining that the memory bank is not active. In an FR-FCFS policy that prioritizes read commands, determining whether a read command corresponding to the memory bank exists determines which command to add to the command scheduler.

[0065] At operation 628, in response to determining that a memory bank is not active, the processing device may add an activation command for the row of the memory bank accessed by the oldest write command to the command scheduler in response to determining that the memory bank does not have a corresponding read command. At operation 650, in response to determining that a memory bank is not active, the processing device may add an activation command for the row of the memory bank accessed by the oldest read command to the command scheduler in response to determining that the memory bank has a corresponding read command. After adding the activation command for the row of the memory bank accessed by the oldest read command or the oldest write command to the command scheduler, the processing device may again check each memory bank in the portion of the memory device to determine whether the memory bank is active, as described with reference to operations 625 and 627.

[0066] At operation 629, the processing device may determine, in response to determining that the memory bank is active, whether a row in the memory bank has a corresponding row command (e.g., a command to be executed on the row). At operation 652, the processing device may determine, in response to determining that the active memory bank has a corresponding row command, whether the active memory bank has a corresponding read command. Determining whether the active memory bank has a corresponding read command determines which command to add to the command scheduler.

[0067] At operation 654, the processing device may add the oldest line command for the line of the active memory to the command scheduler in response to determining that the active memory bank does not have a corresponding read command. After adding the oldest line command for the line of the active memory bank to the command scheduler, the processing device may again examine each memory bank in the portion of the memory device to determine whether the memory bank is active, as described with reference to operations 625 and 627.

[0068] At operation 656, the processing device may determine, in response to determining that the active memory bank has a corresponding read command, whether the oldest read command corresponds to the active row of the active memory bank. At operation 654, the processing device may add the oldest row command for the active memory bank's row to the command scheduler in response to determining that the oldest read command corresponds to the active row of the active memory bank. At operation 633, the processing device may add a precharge command to the command scheduler in response to determining that the oldest read command does not correspond to the active row of the active memory bank. After adding either the oldest row command or the precharge command for the active memory bank's row to the command scheduler, the processing device may again examine each memory bank in the portion of the memory device to determine whether the memory bank is active, as described with reference to operations 625 and 627.

[0069] At operation 632, the processing device may, in response to determining at operation 629 that the active memory bank does not have a corresponding row command, determine whether page-closing mode is enabled on the row of the active memory bank or whether the open row timer on the row of the active memory bank has expired. In response to determining that page-closing mode is not enabled or the active row timer has not expired, the processing device may re-examine each memory bank in the portion of the memory device to determine whether the memory bank is active, as described with reference to operations 625 and 627. In response to determining whether page-closing mode is enabled on the row of the active memory bank or whether the open row timer on the row of the active memory bank has expired, the processing device may add a precharge command to the command scheduler, as described at operation 633. In response to adding the precharge command to the command scheduler, the processing device may re-examine each memory bank in the portion of the memory device to determine whether the memory bank is active, as described with reference to operations 625 and 627.

[0070] At operation 634, the processing device may examine each command in the command scheduler. At operation 636, the processing device may determine whether a command in the command scheduler can be executed. If the processing device determines that a command cannot be executed, then the processing device will examine the next command in the command scheduler to determine whether a command in the command scheduler can be executed, until all commands in the command scheduler have been examined.

[0071] At operation 637, in response to determining that a row command is executable, the processing apparatus may execute the row command based on command priority. In some embodiments, read commands may be executed before write commands in terms of command priority. However, if both read and write commands access the same row, and the write command arrives before the read command, then the FR-FCFS read priority may increase the priority of the write command, since the execution of the read command may be blocked by the execution of the write command. Furthermore, higher priority column commands may be executed before higher priority activation commands in terms of command priority. As used herein, the term "high priority command" refers to a read command or a command that activates a row with a corresponding read command to make the read command executable. Furthermore, higher priority activation commands may be executed before lower priority write column commands in terms of command priority. As used herein, the term "low priority command" refers to a command that is neither a read command nor a command that activates a row with a corresponding read command to make the read command executable. In some embodiments, lower priority write column commands may be executed before lower priority write activation commands in terms of command priority. Furthermore, in the command priority hierarchy, low-priority write activation commands may be executed before precharge commands. In some embodiments, commands may be prioritized based on the number of accesses to the corresponding memory bank.

[0072] At operation 638, the processing device may dequeue a command from the command queue after the command has been executed. At operation 639, the processing device may remove a command from the command list after the command has been executed.

[0073] Figure 7 This is a block diagram of an example computer system 700 in which embodiments of this disclosure may operate. For example, Figure 7 An example machine illustrating computer system 700 is described, within which a set of instructions is executable to cause said machine to perform any or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (The operation of the command scheduling component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The computer may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0074] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0075] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 718, which communicate with each other via a bus 730.

[0076] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communicating via network 720.

[0077] Data storage system 718 may include machine-readable storage medium 724 (also called computer-readable medium) on which one or more sets of instructions 726 or software embodying any or more of the methods or functions described herein are stored. During execution of instructions 726 by computer system 700, instructions 726 may also reside wholly or at least partially in main memory 704 and / or processing device 702, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0078] In one embodiment, instruction 726 includes instructions to implement the command scheduling component 713 (e.g., Figure 1The functionality of the command scheduling component 113). Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0079] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that leads to a desired result. These operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has sometimes proven convenient to refer to these signals primarily for general reasons as bits, values, elements, symbols, characters, items, numbers, or the like.

[0080] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) numbers in the registers and memories of the computer system into physical quantities similarly represented as those in the computer system's memory or registers or other such information storage systems.

[0081] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specifically configured for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will appear as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0083] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0084] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than limiting.

[0085] The diagrams in this document follow a numbering convention, where the first one or a few digits correspond to the diagram number, and the remaining digits identify the elements or components within the diagram. Similar elements or components between different diagrams can be identified using similar digits. For example, 113 can be referenced... Figure 1 The element "13" in the text, and similar elements can be referenced as Figure 3 Reference numeral 313. In this document, a group or plurality of similar elements or components may generally be referred to by a single element number. For example, multiple reference elements 307-1 to 307-N may be collectively referred to as 307. It will be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, the scale and / or relative dimensions of the elements provided in the figures are intended to illustrate various embodiments of this disclosure and should not be construed as limiting.

[0086] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of this disclosure includes other applications using the above-described structures and processes. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims and the full scope of their equivalents.

[0087] In the foregoing detailed embodiments, for the purpose of simplifying this disclosure, some features are grouped together in a single embodiment. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments of the disclosure must use more features than expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention exists in fewer than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. A system comprising: memory components having a plurality of memory banks; and a processing device operatively coupled with the plurality of memory components, the processing device to: make a first determination as to whether at least one memory bank of the plurality of memory banks is active, wherein in response to determining that the at least one memory bank is not active, an activate command for a row of the at least one memory bank accessed by an oldest command of the at least one memory bank is added to a command scheduler; in response to adding the activate command to the command scheduler, make a second determination as to whether the at least one memory bank is active, wherein the second determination is made immediately after the activate command is added to the command scheduler, wherein no scheduling actions occur between the activate command being added to the command scheduler and the second determination being made; in response to the second determination as to whether the at least one memory bank is active, determine that the at least one memory bank is active, determine whether the row of the at least one memory bank has a corresponding row command, wherein in response to determining that the at least one memory bank is active and in response to determining that there is a row command corresponding to the row of the at least one memory bank, an oldest row command corresponding to the row of the at least one memory bank is added to the command scheduler; in response to adding the oldest row command corresponding to the row of the at least one memory bank to the command scheduler, make a third determination as to whether the at least one memory bank is active, wherein: the third determination is made immediately after the oldest row command corresponding to the row of the at least one memory bank is added to the command scheduler, wherein no scheduling actions occur between the oldest row command corresponding to the row of the at least one memory bank being added to the command scheduler and the third determination being made; and in response to determining that the at least one memory bank is active, determining that the at least one memory bank does not have a row command corresponding to the row of the at least one memory bank, and determining that a close page mode is enabled on the row of the at least one memory bank or an open row timer has expired, a precharge command is added to the command scheduler; and in response to adding the precharge command to the command scheduler, determine whether any commands in the command scheduler are executable; in response to determining that the at least one memory bank is active, the row of the at least one memory bank does not have a corresponding row command, the close page mode is enabled or the open row timer has expired, and the command is executable, execute the command in the command scheduler based on a priority of the command included in the command scheduler.

2. The system of claim 1, wherein the processing device is to add the activate command, the oldest row command, and the precharge command to a command list and a command queue after the command is added to the command scheduler.

3. The system of claim 2, wherein the command queue is ordered by age of row commands included in the command queue.

4. The system of claim 2, wherein the processing device is to dequeue the command from the command queue after the command has been executed.

5. The system of claim 2, wherein the processing device is to remove the command from the command list after the command has been executed.

6. The system of claim 1, wherein the processing device is to determine the age of the row command based on a column command to be executed after the row command is executed.

7. A method comprising: making a first determination as to whether at least one bank of a plurality of banks is active, wherein in response to determining that the at least one bank is not active, adding an activate command for a row of the at least one bank accessed by an oldest command of the at least one bank to a command scheduler; in response to adding the activate command to the command scheduler, making a second determination as to whether the at least one bank is active, wherein the second determination is made immediately after adding the activate command to the command scheduler, wherein no scheduling action occurs between adding the activate command to the command scheduler and making the second determination; in response to the second determination as to whether the at least one bank is active resulting in a determination that the at least one bank is active, determining whether the row of the at least one bank has a corresponding row command, wherein in response to determining that there is a row command corresponding to the row of the at least one bank, adding a most recent row command corresponding to the row of the at least one bank to the command scheduler; in response to adding the most recent row command corresponding to the row of the at least one bank to the command scheduler, making a third determination as to whether the at least one bank is active, wherein: the third determination is made immediately after adding the most recent row command corresponding to the row of the at least one bank to the command scheduler, wherein no scheduling action occurs between adding the most recent row command corresponding to the row of the at least one bank to the command scheduler and making the third determination; and in response to determining that the at least one bank is active, determining that the at least one bank does not have a row command corresponding to the row of the at least one bank, and that either a closed page mode is enabled on the row of the at least one bank or an open row timer has expired, adding a precharge command for the at least one bank to the command scheduler; and in response to determining that the at least one bank is active, that the row of the at least one bank does not have a corresponding row command, that either the closed page mode or the open row timer is enabled has expired, and that the command is executable, executing a command in the command scheduler based on a priority of commands included in the command scheduler.

8. The method of claim 7, further comprising forming a dispatch candidate list in the command scheduler, wherein the dispatch candidate list includes commands added to the command scheduler.

9. The method of claim 8, further comprising: prioritizing execution of an oldest column command in the dispatch candidate list over execution of another column command in the dispatch candidate list; prioritizing execution of a column command in the dispatch candidate list over execution of the activate command in the dispatch candidate list; and prioritizing execution of the activate command in the dispatch candidate list over execution of the precharge command in the dispatch candidate list.

10. The method of claim 7, further comprising: after the command scheduler receives a column command, adding the column command to a command list; and after the command scheduler receives the row command, adding the row command to a command queue.

11. The method of claim 10, wherein the oldest row command corresponding to the row of the at least one memory bank is determined by determining which row command is a first row command in the command list.

12. The method of claim 10, wherein the oldest command corresponding to the row of the at least one memory bank is determined based on a timestamp indicating which command entered the command queue first.

13. The method of claim 7, wherein the activate command added to the row of the at least one memory bank of the command scheduler is an activate command for the row of the at least one memory bank accessed by an oldest command of the at least one memory bank.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: make a first determination as to whether at least one memory bank of a plurality of memory banks is active; in response to the first determination determining that the at least one memory bank of the plurality of memory banks is not active, determine whether the at least one memory bank has a corresponding read command, wherein: in response to determining that the at least one memory bank does not have the corresponding read command, and determining that the at least one memory bank is not active, add a first activate command for a row of the at least one memory bank accessed by an oldest write command to a command scheduler; and in response to determining that the at least one memory bank has the corresponding read command, and determining that the at least one memory bank is not active, add a second activate command for the row of the at least one memory bank accessed by an oldest read command to the command scheduler; in response to adding the first activate command or the second activate command to the command scheduler, make a second determination as to whether the at least one memory bank is active, wherein the second determination is made immediately after adding the first activate command or the second activate command to the command scheduler, wherein no scheduling actions occur between adding the first activate command or the second activate command to the command scheduler and making the second determination; in response to the second determination of whether the at least one bank is active, determining that the at least one bank is active and determining whether the row of the bank has a corresponding row command, wherein the corresponding row command is the first activate command, the second activate command, or a precharge command; in response to determining that the at least one active bank has a corresponding row command, determining whether the at least one active bank has a corresponding read command, wherein: in response to determining that the at least one active bank does not have a corresponding read command, adding the oldest row command of the row of the at least one active bank to the command scheduler; and in response to determining that the at least one active bank has the corresponding read command, determining whether the oldest read command of the row of the at least one active bank corresponds to an active row of the at least one active bank, wherein: in response to determining that the oldest read command corresponds to the at least one active row of the at least one active bank, adding the oldest row command of the row of the at least one active bank to the command scheduler; and in response to determining that the oldest read command does not correspond to the active row of the at least one active bank, adding a first precharge command to the command scheduler; in response to adding the oldest row command of the row of the at least one active bank to the command scheduler or adding the first precharge command to the command scheduler, making a third determination of whether the bank is active, wherein the third determination is made immediately after adding the oldest row command of the row of the at least one active bank or the first precharge command to the command scheduler, wherein no scheduling actions occur between adding the oldest row command of the at least one bank or the first precharge command to the command scheduler and making the third determination; in response to the third determination of whether the at least one bank is active resulting in a determination that the at least one bank is active and the row of the at least one active bank does not have a row command, determining that a closed page mode is enabled on the row of the at least one active bank or an open row timer has expired on the row of the at least one active bank, wherein in response to determining that the closed page mode is enabled on the row of the at least one active bank or the open row timer has expired on the row of the at least one active bank, adding a second precharge command to the command scheduler; in response to adding the second precharge command to the command scheduler, determining whether any command in the command scheduler is executable; and in response to determining that the command scheduler contains at least one executable row command, executing the row command based on a priority of commands.

15. The non-transitory computer-readable storage medium of claim 14, wherein in the priority of commands, execution of a read command is prioritized over a write command.

16. The non-transitory computer-readable storage medium of claim 14, wherein: in said priority of commands, execution of a high priority column command is prioritized over a high priority activate command; in said priority of commands, execution of a high priority activate command is prioritized over a low priority write column command; in said priority of commands, execution of a low priority write column command is prioritized over a low priority write activate command; in said priority of commands, execution of a low priority write activate command is prioritized over said pre-charge command.

17. The non-transitory computer readable storage medium of claim 14, wherein commands are prioritized in said priority of commands based on a number of accesses to a corresponding bank.

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