Semiconductor memory device and reading method

Abstract

The present invention provides a semiconductor memory device and a readout method, which can realize high-speed error detection and correction processing and achieve miniaturization. The flash memory (100) of the present invention has a NAND chip (200) and an ECC chip (300). The NAND chip (200) includes a memory array and a page buffer / sensing circuit including a latch (L1) and a latch (L2). The ECC chip (300) includes RAM_E and RAM_O. The RAM_E and RAM_O store readout data output from the latches (L1, L2) of the NAND chip (200). RAM_E stores data of even-numbered sectors, and RAM_O stores data of odd-numbered sectors. The data size of RAM_E and RAM_O can be reduced by making RAM_E or RAM_O alternately store sector data.

Description

Technical Field

[0001] The present invention relates to a semiconductor storage device such as a NAND type flash memory and a reading method thereof, and in particular to error detection and correction. Background Art

[0002] In NAND flash memory, repeated programming and erasing of data can sometimes cause degradation of the tunnel insulation film, leading to poor charge retention characteristics. Alternatively, charge trapped in the tunnel insulation film can cause threshold fluctuations, resulting in bit errors. To combat these bit errors, an error detection and correction circuit (ECC circuit) is used in flash memory. Summary of the Invention

[0003] Figure 1 This diagram shows the structure of a conventional off-chip ECC flash memory. Flash memory 10 includes a NAND chip 20, which includes a NAND memory array and its peripheral circuits. NAND chip 20 is connected to a controller chip 30 equipped with ECC functionality 40. The NAND chip 20 and controller chip 30 are housed in separate packages, each package mounted on, for example, a printed circuit board.

[0004] The NAND chip 20 and the controller chip 30 are equipped with, for example, a serial peripheral interface (SPI) capable of transmitting data synchronously with a clock signal. Input and output terminals #CS, CLK, DI, DO, #WP, and #HOLD are provided on each chip. The controller chip 30 sends commands, addresses, and data to the NAND chip 20 via the SPI input and output terminals.

[0005] The ECC function 40 includes an encoder that encodes data and generates parity data, and a decoder that decodes the data based on the parity data. For example, the ECC function 40 uses a Bose Chaudhuri Hocquenghem (BCH) code to detect and correct multi-bit errors (e.g., 2-bit, 4-bit, 8-bit, etc.). In this case, the BCH decoder includes a syndrome calculation unit that estimates the syndrome of the data; a Euclidean algorithm calculation unit that calculates the error position polynomial (ELP); an error position search unit that calculates the roots of the error position polynomial and finds the error position; and an error correction unit that corrects the error based on the found error position.

[0006] The page buffer / sensing circuit of the NAND chip 20 includes two latches, each of which contains two caches. Each cache stores data from multiple sectors (e.g., two or four sectors). Data transmission between the NAND chip 20 and the controller chip 30 is performed in cache units. Furthermore, the ECC function 40 generates parity data on a sector-by-sector basis, or performs error detection and correction. A sector encoded by the ECC function 40 contains both main data and parity data.

[0007] When the controller chip 30 causes the NAND chip 20 to perform a programming operation, it generates parity data based on the data to be programmed using the ECC function 40 and transmits the generated parity data and main data to the NAND chip 20 via the SPI DO terminal. The NAND chip 20 stores the received main data and parity data in latches and programs the data stored in the latches into a selected page of the memory array.

[0008] Meanwhile, data read from the memory array in the NAND chip 20 is transmitted via the DO terminal of the SPI to the controller chip 30. The ECC function 40 detects errors based on the parity data and corrects the main data or the parity data according to the detection result.

[0009] Figure 2 This is a timing diagram illustrating the operation of various components of the ECC function of the controller chip 30. The NAND chip 20 performs a read operation in response to a read command transmitted from the controller chip 30 and outputs the read data to the controller chip 30. At time t0, the NAND_IF of the controller chip 30 begins receiving the main data and parity data Pt of sector S0 from the NAND chip 20. At time t1, it begins receiving the main data and parity data Pt of sector S1. At times t2 and t3, it begins receiving the main data and parity data Pt of sectors S2 and S3. While receiving data from sector S1, the ECC function 40 simultaneously calculates the syndrome of the main data of sector S0, calculates the error location polynomial, and searches for the error location in a pipelined manner. Based on the found error location, it corrects errors in the main data of sector S0. The CPU_IF of the controller chip 30 then transmits the error-corrected data of sector S0 to the host device. The ECC processing of sectors S1, S2, and S3 is also pipelined, and the error-corrected data of each sector is output during sector reception.

[0010] When transferring read data from the NAND chip 20 to the controller chip 30, syndrome calculation must be performed after transferring the sector's parity data. Consequently, if the bit width of the SPI's DO terminal is narrow, data transfer takes time, and during this time, the controller chip 30 remains idle for extended periods, hindering full pipeline processing performance. Furthermore, as the density of memory arrays increases and the size of a single page increases, the area occupied by the page buffer / sensing circuitry and ECC functionality increases, leading to a larger chip. Therefore, space-saving implementation of the page buffer / sensing circuitry and ECC functionality is desired.

[0011] The semiconductor storage device of the present invention includes: a NAND chip, including a NAND-type memory array, a control unit and an output unit, wherein the control unit controls the read action of the memory array, and the output unit outputs the data read from the memory array to an ECC chip; and an ECC chip, including a first holding unit and a second holding unit, and an ECC unit, wherein the ECC unit performs error detection and correction on the data held in the first holding unit and the second holding unit. When a page contains n sectors, the output unit outputs data to the ECC chip in units of sectors, wherein the first holding unit holds data of even-numbered sectors, and the second holding unit holds data of odd-numbered sectors, and the ECC unit performs error detection and correction on the data read from the first holding unit or the second holding unit.

[0012] The reading method of the present invention is a reading method of a semiconductor storage device, wherein the semiconductor storage device includes: a NAND chip, including a NAND-type memory array, a control component and an output component, wherein the control component controls the reading action of the memory array, and the output component outputs the data read from the memory array to an ECC chip; and an ECC chip, including a first holding part and a second holding part, and an ECC component, wherein the ECC component performs error detection and correction on the data held in the first holding part and the second holding part, and the output component outputs the data to the ECC chip in units of sectors, wherein the first holding part holds data of even-numbered sectors, and the second holding part holds data of odd-numbered sectors, and the ECC component performs error detection and correction on the data read from the first holding part or the second holding part, and outputs the corrected data to the outside.

[0013] According to the present invention, by alternating between the first and second storage sections of the ECC chip to store data for even-numbered and odd-numbered sectors, the data size of the first and second storage sections can be reduced, thereby reducing the chip area of ​​the ECC chip and lowering costs. Furthermore, by providing the ECC chip separately from the NAND chip, faster error detection and correction processing can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A diagram showing a schematic structure of a conventional flash memory;

[0015] Figure 2 A timing diagram showing the operation of the ECC function of a conventional flash memory;

[0016] Figure 3 A diagram showing a schematic structure of a flash memory according to an embodiment of the present invention;

[0017] Figure 4 (A) is a diagram showing the main structure of the flash memory of this embodiment. Figure 4 (B) is a diagram showing the main structure of a flash memory as a comparative example;

[0018] Figure 5 A block diagram showing the internal structure of a NAND chip and an ECC chip according to an embodiment of the present invention;

[0019] Figure 6 A timing diagram showing an ECC operation of a flash memory according to an embodiment of the present invention;

[0020] Figure 7 A diagram showing a timing diagram of a continuous read operation of a flash memory according to a comparative example;

[0021] Figure 8 A diagram showing a timing diagram of a continuous read operation of a flash memory according to an embodiment of the present invention;

[0022] Figure 9 1 is a diagram showing a timing diagram when an interruption occurs during a continuous read operation in a flash memory of a comparative example;

[0023] Figure 10 A diagram showing a timing diagram when an interruption occurs during a continuous read operation in the flash memory of this embodiment;

[0024] Figure 11 A diagram showing a main structure of a flash memory according to a modified example of the present invention.

[0025] Explanation of symbols

[0026] 10, 100, : Flash memory

[0027] 20, 200, 200A, 200_X: NAND chips

[0028] 30, 400: controller chip

[0029] 40: ECC function

[0030] 210, 310, 330, 410: Input and output terminals for SPI

[0031] 220, 320: ECC dedicated input and output terminals

[0032] 230: Page buffer / sensing circuit

[0033] 240: Interface circuit (ECC_IF)

[0034] 250, 350: Interface circuit (CTL_IF)

[0035] 260, 370: ECC control unit

[0036] 270, 380: Controller

[0037] 280: Address control unit

[0038] 300, 300_X: ECC chips

[0039] 340: Interface circuit (NAND_IF)

[0040] 360: ECC core

[0041] C0, C1: Buffer

[0042] CK: clock signal

[0043] L1, L2: latches

[0044] OSC: Oscillator

[0045] P0, P1: page

[0046] Pt: Parity data

[0047] S0~S7: sectors

[0048] SEL1~SEL5: Selector

[0049] t0~t9: time DETAILED DESCRIPTION

[0050] Figure 3 FIG1 is a diagram schematically showing the structure of a flash memory according to the first embodiment of the present invention. The flash memory 100 of this embodiment includes a NAND chip 200 and an ECC chip 300 electrically connected to the NAND chip 200 .

[0051] Although not shown here, the NAND chip 200 typically includes a NAND-type memory array and peripheral circuits. The peripheral circuits include a row decoder, a column decoder, a page buffer / sensing circuit, an interface circuit, a controller, an internal voltage generation circuit, etc. The controller controls the reading, programming, deletion and other actions according to the input commands. The memory array includes a plurality of blocks, and a plurality of NAND strings are formed in each block. The NAND string can be formed two-dimensionally on the surface of the substrate or three-dimensionally on the surface of the substrate. The memory cell can be a single-level cell (SLC) type that stores one bit (binary data) or a type that stores multiple bits.

[0052] The NAND chip 200 includes input and output terminals 210 (#CS, CLK, DI, DO, #WP, #HOLD) for SPI and input and output terminals 220 (VALID, CK, DATA) dedicated to ECC as an interface with the ECC chip 300. "#" indicates low active. #CS is a terminal for receiving a chip select signal for enabling or disabling the chip, CLK is a terminal for receiving a serial clock signal, DI is a terminal for inputting serial data, DO is a terminal for outputting serial data, #WP is a terminal for receiving a signal for protecting the status register from being written, and #HOLD is a terminal for receiving a signal for holding the chip. The NAND chip 200 receives commands, addresses, and data in synchronization with the serial clock signal CLK via the input and output terminals 210 for SPI, or outputs data in synchronization with the serial clock signal CLK.

[0053] The ECC-dedicated input / output terminal 220 includes a VALID terminal for inputting and outputting a VALID signal, which indicates whether the data transmission between the NAND chip 200 and the ECC chip 300 is valid. The CK terminal outputs the clock signal CK used for data transmission and ECC processing. The DATA terminal inputs and outputs data between the NAND chip 200 and the ECC chip 300. It should be noted that while the bit width m (data transmission width) of the SPI-used DO / DI terminals is, for example, ×1, ×4, or ×8, the bit width n of the ECC-dedicated DATA terminal is larger than the bit width m of the SPI-used DO / DI terminals (n>m), for example, ×32. Therefore, if the frequencies of the clock signals CK and CLK are the same, the data transmission time between the NAND chip 200 and the ECC chip 300 is n / m times faster than the SPI data transmission time.

[0054] Although not shown here, the NAND chip 200 may also include an ONFi interface in addition to the SPI input / output terminals 210. The ONFi interface includes external control terminals such as Command Latch Enable (CLE), Address Latch Enable (ALE), and Write Enable (#WE), as well as input / output terminals such as I / O.

[0055] The ECC chip 300 includes SPI input / output terminals 310 (#CS, CLK, DI, DO, #WP, #HOLD) and ECC-specific input / output terminals 320 (VALID, CK, DATA) as interfaces with the NAND chip 200. The SPI input / output terminals 310 of the ECC chip 300 are electrically coupled to corresponding terminals of the SPI input / output terminals 210 of the NAND chip 200, and the ECC-specific input / output terminals 320 are electrically coupled to corresponding terminals of the ECC-specific input / output terminals 220 of the NAND chip 200.

[0056] The ECC chip 300 also includes SPI input / output terminals 330 (#CS, CLK, DI, DO, #WP, #HOLD) as an interface with the controller chip 400. The input / output terminals 330 are electrically coupled to corresponding terminals of the SPI input / output terminals 410 of the controller chip 400. Each terminal of the input / output terminals 310 (#CS, CLK, DI, DO, #WP, #HOLD) is electrically coupled to each terminal of the input / output terminals 330 (#CS, CLK, DI, DO, #WP, #HOLD) via internal wiring or the like. That is, although the input / output terminals 310 and the input / output terminals 330 are physically separated from each other in order to realize the connection between the NAND chip 200 and the controller chip 400, electrically, the input / output terminals 310 and the input / output terminals 330 are common to the NAND chip 200 and the controller chip 400. This connection is equivalent to the input / output terminals 210 for SPI of the NAND chip 200 being connected to the input / output terminals 410 for SPI of the controller chip 400.

[0057] Figure 4 (A) is a diagram showing the main structure of the flash memory of this embodiment. Figure 4(B) is a diagram showing the main structure of a flash memory as a comparative example. NAND chip 200 and NAND chip 200_X include a page buffer / sensing circuit, which holds data read from the memory array or holds data used for programming in the memory array. The page buffer / sensing circuit includes two segments of latches L1 and latch L2. Latch L1 includes buffer C0 and buffer C1, and latch L2 includes buffer C1. Buffer C1 of latch L1 and buffer C1 of latch L2 can perform bidirectional data transmission. Latch L1 holds one page of data (for example, 4KB), buffers C0 and buffers C1 hold 1 / 2 page of data (for example, 2KB), buffer C0 holds data of four sectors, namely, sector S0 to sector S3 (for example, one sector is 512 bytes), and buffer C1 holds data of four sectors, namely, sector S4 to sector S7.

[0058] In the comparative example, when NAND chip 200_X performs a continuous page read operation, the page data read from the memory array is held in buffers C0 and C1 of latch L1. The data held in buffer C1 of latch L1 is transferred to buffer C1 of latch L2. NAND chip 200_X then transfers the data for sectors S0 through S3 held in buffer C0 of latch L1 to ECC chip 300_X. The data for sectors S4 through S7 held in buffer C1 of latch L2 is then transferred to ECC chip 300_X. Data transfer from NAND chip 200_X to ECC chip 300_X is performed in buffer units (four sectors). When data transfer for one half page is complete, NAND chip 300_X transfers the next half page of data.

[0059] ECC chip 300_X includes two-segment random access memories (RAM1 and RAM2) for storing data transferred from NAND chip 200_X. RAM1 and RAM2 each hold half a page of data (e.g., 2KB). RAM1 stores data from sectors S0 through S3 read from latch L1, while RAM2 stores data from sectors S4 through S7 read from latch L2. While receiving data from NAND chip 200_X, ECC chip 300_X performs error detection and correction on a sector-by-sector basis.

[0060] Meanwhile, in this embodiment, the page buffer / sensing circuit of NAND chip 200 includes latches L1 and L2 configured similarly to the comparative example. However, ECC chip 300 includes RAM_E and RAM_O, which have half the data size of RAM0 and RAM1 in the comparative example. In other words, RAM_E and RAM_O can store 1 / 4 of a page's worth of data, or two sectors' worth of data.

[0061] The NAND chip 200 controls data transfer on a sector-by-sector basis. First, it transfers half a page of data from sectors S0 to S3, held in buffer C0 of latch L1, to the ECC chip 300. In response to this transfer, the ECC chip 300 stores even-numbered sectors S0 and S2 in RAM_E and odd-numbered sectors S1 and S3 in RAM_O. Before beginning to transfer the next half page of data from sectors S4 to S7, the ECC chip 300 performs error detection and correction on the data from sectors S0 to S3 stored in RAM_E and RAM_O. The NAND chip 200 then transfers half a page of data from sectors S4 to S7, held in buffer C1 of latch L2, to the ECC chip 300. The ECC chip 300 then stores even-numbered sectors S4 and S6 in RAM_E and odd-numbered sectors S5 and S7 in RAM_O.

[0062] In response to the ECC chip 300 outputting the data at the beginning of sector S0 to the controller chip 400, the NAND chip reads the next page from the memory array and stores the read data in latch L1. At the time the data at the beginning of sector S0 is output to the controller chip 400, the data in buffer C1 of latch L1 is transferred to latch L2, allowing the next page of data to be overwritten in latch L1.

[0063] In this embodiment, the data size (storage capacity) of RAM_E and RAM_O in the ECC chip 300 can be reduced, thereby reducing the chip area and cost of the ECC chip 300. Furthermore, by transferring data from the NAND chip 200 to the ECC chip 300 via a dedicated port, the output of read data can be accelerated.

[0064] Figure 5 3 is a block diagram showing the internal structure of the NAND chip 200 and the ECC chip 300. However, it should be noted that only the structure related to the ECC operation in the NAND chip 200 is shown, and not all the structures are shown.

[0065] The NAND chip 200 includes: a page buffer / sensing circuit 230, including a latch L1 and a latch L2; an oscillator OSC, which generates a clock signal CK; an interface circuit (hereinafter referred to as ECC_IF) 240, which controls data transmission with the ECC chip 300 via an input / output terminal 220 dedicated to ECC; an interface circuit (hereinafter referred to as CTL_IF) 250, which controls data transmission with the controller chip 400 via an input / output terminal 210 for SPI; an ECC control unit 260; a controller 270, which receives commands and addresses input from the input / output terminal 210, includes a decoder for interpreting commands or an address counter for maintaining and counting addresses, and controls each unit based on the decoding result of the command; and an address control unit 280, which controls the column address of the page buffer / sensing circuit 230.

[0066] Latch L1 contains buffer C0 and buffer C1, while latch L2 contains only buffer C1. Data in buffer C1 can be transferred bidirectionally between latch L1 and latch L2. Latch L1 holds a page of data (e.g., 4KB), while buffers C0 and C1 hold half a page of data (e.g., 2KB). Buffer C1 in latch L2 holds half a page of data (e.g., 2KB). Buffer C0 holds data from sectors S0 through S3 (e.g., a sector is 512 bytes), while buffer C1 holds data from sectors S4 through S7.

[0067] Oscillator OSC generates a clock signal CK at a frequency optimized for data transmission timing and the processing times of various ECC components. Data transmission between the NAND chip 200 and the ECC chip 300 using the DATA terminal is synchronized with clock signal CK, and the ECC core 360 ​​of the ECC chip 300 performs ECC processing in synchronization with clock signal CK. The frequency of clock signal CK is independent of the frequency of the SPI clock signal CLK and can be set higher than the frequency of clock signal CLK.

[0068] The ECC_IF 240 receives a clock signal CK generated by an oscillator OSC and supplies the clock signal CK to the CK terminal of the ECC chip 300 via the CK terminal. During a read operation, the ECC_IF 240 outputs the read data held in the latch L2 from the DATA terminal to the DATA terminal of the ECC chip 300 in synchronization with the clock signal CK. Furthermore, during a programming operation, the ECC_IF 240 receives parity data generated by the ECC chip 300 from the DATA terminal in synchronization with the clock signal CK.

[0069] During a read operation, the ECC control unit 260 supplies a VALID signal to the ECC_IF 240. The VALID signal specifies the period during which data transfer between the ECC-dedicated input / output terminals 220 and 320 is valid, allowing data transfer on a sector-by-sector basis. During the period specified by the VALID signal, for example, while the VALID signal is high, the ECC_IF 240 transfers data from the DATA terminal of the NAND chip 200 to the DATA terminal of the ECC chip. Furthermore, the ECC_IF 240 outputs the VALID signal from the VALID terminal to the VALID terminal of the ECC chip 300, enabling the NAND_IF 340 of the ECC chip 300 to receive data from the NAND chip 200.

[0070] The CTL_IF 250 controls the input and output of data via the input / output terminal 210. The CTL_IF 250 receives commands, addresses, and data output from the controller chip 400, provides the commands and addresses to the controller 270, and holds the data in the latch L2 or the latch L1.

[0071] The controller 270 decodes the input command and controls operations such as read, program, and erase based on the decoded result. Furthermore, based on the decoded result, the controller 270 provides a control flag identifying read or program to the ECC control unit 260, or provides a status signal indicating whether the NAND chip 200 is busy or in standby mode to the CTL_IF 250. The controller 270 includes an address counter that counts the column address input from the CTL_IF 250 and provides the address of the address counter to the address control unit 280.

[0072] The ECC control unit 260 includes logic for controlling ECC processing and an address counter that stores and counts addresses used in ECC processing. The ECC control unit 260 is configured similarly to the ECC control unit 370 of the ECC chip 300. Specifically, the ECC control unit 260 is synchronized with the ECC control unit 370 to identify the ECC operation being performed by the ECC chip 300. Furthermore, a control flag is used by the ECC core 360 ​​to switch between the encoder and decoder.

[0073] The address control unit 280 receives the column address output from the controller 270 and the ECC column address output from the ECC control unit 260, and provides the page buffer / sensing circuit 230 with the column address selected according to the operation of the NAND chip 200. The position of data read from the latch L2 or the position of data written to the latch L2 is controlled by the column address.

[0074] The ECC chip 300 includes: RAM_E, RAM_O; an interface circuit (hereinafter referred to as NAND_IF) 340, which controls the data transmission between the NAND chip 200 via the ECC-specific input and output terminals 320; an interface circuit (hereinafter referred to as CTL_IF) 350, which controls the input and output of data between the NAND chip 200 and the controller chip 400 via the SPI-used input and output terminals 330 and 310; an ECC core 360, which performs error detection and correction; an ECC control unit 370, which includes logic for controlling the ECC core 360 ​​and an address counter for maintaining and counting addresses used for ECC processing; and a controller 380, which receives commands, addresses, and data input from the input and output terminals 310 and 330.

[0075] It's important to note that the ECC chip 300 is equipped with a controller 380 that identifies the NAND chip 200's current operation. Similar to the controller 270 of the NAND chip 200, the controller 380 receives input commands and addresses and includes a decoder for interpreting commands and an address counter for storing and counting addresses. Furthermore, the SPI input / output terminals 330 are electrically coupled to corresponding terminals on the SPI input / output terminals 310. Commands, addresses, and data from the controller 400 are supplied to both the ECC chip 300 and the NAND chip 200.

[0076] RAM_E and RAM_O each hold 1 / 4 page of data (data from two sectors). RAM_E can hold data from sectors S0, S2, S4, and S6 read from buffer C0 of latch L1, while RAM_O can hold data from sectors S1, S3, S5, and S7 read from buffer C1 of latch L2. Unlike latches L1 and L2, RAM_E and RAM_O function as dual-port memories. Furthermore, while latches L1 and L2 contain asynchronous circuitry, RAM_E and RAM_O contain synchronous circuitry.

[0077] During a read operation in the NAND chip 200, the NAND_IF 340 sequentially receives one page of data, sector by sector, from the NAND chip 200 via the ECC-dedicated input / output terminals 220 and 320 while the VALID signal is active high. The ECC control unit 370 selects Data_E (sectors S0, S2, S4, and S6) or Data_O (sectors S1, S3, S5, and S7) stored in RAM_E or RAM_O via selector SEL1, and selects Address_E or Address_O to RAM_E or RAM_O via selector SEL3.

[0078] When the ECC core 360 ​​performs error detection and correction on read data, the ECC control unit 370 selects the address of RAM_E or RAM_O via selector SEL3 and provides the ECC core 360 ​​with data identical to the data written to RAM_E or RAM_O via selector SEL2. Under the control of the ECC control unit 370, the ECC core 360 ​​performs syndrome calculation, Euclidean calculation, and error location search in a pipelined manner. To correct errors based on the found error location, the ECC core 360 ​​inverts the erroneous bits in the data read from RAM_E or RAM_O selected by selector SEL4. The corrected data is then output to the controller chip 400 via the CTL_IF 350 and the input / output terminal 330.

[0079] Furthermore, during programming, commands, addresses, and data from the controller chip 400 are input not only to the NAND chip 200 but also to the ECC chip 300. Based on the command decoding results, the controller 380 recognizes the programming operation and stores the data input from the SPI input / output terminal 330 in RAM_E and RAM_O. The ECC control unit 370 recognizes the programming operation through a control flag from the controller 380 and activates the encoder of the ECC core 360.

[0080] Under the control of the ECC control unit 370, the ECC core 360 ​​reads the input data stored in RAM_E or RAM_O, encodes the read data in sector units, and generates parity data for each sector. The generated parity data is transmitted from the DATA terminal to the DATA terminal of the NAND chip 200 via the NAND_IF 340. The NAND chip 200 stores the data received from the controller chip 400 in latch L1 and stores the parity data for each sector received from the ECC chip 300 via the ECC_IF 240 in latch L1 according to the column address specified by the ECC control unit 260. The controller 270 then programs the data stored in latch L1 into the memory array.

[0081] Next, the ECC operation of the flash memory 100 according to this embodiment will be described in detail. Figure 6 This diagram shows the timing of decoding read data by the ECC core 360. When the NAND chip 200 performs a read operation in response to a read command, at time t0, the ECC_IF 240 of the NAND chip 200 transmits the main data and parity data Pt of sector S0, held in latch L1, from the DATA terminal in synchronization with the clock signal CK. The NAND_IF 340 of the ECC chip 300 begins receiving the main data and parity data Pt of sector S0 from the DATA terminal. At time t1, reception of the main data and parity data Pt of sector S0 is completed. The received data of sector S0 is stored in RAM_E, while the ECC core 360 ​​performs syndrome calculation for sector S0. The transmission time between times t0 and t1 is shorter than the time required to transmit data via the SPI input / output terminals 210 because the data width of the ECC-dedicated DATA terminal and the frequency of the clock signal CK are optimized for ECC processing.

[0082] Similarly, at time t2, the transmission of the main data and parity data Pt of sector S1 is completed, and the data of sector S1 is saved in RAM_O. At time t3, the transmission of the main data and parity data Pt of sector S2 is completed, and the data of sector S2 is saved in RAM_E. At time t4, the transmission of the main data and parity data Pt of sector S3 is completed, and the data of sector S3 is saved in RAM_O.

[0083] While storing the data of sector S0 in RAM_E, the ECC core 360 ​​begins calculating the syndrome for sector S0. However, in one embodiment, the bit width of the DATA terminal or the frequency of the clock signal CK is set so that the syndrome calculation for sector S0 is completed at time t1. After calculating the syndrome, the ECC core 360 ​​calculates the error location polynomial for sector S0 and searches for the error location while receiving data from sector S1.

[0084] At time t5, the ECC core 360 ​​reads the main data of sector S0 from RAM_E selected by selectors SEL4 and SEL5 in synchronization with the clock signal CLK, inverts bit errors in the main data of sector S0 using ExOR, and outputs the error-corrected main data of sector S0 from the DO terminal of the input / output terminal 330 to the controller chip 400 in synchronization with the SPI clock signal CLK. At times t6, t7, and t8, the ECC core 360 ​​performs error correction on sectors S1, S2, and S3, and sequentially outputs the error-corrected main data of sectors S1, S2, and S3 to the controller chip 400 via the input / output terminal 330. The CPU_IF of the controller chip 400 transmits the main data of sectors S0, S1, S2, and S3 received at times t6, t7, t8, and t9 to the host device.

[0085] While the ECC core 360 ​​is performing the subsequent processing after calculating the error location polynomial for sectors S0 through S3, the NAND chip 200 transfers the main data and parity data for sectors S4 through S7 to the ECC chip 300 via the ECC-dedicated input / output terminals 220. The data transfer for sectors S4 through S7 is performed in response to the timing of external output of sectors S0 through S3. In other words, RAM_E and RAM_O can each only hold data for 1 / 4 page (two sectors). Therefore, after the stored data is output, the data in RAM_E and RAM_O can be overwritten.

[0086] Next, the continuous page read operation of the flash memory according to this embodiment will be described. Figure 7 for Figure 4 (B) shows a timing diagram of a continuous read operation of a flash memory (RAM0 and RAM1 each have a size (2KB) for storing 1 / 2 page data) of a comparative example. Figure 8 This is a timing diagram of the continuous read operation of the flash memory (RAM_E and RAM_O each have a size (1 KB) for storing 1 / 4 page data) of this embodiment.

[0087] Figure 7 、 Figure 8 In FIG. 1 , the upper half shows the operation of the NAND chip 200, and the lower half shows the timing of the ECC chip 300. Figure 7 As shown, array reading of the memory array is performed in response to data of the top address of a page being output from the DO terminal of the ECC chip 300. For example, when data of the top address of sector S0 of page P0 is output from terminal DO, the NAND chip 200 starts reading the array of page P1.

[0088] The NAND chip 200 stores the page data read from the memory array in buffers C0 and C1 of latch L1. Then, it transfers the data from sectors S4 through S7 of buffer C1 of latch L1 to buffer C1 of latch L2. While the VALID signal is high, the data from sectors S0 through S3 held in buffer C0 of latch L1 and the data from sectors S4 through S7 held in buffer C1 of latch L2 are transferred as a page of data to the ECC chip 300 on a buffer-by-buffer basis. The timing of data transfer from the NAND chip 200 to the ECC chip 300 coincides with the timing of the ECC chip 300 outputting data at the final address of the buffer unit to the controller chip 400. For example, in response to the ECC chip 300 outputting data at the final address of sector S3 of page P0, the NAND chip 200 begins transferring data from sectors S0 through S3 of page P1.

[0089] The ECC chip 300 performs error detection and correction on a sector-by-sector basis, outputting corrected data from the DO terminal. When the ECC chip 300 outputs data at the beginning address of a page, the NAND chip 200 begins array reading of the next page and stores the read data in latch L1. When array reading of the next page begins, data from buffer C1 in latch L1 is transferred to latch L2, preventing the latch L1 from overwriting the next page's data.

[0090] The address counter of the controller 270 of the NAND chip 200 is synchronized with the address counter of the controller 380 of the ECC chip 300. The controller 270 of the NAND chip 200 can use the column address counted by the address counter to obtain the starting address of the page or the final address of the buffer output from the DO terminal of the ECC chip 300. The address counter increments the column address by counting the number of toggles of the clock signal CK.

[0091] In the flash memory of this embodiment, Figure 8As shown, the timing of reading the memory array is the same as that of the comparative example, that is, it is performed in response to the data of the starting address of the page output from the DO terminal of the ECC chip 300. Moreover, regarding the data transmission between the NAND chip 200 and the ECC chip 300, the comparative example is performed in units of buffers, while the present embodiment is performed in units of sectors. If the data of one sector is transmitted, the VALID signal transitions to a high level during the data transmission period of one sector. In response to the ECC chip 300 completing the data output of the sector, the NAND chip 200 transmits the data of the sector of the 1 / 2 page from the sector to the ECC chip 300. For example, if the ECC chip 300 completes the output of the data of sector S0, the NAND chip 200 transmits the data of sector S4 of the same page to the ECC chip 300. If the ECC chip completes the output of the data of sector S1, the data of sector S5 of the same page is transmitted to the ECC chip 300. After the data output of sector S0 is completed, the next sector S4 can be overwritten in RAM_E. After the data output of sector S1 is completed, the next sector S5 can be overwritten in RAM_O.

[0092] Next, the limitations of continuous readout from the flash memory of this embodiment are described. Here, the time it takes for the NAND chip 200 to output data for one sector is tDOUT1, the time it takes for the ECC chip 300 to output data for one sector is tDOUT2, and the latency from the time the NAND chip 200 outputs data for one sector until error detection and correction for that sector is completed is tLTCY.

[0093] In the comparative example, formula (1) serves as a limitation.

[0094] tDOUT1+tLTCY<tDOUT2×4···(1)

[0095] In contrast, in this embodiment, formula (2) serves as a restriction.

[0096] tDOUT1+tLTCY<tDOUT2×3···(2)

[0097] The NAND chip 200 and the ECC chip 300 are connected via dedicated ECC input and output terminals. If a sector is 512 bytes, the bit width of the dedicated DATA terminal is set to 16 bits, and the clock signal CK frequency is set to 80 MHz, then tDOUT1 = 4 μs and tLTCY = 4 μs. In this case, tDOUT2 > (4 + 4) / 3 = 2.7 μs.

[0098] Figure 9 This is a timing diagram when an interruption occurs during the continuous reading of pages of the flash memory of the comparative example. Figure 10This is a timing diagram for the case where an interruption occurs during the continuous reading of a page of the flash memory of this embodiment. For example, sometimes the clock signal CLK of the ECC chip 300 stops, causing the data output from the DO terminal to be interrupted during the continuous reading (the interruption is shown at the DO terminal). In the event of such an interruption, in the flash memory of this embodiment, the RAM_E and RAM_O of the ECC chip 300 retain the data transmitted from the NAND chip 200, and before the ECC chip 300 outputs the data of the starting address of the page, the array read of the next page is not performed, so the data of the previous page is retained in the latches L1 and L2. Therefore, the data will not disappear due to the interruption, and the NAND chip 200 and the ECC chip 300 share the address of the page being read, so continuous reading can be restarted after the interruption.

[0099] Figure 11 FIG. 1 is a diagram showing the main structure of a flash memory according to a modified example of the present invention. Figure 4 As shown in (A), the NAND chip 200 includes a latch L1 including a buffer C0, a buffer C1, and a latch L2 including the buffer C1. However, in this modification, as shown in FIG. Figure 11 As shown, the NAND chip 200A includes a latch L1 including buffers C0 and C1, and a latch L2 including buffers C0 and C1. Latch L1 and latch L2 can each hold one page of data.

[0100] During a read operation, NAND chip 200A transfers data from sectors S0 through S3 in buffer C0 of latch L2 to ECC chip 300. Then, it transfers data from sectors S0 through S3 of the next page, held in buffer C0 of latch L1, to buffer C0 of latch L2. After transferring data from sectors S4 through S7 of buffer C1 of latch L2 to ECC chip 300, it transfers data from sectors S4 through S7 of the next page, held in buffer C1 of latch L1, to buffer C1 of latch L2. Finally, the next page of data read from the memory array is held in latch L1. ECC chip 300 performs the same operations as in the previous embodiment.

[0101] As described above, according to this embodiment, by having RAM_E and RAM_O of the ECC chip 300 alternately store data from even-numbered sectors and data from odd-numbered sectors, the data size (storage capacity) of RAM_E and RAM_O can be reduced, thereby reducing the area of ​​the ECC chip 300 and lowering costs. Furthermore, by transmitting read data between the NAND chip 200 and the ECC chip 300 via the ECC-dedicated DATA terminal, the time required for ECC processing can be shortened.

[0102] Furthermore, the above embodiment shows an example where a page consists of eight sectors (a buffer consists of four sectors). However, this is merely an example. For example, if a page is 4KB (a buffer is 2KB), and a sector is 512 bytes, then a page may consist of eight sectors. If a page is 2KB, then a page may consist of four sectors. In this case, the ECC chip 300 can also perform ECC processing on a sector-by-sector basis or on a multi-sector basis (generating parity data for each sector during programming and performing sector error detection and correction based on the parity data during reading).

[0103] While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A semiconductor memory device comprising: A NAND chip comprising a NAND-type memory array, a control unit, and an output unit, wherein the control unit controls a read operation of the memory array, and the output unit outputs data read from the memory array to an error detection and correction chip; An error detection and correction chip includes a first holding portion and a second holding portion, and an error detection and correction component, wherein the error detection and correction component performs error detection and correction on data held in the first holding portion and the second holding portion, and When a page contains n sectors, the output component outputs data to the error detection and correction chip in sectors, the first holding unit holds the data of the even-numbered sectors, and the second holding unit holds the data of the odd-numbered sectors. The error detection and correction component performs error detection and correction on the data read from the first holding unit or the second holding unit.

2. The semiconductor memory device according to claim 1, wherein The first holding unit and the second holding unit can each hold data of n / 4 sectors. The output section outputs the data of the sector to the outside in response to the error detection and correction chip, and outputs the data of the n / 2th sector from the sector to the error detection and correction chip.

3. The semiconductor memory device according to claim 1, wherein The control unit reads a next page from the memory array in response to the error detection and correction chip outputting data of a leading sector of a page to the outside.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein The output component includes: a first dedicated terminal for outputting data to the error detection and correction chip, The error detection and correction chip includes a second dedicated terminal for receiving data output from the first dedicated terminal.

5. The semiconductor memory device according to claim 4, wherein The first dedicated terminal includes a clock terminal for outputting a clock signal and a data terminal for outputting data, and the second dedicated terminal includes a clock terminal for receiving the clock signal and a data terminal for inputting data. The output section outputs data from the data terminal in synchronization with the clock signal, The error detection and correction chip inputs data from the data terminal in synchronization with the clock signal.

6. The semiconductor memory device according to any one of claims 1 to 3, wherein The control unit includes: a first latch for holding data read from a memory array; and a second latch for holding data transmitted from the first latch, wherein the first latch holds one page of data and the second latch holds 1 / 2 page of data. The output unit outputs the first half data of the 1 / 2 page held in the first latch and the second half data of the 1 / 2 page held in the second latch to the error detection and correction chip.

7. The semiconductor memory device according to any one of claims 1 to 3, wherein When a page contains eight sectors and the error detection and correction unit performs data error detection and correction in units of sectors, the time for the output unit to output data of one sector is set as tDOUT1, the time for the error detection and correction chip to output data of one sector to the outside is set as tDOUT2, and the delay from the time the NAND chip outputs data of one sector until the error detection and correction of the sector is completed is set as tLTCY. There is a limitation of tDOUT1+tLTCY<tDOUT2×3.

8. The semiconductor memory device according to any one of claims 1 to 3, wherein The NAND chip and the error detection and correction chip are housed in one package.

9. A readout method for a semiconductor memory device, the semiconductor memory device comprising: A NAND chip comprising a NAND-type memory array, a control unit, and an output unit, wherein the control unit controls the read operation of the memory array, and the output unit outputs the data read from the memory array to an error detection and correction chip; and an error detection and correction chip comprising a first holding unit and a second holding unit, and an error detection and correction unit, wherein the error detection and correction unit performs error detection and correction on the data held in the first holding unit and the second holding unit, and The output component outputs data to the error detection and correction chip in units of sectors. The first holding unit holds data of even-numbered sectors, and the second holding unit holds data of odd-numbered sectors. The error detection and correction unit performs error detection and correction on data read from the first holding unit or the second holding unit, and outputs the corrected data to the outside.

10. The readout method according to claim 9, wherein: The output unit outputs data from the first dedicated terminal to the error detection and correction chip in synchronization with the clock signal. The error detection and correction chip receives data from a second dedicated terminal connected to the first dedicated terminal in synchronization with the clock signal.

11. The readout method according to claim 9 or 10, wherein: The first holding unit and the second holding unit can each hold data of n / 4 sectors. The output section outputs the data of the sector to the outside in response to the error detection and correction chip, and outputs the data of the n / 2th sector from the sector to the error detection and correction chip.

12. The readout method according to claim 9, wherein: The control unit reads a next page from the memory array in response to the error detection and correction chip outputting data of a leading sector of a page to the outside.

13. The readout method according to claim 9 or 10, wherein: When a page contains eight sectors and the error detection and correction unit performs data error detection and correction in units of sectors, the time for the output unit to output data of one sector is set as tDOUT1, the time for the error detection and correction chip to output data of one sector to the outside is set as tDOUT2, and the delay from the time the NAND chip outputs data of one sector until the error detection and correction of the sector is completed is set as tLTCY. There is a limitation of tDOUT1+tLTCY<tDOUT2×3.

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