Method of forming a semiconductor package element

Abstract

A method of forming a semiconductor package element includes providing a substrate, forming a flip chip on a first side of the substrate, forming a molding compound on the first side of the substrate, wherein the molding compound covers the flip chip, forming a heat sink on the molding compound, forming an adhesive layer on a second side of the substrate, wherein the second side is an opposite side of the first side in a vertical direction, performing a pre-cut process and an etching process on the heat sink after forming the adhesive layer, and removing the adhesive layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method for forming a semiconductor package element, and more particularly to a method for protecting a solder pad for connecting a solder ball. BACKGROUND

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size. However, as the minimum feature size is reduced, new problems arise that need to be addressed.

[0003] As more components are integrated into a given area, the heat dissipation requirement of the components during operation also increases. A heat sink is conventionally formed on a semiconductor package element. However, the material of the heat sink is usually selected from hard materials such as metal, which increases the difficulty of singulation process. In order to overcome the added difficulty, another etching process needs to be performed before the singulation process, which may damage the metal solder pad on the surface of the semiconductor package element. Therefore, before improving the heat dissipation capability of the semiconductor package element, the problem of etching process damaging the surface of the package element must be solved. SUMMARY

[0004] A method for forming a semiconductor package element includes providing a substrate, forming a flip chip on a first side of the substrate, forming a molding compound on the first side of the substrate, wherein the molding compound covers the flip chip, forming a heat sink on the molding compound, forming an adhesive layer on a second side of the substrate, wherein the second side is an opposite side of the first side in a vertical direction, performing a pre-singulation process and an etching process on the heat sink after forming the adhesive layer, and removing the adhesive layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] Various aspects of the disclosure will be described in detail with reference to the drawings, of which:

[0006] Figure 1A and 2 FIGS. 1-11 are cross-sectional schematic views of various intermediate stages in manufacturing a semiconductor package element according to some embodiments of the present disclosure.

[0007] Figure 1B FIG. 12 is an enlarged schematic view of the structure of FIG. 11 according to some embodiments of the present disclosure. Figure 1A

[0008] SYMBOL DESCRIPTION

[0009] ​10: Semiconductor packaged components

[0010] 100: Base

[0011] 100A: First side

[0012] 100B: Second side

[0013] 120: Flip Chip

[0014] 130: Column

[0015] 140: Bottom filler

[0016] 150: Molded compound

[0017] 160: Heatsink

[0018] 160R: Metal residue

[0019] 170: Cutting the opening

[0020] 180: Adhesive layer

[0021] 200: Welding ball

[0022] 1000: Core

[0023] 1100: Inner metal layer

[0024] 1200: Guide hole

[0025] 1300: Adhesive layer

[0026] 1400: Outer metal layer

[0027] 1500: Welding Mask

[0028] 1600: Organic solder mask

[0029] 1800: Patterned opening Detailed Implementation

[0030] The following disclosure provides numerous different embodiments or examples for implementing various components of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to limit the embodiments disclosed herein. For example, the description mentioning that a first component is formed on top of a second component may include embodiments in which the first and second components are in direct contact, or embodiments in which an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplification and clarity and does not in itself govern the relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, in some embodiments of the present invention, terms such as “connection” and “interconnection” may, unless specifically defined, refer to two structures being in direct contact, or to two structures not being in direct contact, wherein there is another structure disposed between the two structures.

[0032] Furthermore, spatially related terms such as “below,” “under,” “lower,” “above,” “above,” and similar terms may be used here to describe the relationship between one element or component and other elements or components as shown in the figure. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations shown in the figures. When the device is rotated to other orientations (rotated 90° or other orientations), the spatial relative descriptions used herein can also be interpreted according to the orientation after rotation.

[0033] The terms "about," "approximately," and "roughly" as used herein generally mean within ±20%, preferably ±10%, and even more preferably ±5%, or ±3%, or ±2%, or ±1%, or 0.5%, of a given value. The values ​​given herein are approximate; that is, unless specifically stated otherwise, the given values ​​may imply the meaning of "about," "approximately," or "roughly."

[0034] The following describes some embodiments of this disclosure in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Additional components may be added to the semiconductor device structure. Some of the described components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It is understood that these terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with the background or context of the relevant art and the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments disclosed herein.

[0036] In the manufacturing process of semiconductor packaging components, molding materials are used to cover all components (whether active or passive) on the chip surface to facilitate subsequent packaging steps. As circuit feature sizes continue to shrink and integration density increases, all components experience overheating during operation. To address this overheating, modern semiconductor packaging components (especially those with flip chips) incorporate heat sinks on the molding material. Generally, the heat sink is made of a highly thermally conductive metal, which has higher hardness than the molding material.

[0037] This disclosure provides a method for forming a semiconductor package element, particularly suitable for protecting solder pads. Since semiconductor package elements require a singulation process, the added heat sink also needs to be cut along with it. However, due to the significant difference in properties (e.g., hardness) between the heat sink and the molding material, it is difficult to simultaneously complete the singulation of both the heat sink and the molding material in a single process. Therefore, in existing methods, a pre-cut process is performed only on the heat sink before the original singulation process. Since the heat sink is in direct contact with the underlying molding material, the pre-cut process must be precisely controlled to avoid damaging the underlying molding material. Also, because damage to the molding material must be avoided, the pre-cut process typically cannot cut the heat sink cleanly. Therefore, after the pre-cut process, an etching process is performed to remove metal residues from the cut heat sink, which may be hair-like conductive material.

[0038] In some embodiments, a wet etching process is used to remove metal residues. In other words, the entire semiconductor package may be immersed in an etchant to remove metal residues. However, in addition to removing metal residues, the etchant may also damage the metal pads on the other side of the semiconductor package used to solder solder balls. Existing components use nickel-gold (NiAu) materials to form the solder pads, which avoids the adverse effects of etchants (such as the inability to form solder balls on the metal pads). However, specifying the metal material for the solder pads can impose too many limitations on the overall process. For example, there are not many manufacturers that can supply such materials.

[0039] In some embodiments disclosed herein, an adhesive layer is formed on the other side of the substrate prior to the pre-cutting process of the heat sink, and then removed after the etching process is completed. This protects the metal solder pads on the other side of the substrate from the etching process. A wider variety of metals or other conductive materials can therefore be used for the solder pads. Furthermore, the risks associated with the Giaviani effect are also avoided. Overall, this increases the design flexibility of semiconductor package substrates and improves the quality of the fabrication process and device handling.

[0040] Figure 1A and 2 Figures 1-11 are schematic cross-sectional views illustrating various intermediate stages in the fabrication of a semiconductor package element 10 according to some embodiments of the present disclosure. In this embodiment, the semiconductor package element 10 includes a flip chip, a molding compound, and a heat sink formed on one side of a substrate, and solder balls formed on the other side of the substrate. It should be noted that... Figure 1A and 2 The components shown in 11-12 are illustrative and not intended to limit the embodiments disclosed herein. Figure 1A As shown, a base 100 can be provided initially.

[0041] Continue to refer to Figure 1A The substrate 100 may be a laminate. For example, the substrate 100 may include multiple metal layers and dielectric layers arranged alternately, and has vias through the dielectric layers coupling the respective metal layers. In some embodiments, one surface of the substrate 100 is used to attach flip chips, while the other surface is used to form solder balls. According to some embodiments of this disclosure, both sides of the substrate have metal layers. By design, a portion of the surface metal layers is covered by a solder mask, while another portion of the surface metal layers not covered by the solder mask is covered by a thin film of Organic Solderability Preservative (OSP).

[0042] Figure 1B The following are some embodiments illustrated according to the present disclosure. Figure 1A An enlarged schematic diagram of substrate 100 is shown. Substrate 100 includes a first side 100A and a second side 100B, wherein the first side 100A and the second side 100B are opposite sides of substrate 100 in the vertical direction. According to some embodiments of this disclosure, the first side 100A is used to connect flip chips, while the second side 100B is used to form solder balls. According to some embodiments, substrate 100 includes a core 1000 located at the center of substrate 100. Core 1000 may be a single film layer or a composite structure formed of multiple film layers (not shown). The thickness of core 1000 may be between about 60 μm and 400 μm, for example, between 100 μm and 200 μm. In some embodiments, core 1000 may include a suitable insulating or dielectric material. For example, the material of core 1000 may include glass epoxy resin, bismaleimide triazine (BT), or Ajinomoto build-up film (ABF). In other embodiments, the core 1000 may be a fiber-reinforced glass epoxy resin.

[0043] Continue to refer to Figure 1BThrough-holes can be formed through the core 1000 using laser drilling. Next, a metallic material is deposited on both sides of the core 1000 in the vertical direction. In some embodiments, physical vapor deposition (PVD), atomic layer deposition (ALD), plating, other suitable processes, or combinations thereof, can be used to deposit the metallic material. An inner metal layer 1100 is formed on both sides of the core 1000. In addition, the metallic material also fills the through-holes through the core 1000 to form vias 1200. In some embodiments, the vias 1200 are coupled to the inner metal layer 1100 on both sides of the core 1000. The thickness of the inner metal layer 1100 can be between about 15 μm and 29 μm, for example, between 20 μm and 24 μm. The width of the vias 1200 can be between about 85 μm and 105 μm, for example, between 90 μm and 100 μm. Metallic materials may include cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), other similar materials, combinations thereof, or multiple layers thereof.

[0044] Please refer to Figure 1B An adhesive layer 1300 can be formed on the inner metal layers 1100 on both sides. The function of the adhesive layer 1300 is to bond the two metal layers together, such as the inner metal layer 1100 and the outer metal layer 1400 (described below), while maintaining a separation between the two bonded metal layers. The adhesive layer 1300 can be a sheet substrate containing a resin component. According to some embodiments of this disclosure, the adhesive layer 1300 is pre-impregnated (pre-preg, PP) fiberglass, and therefore the adhesive layer 1300 can also be referred to as a pre-impregnated (PP) layer. The thickness of the adhesive layer 1300 can be between about 25 μm and 55 μm, for example, between 30 μm and 50 μm. The adhesive layer 1300 can be formed on the inner metal layers 1100 on both sides in the vertical direction by lamination.

[0045] For example, the material of the adhesive layer 1300 may include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenyl type epoxy resin, aralkyl type epoxy resin, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, biphenyl aralkyl type epoxy resin, fluorene type epoxy resin, xanthene type epoxy resin, triglycidyl isocyanurate (TGIC), combinations thereof, or other similar materials. The adhesive layer 1300 can be formed by spin-on coating, chemical vapor deposition (CVD), atomic layer deposition, high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or combinations thereof.

[0046] Continue to refer to Figure 1BThrough-holes can be formed through the adhesive layer 1300 using the laser drilling method described above. Next, a metal material is deposited on both sides of the adhesive layer 1300 in the vertical direction. In some embodiments, physical vapor deposition, atomic layer deposition, electroplating, other suitable processes, or combinations thereof can be used to deposit the metal material. An outer metal layer 1400 is formed on the surface of the adhesive layer 1300 by the metal material. In addition, the metal material also fills the through-holes in the adhesive layer 1300 to form vias 1200. In some embodiments, the vias 1200 in the adhesive layer 1300 couple the inner metal layer 1100 and the outer metal layer 1400. The thickness of the outer metal layer 1400 can be between about 13 μm and 25 μm, for example, between 15 μm and 23 μm. The material of the outer metal layer 1400 can be similar to that of the inner metal layer 1100, and therefore will not be repeated here. In some embodiments, the outer metal layer 1400 can optionally be patterned.

[0047] Please refer to Figure 1B A solder mask material can be coated on the surfaces of the adhesive layers 1300 on both sides in the vertical direction, covering the patterned outer metal layer 1400. The solder mask material can be a laminated or screen-printed film layer formed on the first side 100A and the second side 100B. In some embodiments, the solder mask material is an electrically insulating material with low surface stress. According to some embodiments of this disclosure, the solder mask material can be patterned to form a solder mask 1500. In some embodiments, lithography processes (e.g., coating an impedance layer, soft baking, exposure, post-exposure baking, development, other suitable techniques, or combinations thereof) and etching processes (e.g., wet etching, dry etching, other suitable methods, or combinations thereof), other suitable processes, or combinations thereof, can be used to form patterned openings 1800 in the solder mask material. The solder mask 1500 is used to protect a portion of the outer metal layer 1400 from short circuits caused by subsequent soldering and / or electroplating steps. The portion of the outer metal layer 1400 exposed through the patterned opening 1800 corresponds to the metal pads subsequently used for electrically connecting the flip chip (on the first side 100A) and the solder ball (on the second side 100B). Since the solder mask 1500 must cover the outer metal layer 1400, the thickness of the solder mask 1500 naturally needs to be greater than the thickness of the outer metal layer 1400. The thickness of the solder mask 1500 can be between approximately 10 μm and 22 μm, for example, between 12 μm and 20 μm.

[0048] Continue to refer to Figure 1BAn organic solder mask 1600 can be deposited on the portion of the outer metal layer 1400 exposed through the patterned opening 1800. In some embodiments, the organic solder mask 1600 can protect the outer metal layer 1400 from contact with air until the soldering step. Furthermore, the organic solder mask 1600 can be easily removed by flux and dilute acid, exposing a clean metal surface for soldering. The organic solder mask 1600 adheres to the metal surface by forming coordination bonds with metal atoms. The organic solder mask 1600 can be a water-based organic compound. For example, the material of the organic solder mask 1600 can be selected from the azole family, including benzotriazoles, imidazoles, benzimazoles, other similar materials, or combinations thereof. If the thickness of the organic solder mask 1600 is too thin, holes may appear, causing the metal surface to come into contact with air and resulting in oxidation or sulfidation. If the organic solder mask 1600 is too thick, a stronger flux will be needed to remove it before soldering. The thickness of the organic solder mask 1600 can be between approximately 0.2 μm and 0.5 μm, for example, between 0.3 μm and 0.4 μm.

[0049] First, the exposed metal surface can be degreased (using an acid cleaner). Degreasing removes oxides, fingerprints, grease, or other contaminants that may have appeared on the metal surface from previous processes, thus cleaning the surface. Next, micro-etching can be performed to remove more severe oxides, creating a uniform, bright, slightly rough metal surface that allows for a more fine and even application of the subsequent organic solder mask. Then, acid rinsing can be performed to thoroughly remove any residue from the micro-etched metal surface, ensuring a clean finish. The organic solder mask can then be applied to the clean metal surface. Finally, drying is performed to maintain the organic solder mask at 1600°C.

[0050] After the organic solder mask 1600 is completed, the outer metal layers 1400 of the first side 100A and the second side 100B of the substrate 100 are completely covered to prevent contact with air and thus avoid affecting subsequent processes. In some embodiments, the solder mask 1500 covers the portion of the outer metal layer 1400 of the first side 100A that is not used to form a flip chip, and covers the portion of the outer metal layer 1400 of the second side 100B that is not used to solder solder balls. In other words, the portion of the outer metal layer 1400 of the first side 100A that is used to form a flip chip and the portion of the outer metal layer 1400 of the second side 100B that is used to solder solder balls are exposed through the patterned opening 1800 and protected by the easily removable organic solder mask 1600 until the relevant processes are required. After the organic solder mask 1600 is formed, the preset structure of the substrate 100 is completed, and the manufacturing of the semiconductor packaged device of this invention can begin.

[0051] Please refer to Figure 2 A flip chip 120 is connected on a first side 100A of the substrate 100. In some embodiments, the flip chip 120 may include active or passive components. Active components include metal-oxide-semiconductor (MOS) transistors, complementary metal-oxide-semiconductor (CMOS) transistors, lateral-diffused metal-oxide-semiconductor (LDMOS), bipolar complementary metal-oxide-semiconductor-double diffused metal-oxide-semiconductor (BCD), planar transistors, fin field-effect transistors (FinFETs), gate-all-around (GAA) field-effect transistors, other similar elements, or combinations thereof. Passive components include metal traces, inductors, resistors, diodes, bonding pads, or other similar structures. For simplicity, details of the flip chip 120 are not shown here.

[0052] Because the front end of the chip is connected to the first side 100A of the substrate 100 in an "inverted" manner, it is referred to as a flip chip 120. Traditional processes wire bond the chip's bonding pads to the bonding pads of the packaged components, but excessively long metal wires increase inductance between components. Unlike wire bonding, this chip has multiple pillars 130, sometimes referred to as bumps, formed on the top of its front end. These pillars 130 are then soldered to the first side 100A of the substrate 100, specifically the portion of the outer metal layer 1400 of the first side 100A exposed through patterned openings 1800. By eliminating wire bonding, the bonding pads can be distributed across the entire chip surface, rather than concentrated around the periphery. Furthermore, the chip size and circuit configuration offer greater flexibility, while optimizing overall structural performance. This process is known as surface mount technology (SMT).

[0053] In some embodiments, a plurality of pillars 130 may include a metal layer, a capping layer, and a solder area sequentially formed on the top of the front end of the flip chip 120. The base area of ​​the plurality of pillars 130 may be circular or elliptical, and its diameter may be between about 40 μm and 80 μm, for example, between 60 μm and 70 μm. The height of the plurality of pillars 130 may be between about 50 μm and 65 μm, for example, between 58 μm and 62 μm. The metal layer may be columnar with straight sidewalls, and its material may include copper or a copper alloy. The material of the capping layer may include nickel, palladium, gold, other similar materials, or combinations thereof. The material of the solder area may include a tin-silver alloy, a tin-silver-copper alloy, other similar materials, or combinations thereof. According to some embodiments of this disclosure, a reflow process (e.g., a convection reflow process, a laser reflow process, or other similar methods) may be used to reflow the solder area. After the reflow process, the solder area may have a rounded surface. It should be noted that during the bonding process, the solder areas of the multiple pillars 130 will directly contact the portion of the outer metal layer 1400 of the first side 100A exposed through the patterned opening 1800.

[0054] Please refer to Figure 3An underfiller 140 can be injected, which penetrates into the space between the flip chip 120 and the substrate 100 via dispensing. In some embodiments, the underfiller 140 may contact and surround a plurality of pillars 130. The underfiller 140 can be cured to further secure the flip chip 120 and the plurality of pillars 130 on a first side 100A of the substrate 100. In some embodiments, the underfiller 140 may overflow beyond the space between the flip chip 120 and the substrate 100 and surround a portion of the peripheral sidewalls of the flip chip 120 to reinforce the stability of the flip chip 120. The material of the underfiller 140 may include epoxy resin or silicone.

[0055] Please refer to Figure 4 A molding compound 150 can be formed on a first side 100A of the substrate 100. In some embodiments, the molding compound 150 covers the flip chip 120 and the underfill 140. The molding compound 150 protects the flip chip 120 from mechanical stress to facilitate subsequent operations. Furthermore, the molding compound 150 can be planarized with a planarization process (e.g., chemical mechanical polishing, CMP), the surface of which can be used for marking for identification. The molding compound 150 can be formed using hot-press, compression, or injection methods. The height of the molding compound 150 can be between about 300 μm and 500 μm, for example, between 350 μm and 480 μm. The material of the molding compound 150 is generally a plastic compound, which may include epoxy resin, phenolic curing agents, silica, catalyst, pigment, or mold release agent.

[0056] Please refer to Figure 5A heat sink 160 can be formed on the flat top surface of the molding compound 150. According to some embodiments of this disclosure, the heat sink 160 can dissipate heat generated from the flip chip 120 during operation. In some embodiments, the surface of the heat sink 160 can also be used for marking for identification. The heat sink 160 can be deposited using physical vapor deposition, atomic layer deposition, electroplating, other suitable processes, or combinations thereof. The thickness of the heat sink 160 can be between about 0.11 μm and 0.15 μm, for example, between 0.12 μm and 0.14 μm. The material of the heat sink 160 can include any material with thermal conductivity, such as metal. Since the thermal conductivity of metal can be 400 to 500 times higher than that of plastic, it is necessary to provide a heat sink 160 made of metal material in components with increasingly higher component integration densities. However, the heat sink 160 made of metal material has a higher hardness than the plastic material of the molding compound 150, making it difficult to cut the molding compound 150 and the heat sink 160 together during the single-crystallization process.

[0057] In conventional manufacturing processes, a pre-cutting process is performed after the heat sink 160 is formed, cutting the heat sink 160 to align with the positions for subsequent single crystallization. Compared to cutting plastic materials, cutting the heat sink 160 may require greater energy or more rigid tools. It should be noted that the heat sink 160 is formed directly on top of the molding compound 150, and the molding compound 150 is in direct contact with the heat sink 160. If the cutting process parameters for the heat sink 160 are set too high, the molding compound 150 directly below may be damaged. Therefore, to avoid damaging the molding compound 150, the pre-cutting process for the heat sink 160 may not create clean cuts.

[0058] Metal residues can easily form on the sidewalls of the 160-cut channels in the heatsink, requiring additional etching processes to remove them. Generally, this etching process is a wet etching process, which immerses the entire semiconductor package in an acidic etchant solution. Besides removing metal residues, the etchant may also damage the outer metal layer 1400 on the other side of the substrate 100 (e.g., the second side 100B), and the organic solder mask 1600 may not be able to protect the outer metal layer 1400 from the etchant's effects. To reduce the impact of the etching process on the outer metal layer 1400 of the second side 100B, conventional processes specifically form the outer metal layer 1400 with a nickel-gold material, which will subsequently be used to form solder balls. However, limiting the material of the outer metal layer 1400 of the second side 100B imposes excessive constraints on the overall process. For example, there are not many manufacturers that can supply such materials.

[0059] The Giavani effect occurs when materials coupled with two different metallic elements (such as nickel and gold) are immersed in an etchant solution. One of the coupled metals acts as the anode, and the other as the cathode. The corrosion rate of the anode is higher than that of the uncoupled metal, while the corrosion rate of the cathode is lower. The driving force created by the potential difference between the two elements results in different corrosion patterns. The element that corrodes more quickly reduces the overall material properties, thus affecting the stability of the weld ball.

[0060] The inventors of this case propose a method to protect the metal layer used to form the solder balls from the etching process of the heat sink 160. Please refer to... Figure 6 An adhesive layer 180 is formed on the second side 100B of the substrate 100. The material of the adhesive layer 180 may include polyimide (PI), polyamide (PA), combinations thereof, or other similar materials. The thickness of the adhesive layer 180 may be between about 100 μm and 150 μm, for example, between 120 μm and 140 μm. The adhesive layer 180 may be formed by spin coating, chemical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, flow-through chemical vapor deposition, subatmospheric pressure chemical vapor deposition, other similar methods, or combinations thereof.

[0061] The adhesive layer 180 isolates the portion of the outer metal layer 1400 of the second side 100B exposed through the patterned opening 1800 from the etchant used in the etching process of the heat sink 160, thereby protecting the outer metal layer 1400 from damage during the etching process. Furthermore, since the adhesive layer 180 provides stronger protection than the organic solder mask 1600, the material of the outer metal layer 1400 is not limited to nickel-gold. Any metal material can be used to form the outer metal layer 1400 of the second side 100B. Moreover, when the outer metal layer 1400 of the second side 100B does not come into contact with the etchant, the effect of the Giovanni effect becomes very small.

[0062] Please refer to Figure 7After forming the adhesive layer 180 on the second side 100B of the substrate 100, a pre-cutting process can be performed on the heat sink 160. The pre-cutting process removes portions of the heat sink 160 that are expected to be monocrystallized. As previously mentioned, the heat sink 160 and the molding compound 150 have significantly different material hardness, making it difficult to monocrystallize them together. In some embodiments, the pre-cutting process can be partial, where the portion of the heat sink 160 away from the molding compound 150 is cut, while the portion closer to the molding compound 150 is not cut. In other embodiments, the pre-cutting process can be complete, cutting through the heat sink 160 entirely. Those skilled in the art can tailor appropriate pre-cutting methods to subsequent etching processes. Lasers or blades can be used for the pre-cutting process. After the pre-cutting process is completed, multiple cutting openings 170 are formed in the heat sink 160. Since the multiple cutting openings 170 correspond to portions expected to be monocrystallized, from a top view, the multiple cutting openings 170 can form a single mesh structure. To avoid damaging the underlying molding compound 150, the parameters of the pre-cutting process cannot be set too high, resulting in the formation of multiple metal residues 160R on the cutting surfaces of the multiple cutting openings 170. According to some embodiments of this disclosure, the metal residues 160R may be hair-like conductive materials, which need to be removed by subsequent etching processes to avoid short circuits in subsequent processes.

[0063] Please refer to Figure 8 After the pre-cutting process is completed, an etching process can be performed on the heat sink 160. The etching process removes multiple metal residues 160R left in the multiple cut openings 170, thereby producing clean multiple cut openings 170. In conventional processes, since the molding compound 150 is disposed on the first side 100A of the substrate 100, the outer metal layer 1400 of the first side 100A does not come into contact with the etchant. In this case, the adhesive layer 180 covers the second side 100B of the substrate 100, so the outer metal layer 1400 of the second side 100B also does not come into contact with the etchant. Since the adhesive layer 180 provides effective protection, the material of the outer metal layer 1400 is not limited to nickel-gold material, but can be any metal material. Furthermore, when the outer metal layer 1400 of the second side 100B does not come into contact with the etchant, the effect of the Giovanni effect becomes very small. As described above, the etching process can be a wet etching process, which immerses the entire semiconductor package element in an acidic etchant solution. The etchant chemicals may include sulfuric acid (H2SO4), hydrochloric acid (HCl), hydrogen bromide (HBr), ammonia (NH3), or combinations thereof. The solvents for the chemicals include deionized (DI) water, ethanol, acetone, other similar solvents, or combinations thereof.

[0064] Please refer to Figure 9 After the etching process is completed, the adhesive layer 180 can be removed. Since the purpose of the adhesive layer 180 is to protect the outer metal layer 1400 of the second side 100B from the effects of the etching process, the adhesive layer 180 needs to be removed to facilitate subsequent processes. The adhesiveness of the adhesive layer 180 can be reduced using appropriate chemicals or heating methods without affecting the structure of other semiconductor package components. Afterwards, the adhesive layer 180 can be peeled off from the second side 100B of the substrate 100.

[0065] Please refer to Figure 10 When the second side 100B of the substrate 100 is exposed, a plurality of solder balls 200 can be formed on the portion of the outer metal layer 1400 exposed through the patterned opening 1800. In some embodiments, the solder balls 200 may also be referred to as “solder bumps”. The plurality of solder balls 200 on the second side 100B can be arranged in a ball grid array (BGA) for connecting semiconductor packaged components to other components, such as printed circuit boards (PCBs). The plurality of solder balls 200 can be thermally bonded to the outer metal layer 1400 of the second side 100B using an bonding machine, followed by a reflow process. After reflow, the diameter of the plurality of solder balls 200 can be between approximately 250 μm and 500 μm, for example, between 300 μm and 400 μm. The material of the plurality of solder balls 200 includes any suitable metallic material. In other embodiments, a barrier metal layer may be formed on the outer metal layer 1400 before bonding the plurality of weld balls 200 to increase the adhesion strength between the plurality of weld balls 200 and the outer metal layer 1400.

[0066] After forming multiple solder balls 200, the manufacturing of the semiconductor package element 10 is completed. As described above, the semiconductor package element 10 can be connected to a printed circuit board via the multiple solder balls 200. The printed circuit board can be installed in many electronic products. Since the outer metal layer 1400 of the second side 100B is effectively protected, the multiple solder balls 200 formed on the outer metal layer 1400 can provide a more reliable electrical connection between the semiconductor package element 10 and the printed circuit board.

[0067] Please refer to Figure 11A single-crystallization process can be performed on the semiconductor package element 10. According to some embodiments of this disclosure, the single-crystallization process can begin from the second side 100B. As described above, the plurality of cut openings 170 in the heat sink 160 correspond to the locations of the semiconductor package element 10 to be single-crystallized, and can be single-crystallization cut streets or scribings. Alignment detection can be used to ensure that the cut streets / scibings for single-crystallization on the second side 100B are consistent with the plurality of cut openings 170 on the reverse side. In some embodiments, the cut streets / scibings are arranged to avoid critical components of the semiconductor package element 10, such as the flip chip 120. In embodiments using cut streets, the width of the cut streets can be between about 0.25 mm and 0.35 mm, for example, between 0.28 mm and 0.32 mm. The single-crystallization process can be performed by sawing, plasma etching, laser, combinations thereof, or other similar methods. The single-crystallized component can be used for subsequent processes.

[0068] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the disclosed embodiments. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the disclosed embodiments to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor packaged element, comprising: Provide a base; A flip chip die is formed on a first side of the substrate; A molding compound is formed on the first side of the substrate, wherein the molding compound covers the flip chip; A heat sink is formed on the molding compound; An adhesive layer is formed on a second side of the substrate, wherein the second side is the opposite side of the first side in the vertical direction; After the adhesive layer is formed, the heat sink undergoes a pre-cut process and an etching process. Remove the adhesive layer; and After the adhesive layer is removed, a plurality of weld balls are formed on the second side of the substrate.

2. The method for forming a semiconductor packaged element as claimed in claim 1, characterized in that, The flip chip is connected to the substrate via multiple pillars.

3. The method for forming a semiconductor packaged element as claimed in claim 2, characterized in that, It also includes injecting an underfill between the substrate and the flip chip, and around the pillars.

4. The method for forming a semiconductor packaged element as claimed in claim 1, characterized in that, Forming the molding compound includes planarizing the top surface of the molding compound.

5. The method for forming a semiconductor packaged element as claimed in claim 1, characterized in that, Each of the first side and the second side of the base further includes: An outer metal layer; A welding mask is used to cover the outer metal layer; and An organic solderability preservative (OSP) film covers the outer metal layer.

6. The method for forming a semiconductor packaged element as claimed in claim 5, characterized in that, It also includes patterning the solder mask to form a plurality of patterned openings through which the outer metal layer is exposed.

7. The method for forming a semiconductor packaged element as claimed in claim 6, characterized in that, The organic solder mask directly contacts the portion of the outer metal layer exposed through the patterned openings.

8. The method for forming a semiconductor packaged element as claimed in claim 1, characterized in that, The heat sink is pre-cut to create multiple cut openings in the heat sink.

9. The method for forming a semiconductor packaged element as claimed in claim 8, characterized in that, After the pre-cutting process, multiple metal residues are generated in the cut openings.

10. The method for forming a semiconductor packaged element as claimed in claim 1, characterized in that, This etching process is a wet etching process.

11. The method for forming a semiconductor packaged element as claimed in claim 9, characterized in that, The etching process is performed to remove these metal residues.

12. The method for forming a semiconductor packaged element as claimed in claim 1, characterized in that, The adhesive layer isolates the second side of the substrate from the chemicals used in the etching process.

13. The method for forming a semiconductor packaged element as claimed in claim 1, characterized in that, After the etching process is completed, the adhesive layer is removed.

14. The method for forming a semiconductor packaged element as claimed in claim 1, characterized in that, This also includes a singulation process for the semiconductor package element after the solder balls are formed.

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