Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises: a substrate, a first trench isolation structure with an isolated LDMOS region and a memory device region; a gate layer, comprising a gate lateral part and a gate longitudinal part connected with each other, the gate lateral part extending from the LDMOS region to the memory device region, the gate longitudinal part being located in the first trench isolation structure of the LDMOS region, a tunneling oxide layer being sandwiched between the gate lateral part and the substrate of the memory device region, and a gate oxide layer being sandwiched between the gate longitudinal part and the substrate of the LDMOS region; a second source region and a second drain region being formed in the substrate on both sides of the gate lateral part of the memory device region, and a partial tunneling oxide layer being sandwiched between the second drain region and the gate lateral part. The technical scheme of the application makes it unnecessary to connect a gate drive circuit on the gate layer to control the opening and closing of the LDMOS device, thereby reducing the complexity of the opening and closing operation of the LDMOS device and reducing the complexity of the circuit design in a DC-DC converter and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Power devices are widely used in the fields of automobile electronics, consumer electronics and the like, and are mainly used as DC-DC converters, power management, voltage stabilizers and the like. In a traditional DC-DC converter, a laterally-diffused metal oxide semiconductor (LDMOS) is mainly used as a switching circuit. However, a gate drive circuit needs to be connected to the gate of the LDMOS to control the opening and closing of the LDMOS, and the gate drive circuit is very complex, which increases the complexity of the opening and closing operation of the LDMOS and increases the complexity of the circuit design in the DC-DC converter.

[0003] Therefore, how to improve the way of controlling the opening and closing of the LDMOS is a problem to be solved at present. SUMMARY

[0004] The present application aims to provide a semiconductor device and a manufacturing method thereof, so that the gate drive circuit does not need to be connected to the gate layer to control the opening and closing of the LDMOS device, thereby reducing the complexity of the opening and closing operation of the LDMOS device and reducing the complexity of the circuit design in the DC-DC converter and the like.

[0005] To achieve the above-mentioned purpose, the present application provides a semiconductor device, comprising:

[0006] a substrate, the substrate having a first trench isolation structure separating an LDMOS region and a memory device region;

[0007] a gate layer, the gate layer comprising a gate lateral part and a gate longitudinal part connected to each other, the gate lateral part extending from the LDMOS region to the memory device region through the first trench isolation structure, the gate longitudinal part being located in the first trench isolation structure of the LDMOS region, a tunneling oxide layer being interposed between the gate lateral part and the substrate of the memory device region, and a gate oxide layer being interposed between the gate longitudinal part and the substrate of the LDMOS region;

[0008] a drift region formed in the substrate of the LDMOS region;

[0009] a first source region and a first drain region, the first source region being formed in the drift region, and the first drain region being formed in the drift region away from the first source region on a side away from the gate longitudinal part;

[0010] a second source region and a second drain region formed in the substrate on both sides of the gate lateral portion of the memory device region, the second drain region being sandwiched between the gate lateral portion and the second source region with part of the tunnel oxide layer.

[0011] Optionally, the semiconductor device further comprises:

[0012] a first well region formed in the drift region, the first well region surrounding the first source region, the first well region being sandwiched between the gate vertical portion and the first source region with part of the gate oxide layer;

[0013] a second well region formed in the substrate of the memory device region, the second well region surrounding the second source region and the second drain region.

[0014] Optionally, the semiconductor device further comprises:

[0015] a first body contact region formed in the first well region on a side of the first source region away from the gate vertical portion;

[0016] a second body contact region formed in the second well region on a side of the second source region away from the second drain region.

[0017] Optionally, the substrate is an SOI substrate comprising a lower layer substrate, an insulating buried layer and an upper layer semiconductor layer from bottom to top, the first trench isolation structure being connected with the insulating buried layer.

[0018] Optionally, electrodes are formed on the first source region, the first drain region, the first body contact region, the second source region, the second drain region and the second body contact region, and the electrode on the first source region is connected with the electrode on the first body contact region.

[0019] Optionally, a second trench isolation structure is formed between the second body contact region and the second source region.

[0020] Optionally, the second well region and the second body contact region are of N type, the second source region and the second drain region are of P type; when the drift region, the first source region and the first drain region are of P type, the first well region and the first body contact region are of N type; when the drift region, the first source region and the first drain region are of N type, the first well region and the first body contact region are of P type.

[0021] Optionally, the programming of the semiconductor device comprises:

[0022] a first positive voltage is applied to the first source region, a negative voltage is applied to the second drain region, the second source region is floating, and the second body contact region is grounded.

[0023] Optionally, the erasing of the semiconductor device comprises:

[0024] a second positive voltage is applied to the second drain region, the second source region, and the second body contact region, respectively.

[0025] The present application also provides a method for manufacturing a semiconductor device, comprising:

[0026] providing a substrate having a first trench isolation structure separating a LDMOS region and a memory device region;

[0027] forming a drift region in the substrate of the LDMOS region;

[0028] forming a tunnel oxide layer, a gate oxide layer, and a gate layer, the gate layer comprising a gate lateral portion and a gate longitudinal portion connected to each other, the gate lateral portion extending from the LDMOS region to the memory device region through the first trench isolation structure, the gate longitudinal portion being located in the first trench isolation structure of the LDMOS region, the tunnel oxide layer being sandwiched between the gate lateral portion and the substrate of the memory device region, the gate oxide layer being sandwiched between the gate longitudinal portion and the substrate of the LDMOS region;

[0029] forming a first source region and a first drain region in the drift region, the first drain region being formed in the drift region on a side of the first source region away from the gate longitudinal portion, and forming a second source region and a second drain region in the substrate on both sides of the gate lateral portion of the memory device region, the second drain region being sandwiched with a part of the tunnel oxide layer between the second drain region and the gate lateral portion.

[0030] Optionally, after the drift region is formed in the substrate of the LDMOS region and before the tunnel oxide layer, the gate oxide layer, and the gate layer are formed, the method for manufacturing a semiconductor device further comprises:

[0031] forming a first well region in the drift region and a second well region in the substrate of the memory device region, so that the first source region is formed in the first well region, a part of the gate oxide layer is sandwiched between the first well region and the gate longitudinal portion, and the second source region and the second drain region are formed in the second well region.

[0032] Optionally, the method for manufacturing a semiconductor device further comprises:

[0033] forming a first body contact region in the first well region on a side of the first source region away from the gate longitudinal portion;

[0034] forming a second body contact region in the second well region on a side of the second source region away from the second drain region.

[0035] Optionally, the method for manufacturing the semiconductor device further comprises:

[0036] forming electrodes on the first source region, the first drain region, the first body contact region, the second source region, the second drain region and the second body contact region, and the electrode on the first source region is connected with the electrode on the first body contact region.

[0037] Optionally, the steps of forming the tunneling oxide layer, the gate oxide layer and the gate layer comprise:

[0038] etching the first trench isolation structure to form a trench exposing the substrate of the LDMOS region;

[0039] forming a tunneling oxide layer on part of the substrate of the memory device region and a gate oxide layer on the substrate of the LDMOS region exposed by the trench by a thermal oxidation process;

[0040] depositing a gate material on the substrate and the first trench isolation structure, and the gate material fills the trench;

[0041] etching to remove part of the gate material, and the gate material in the trench is reserved as a gate longitudinal portion, and the gate material on the tunneling oxide layer and between the tunneling oxide layer and the trench is reserved as a gate lateral portion.

[0042] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0043] 1. The semiconductor device of the present application, since it comprises a substrate with mutually isolated LDMOS region and memory device region, an LDMOS device is formed in the LDMOS region and a memory device is formed in the memory device region, and the LDMOS device and the memory device share the gate layer, so that the memory device and the LDMOS device are integrated together, and thus the semiconductor device has the non-volatile storage function of the memory device, and at the same time, by applying voltage to the first source region, the first body contact region and the second drain region, so that the electrons pass through the part of the tunneling oxide layer between the second drain region and the gate horizontal part in the gate layer, and then enter the gate horizontal part, so as to enter the gate vertical part in the gate layer, to realize the programming operation, and by applying voltage to the second drain region, the second source region and the second body contact region, so that the electrons are removed from the gate layer, to realize the erasing operation, so that by controlling the number of electrons in the gate layer in the semiconductor device, the on and off control of the LDMOS device can be realized, without connecting the gate driving circuit on the gate layer to control the on and off of the LDMOS device, so that the complexity of the on and off operation of the LDMOS device is reduced, and the complexity of the circuit design in the DC-DC converter and the like is reduced.

[0044] 2. The manufacturing method of the semiconductor device of the present application, by providing mutually isolated LDMOS region and memory device region in the substrate, forming LDMOS device in the LDMOS region and forming memory device in the memory device region, and the LDMOS device and the memory device share the gate layer, so that the memory device and the LDMOS device are integrated together, and thus the semiconductor device has the non-volatile storage function of the memory device, and at the same time, by applying voltage to the first source region, the first body contact region and the second drain region, so that the electrons pass through the part of the tunneling oxide layer between the second drain region and the gate horizontal part in the gate layer, and then enter the gate horizontal part, so as to enter the gate vertical part in the gate layer, to realize the programming operation, and by applying voltage to the second drain region, the second source region and the second body contact region, so that the electrons are removed from the gate layer, to realize the erasing operation, so that by controlling the number of electrons in the gate layer in the semiconductor device, the on and off control of the LDMOS device can be realized, without connecting the gate driving circuit on the gate layer to control the on and off of the LDMOS device, so that the complexity of the on and off operation of the LDMOS device is reduced, and the complexity of the circuit design in the DC-DC converter and the like is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 is the layout of the semiconductor device of an embodiment of the present application;

[0046] Figure 2a is Figure 1 is a sectional view of the semiconductor device shown in FIG. 1 along the direction of AA';

[0047] Figure 2b is Figure 1 is a sectional view of the semiconductor device shown in FIG. 1 along the direction of BB';

[0048] Figure 3 is a flow chart of a manufacturing method of a semiconductor device according to an embodiment of the present application.

[0049] wherein the Figures 1-3 The reference signs in the drawings are explained as follows:

[0050] 111 - lower substrate; 112 - insulating buried layer; 113 - upper semiconductor layer; 12 - first trench isolation structure; 13 - gate layer; 131 - tunneling oxide layer; 132 - gate oxide layer; 151 - first source region; 152 - first drain region; 153 - first body contact region; 154 - first well region; 161 - second source region; 162 - second drain region; 163 - second body contact region; 164 - second well region; 17 - second trench isolation structure; 18 - interlayer dielectric layer; 19 - electrode. DETAILED DESCRIPTION

[0051] In order to make the objects, advantages and features of the present application clearer, the semiconductor device and the manufacturing method thereof according to the present application are further described in detail below with reference to the accompanying drawings. It should be noted that all the drawings are very simplified and all use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0052] An embodiment of the present application provides a semiconductor device, comprising: a substrate having a first trench isolation structure isolating an LDMOS region and a memory device region; a gate layer comprising a gate lateral portion and a gate longitudinal portion connected to each other, the gate lateral portion extending from the LDMOS region to the memory device region through the first trench isolation structure, the gate longitudinal portion being located in the first trench isolation structure of the LDMOS region, a tunneling oxide layer being sandwiched between the gate lateral portion and the substrate of the memory device region, and a gate oxide layer being sandwiched between the gate longitudinal portion and the substrate of the LDMOS region; a drift region formed in the substrate of the LDMOS region; a first source region and a first drain region, the first source region being formed in the drift region, and the first drain region being formed in the drift region on a side of the first source region away from the gate longitudinal portion; a second source region and a second drain region, the second source region and the second drain region being respectively formed in the substrate on both sides of the gate lateral portion of the memory device region, and a part of the tunneling oxide layer being sandwiched between the second drain region and the gate lateral portion.

[0053] Reference will now be made to Figures 1-2b The semiconductor device provided by the embodiment will be described in more detail.

[0054] The substrate has an LDMOS region A1 and a memory device region A2 isolated from each other. LDMOS refers to lateral diffusion metal oxide semiconductor, and the memory device region A2 is used to form a memory device such as EEPROM, which refers to electrically erasable programmable non-volatile memory.

[0055] The substrate can be a bulk substrate or an SOI (Semiconductor On Insulator) substrate, such as a substrate commonly used in the semiconductor field, for example, silicon, germanium, etc. The following embodiment takes the SOI substrate as an example, which includes a lower substrate 111, an insulating buried layer 112 and an upper semiconductor layer 113 from bottom to top, for example, a silicon-on-insulator or germanium-on-insulator substrate.

[0056] The LDMOS region A1 and the memory device region A2 are isolated by a first trench isolation structure 12, that is, the LDMOS region A1 and the memory device region A2 are both surrounded by the first trench isolation structure 12.

[0057] When the substrate is an SOI substrate, the first trench isolation structure 12 is preferably connected to the insulating buried layer 112.

[0058] The first trench isolation structure 12 in the LDMOS region A1 close to the substrate side has a trench (not shown) formed therein, and the side wall of the trench exposes the substrate of the LDMOS region A1.

[0059] The drift region 14 is formed in the substrate of the LDMOS region A1, and the drift region 14 is in contact with the side wall of the trench.

[0060] In addition, when the substrate is an SOI substrate, the drift region 14 is formed in the upper semiconductor layer 113 of the side wall of the trench.

[0061] The gate layer 13 includes a connected gate lateral part and a gate longitudinal part, the gate lateral part extends from the LDMOS region A1 to the memory device region A2 through the first trench isolation structure 12, and the gate longitudinal part is located in the trench of the first trench isolation structure 12, which serves as a slot gate of the LDMOS. The gate lateral part and the substrate of the memory device region A2 are sandwiched by a tunneling oxide layer 131, and the gate longitudinal part and the substrate of the LDMOS region A1 are sandwiched by a gate oxide layer 132, which are formed by thermal oxidation.

[0062] When the memory device region A2 is used to form an EEPROM device, since only one layer of the gate lateral part is formed as a gate on the memory device region A2, a single-layer gate EEPROM device is formed in the memory device region A2.

[0063] Preferably, the thickness of the gate oxide layer 132 is, for example, The thickness of the gate oxide layer 132 is selected according to the working voltage of the LDMOS.

[0064] Preferably, the thickness of the tunneling oxide layer 131 is, for example,

[0065] The semiconductor device further comprises:

[0066] The first well region 154 is formed in the drift region 14, and the first well region 154 is in contact with the sidewall of the trench, and part of the gate oxide layer 132 is sandwiched between the first well region 154 and the gate longitudinal part; wherein the bottom surface of the first well region 154 is higher than the bottom surface of the gate longitudinal part.

[0067] The second well region 164 is formed in the substrate of the memory device region A2, and when the substrate is an SOI substrate, the second well region 164 is formed in the upper semiconductor layer 113 of the memory device region A2.

[0068] In the LDMOS region A1, the first source region 151 is formed in the first well region 154 on one side of the trench, and the first drain region 152 is formed in the drift region 14 on the side of the first source region 151 away from the gate longitudinal part; wherein the first source region 151 is in contact with the sidewall of the trench.

[0069] In the memory device region A2, the second source region 161 and the second drain region 162 are respectively formed in the substrate on both sides of the gate lateral part of the memory device region A2, the second well region 164 surrounds the second source region 161 and the second drain region 162, and part of the tunneling oxide layer 131 is sandwiched between the second source region 161 and the gate lateral part and between the second drain region 162 and the gate lateral part, i.e. in the direction perpendicular to the top surface of the substrate, the second source region 161 overlaps part of the region of the gate lateral part, and the second drain region 162 overlaps part of the region of the gate lateral part.

[0070] The semiconductor device further comprises:

[0071] The first body contact region 153 is formed in the first well region 154 on the side of the first source region 151 away from the gate longitudinal portion. Figure 2a The first body contact region 153 and the first drain region 152 are not in contact with each other; compared with the lack of contact between the first source region 151 and the first body contact region 153, the contact between the first source region 151 and the first body contact region 153 can reduce the device area and form a source-body butted contact. In addition, the boundary of the first body contact region 153 away from the gate longitudinal portion can be flush with the boundary of the first well region 154 away from the gate longitudinal portion; or, the boundary of the first body contact region 153 away from the gate longitudinal portion is closer to the gate longitudinal portion than the boundary of the first well region 154 away from the gate longitudinal portion, that is, the first well region 154 surrounds the first body contact region 153.

[0072] The second body contact region 163 is formed in the second well region 164 on a side of the second source region 161 away from the second drain region 162 .

[0073] Furthermore, a second trench isolation structure 17 is formed between the second body contact region 163 and the second source region 161, isolating the second body contact region 163 from the second source region 161. Furthermore, a second trench isolation structure 17 is formed on top of the second well region 164, surrounding the second source region 161, the second drain region 162, and the second body contact region 163. This second trench isolation structure 17 is connected to the second trench isolation structure 17 between the second body contact region 163 and the second source region 161. When the substrate is an SOI substrate, the first trench isolation structure 12 is preferably connected to the buried insulating layer 112, and the bottom surface of the second trench isolation structure 17 is higher than the bottom surface of the first trench isolation structure 12.

[0074] Moreover, in the LDMOS region A1, the first well region 154 below the first source region 151 is the channel region, and the boundary region between the first well region 154 and the longitudinal portion of the gate forms the longitudinal channel of the LDMOS; in the memory device region A2, the region below the lateral portion of the gate and between the second source region 161 and the second drain region 162 is the channel region.

[0075] In addition, the semiconductor device further comprises:

[0076] a metal silicide layer (not shown) formed on the first source region 151, the first drain region 152, the first body contact region 153, the second source region 161, the second drain region 162 and the second body contact region 163, and the metal silicide layer on the first source region 151 is connected with the metal silicide layer on the first body contact region 153; the metal in the metal silicide layer can include one or more than two combinations of tungsten, iron, nickel, cobalt, platinum and titanium;

[0077] an interlayer dielectric layer 18 formed on the substrate;

[0078] a plurality of electrodes 19 formed in the interlayer dielectric layer 18 on the first source region 151, the first drain region 152, the first body contact region 153, the second source region 161, the second drain region 162 and the second body contact region 163, and the electrode 19 on the first source region 151 is connected with the electrode 19 on the first body contact region 153, the top surface of the interlayer dielectric layer 18 exposes each of the electrodes 19 and exposes the gate layer, and each of the electrodes 19 and the gate layer are insulated and separated by the interlayer dielectric layer 18.

[0079] In addition, when the substrate is an SOI substrate, the doping type of the lower substrate 111 is P type, and the doping type of the upper semiconductor layer 113 is N type.

[0080] The doping type of the second well region 164 and the second body contact region 163 is N type, and the doping type of the second source region 161 and the second drain region 162 is P type, at this time, the memory device formed in the memory device region A2 is equivalent to a PMOS device.

[0081] When the doping type of the drift region 14, the first source region 151 and the first drain region 152 is P type, the doping type of the first well region 154 and the first body contact region 153 is N type, at this time, the LDMOS device formed in the LDMOS region A1 is a PLDMOS device; when the doping type of the drift region 14, the first source region 151 and the first drain region 152 is N type, the doping type of the first well region 154 and the first body contact region 153 is P type, at this time, the LDMOS device formed in the LDMOS region A1 is a NLDMOS device.

[0082] The semiconductor device of the present application, due to comprising a substrate with mutually isolated LDMOS region A1 and memory device region A2, an LDMOS device is formed in the LDMOS region A1 and a memory device is formed in the memory device region A2, and the LDMOS device and the memory device share the gate layer 13, so that the memory device and the LDMOS device are integrated together, and further so that the semiconductor device has the non-volatile storage function of the memory device, and at the same time, by applying voltage to the first source region 151, the first body contact region 153 and the second drain region 162 so that the electrons pass through the part of the tunneling oxide layer 131 sandwiched between the second drain region 162 and the gate transverse part in the gate layer 13, then enter the gate longitudinal part in the gate layer 13 to realize the programming operation, and by applying voltage to the second drain region 162, the second source region 161 and the second body contact region 163 so that the electrons move away from the gate layer 13 to realize the erasing operation, so that the opening and closing control of the LDMOS device can be realized by controlling the number of electrons in the gate layer 13 in the semiconductor device, without the need to connect a gate drive circuit on the gate layer 13 to control the opening and closing of the LDMOS device, so that the complexity of the opening and closing operation of the LDMOS device is reduced, and the complexity of the circuit design in the DC-DC converter and the like is reduced.

[0083] And, since only one layer of the gate layer 13 is formed as the gate in the LDMOS region A1 and the memory device region A2 to realize the programming operation and the erasing operation, compared with forming a floating gate layer and a control gate layer as the gate, the process is simplified.

[0084] The step of performing the programming operation on the semiconductor device comprises:

[0085] A common first positive voltage is applied to the first source region 151 and the first body contact region 153, and a negative voltage is applied to the second drain region 162, the second source region 161 is floating (i.e. the second source region 161 is not connected in the circuit), and the second body contact region 163 is grounded, to perform the programming operation on the semiconductor device.

[0086] Among them, since the electrode 19 on the first source region 151 is connected with the electrode 19 on the first body contact region 153, i.e. the first source region 151 and the first body contact region 153 share the same electrode 19, the first positive voltage is applied to the first source region 151 and the first body contact region 153 through the shared electrode 19; and the negative voltage is applied to the second drain region 162 through the electrode 19 on the second drain region 162.

[0087] When the first positive voltage is applied to the first source region 151 and the first body contact region 153, the gate layer 13 is coupled with a positive voltage through the gate oxide layer 132, and the positive voltage is the product of the first positive voltage and a coupling coefficient. Preferably, the coupling coefficient ranges from 0.6 to 0.8 when the first positive voltage is coupled to the gate layer 13.

[0088] Preferably, the first positive voltage ranges from 5V to 10V.

[0089] Preferably, the negative voltage ranges from -8V to -5.5V.

[0090] Since the LDMOS region A1 and the memory device region A2 share the gate layer 13, and the memory device region A2 is equivalent to a PMOS device with no gate terminal, by applying a negative voltage to the second drain region 162 in the PMOS device, and floating the second source region 161 and grounding the second body contact region 163, the second drain region 162 and the gate layer 13 in the direction perpendicular to the top surface of the substrate have a band-to-band tunneling hot electron programming in the overlapping area, and the electrons enter the gate layer 13 through the part of the tunneling oxide layer 131 between the second drain region 162 and the gate transverse part in the gate layer 13, and then enter the gate longitudinal part in the gate layer 13, thereby controlling the channel inversion of the LDMOS device in the LDMOS region A1, and enabling the LDMOS device.

[0091] The step of performing the erase operation on the semiconductor device comprises:

[0092] The second positive voltage is applied to the second drain region 162, the second source region 161 and the second body contact region 163 to perform the erase operation on the semiconductor device. Under the action of the high second positive voltage, the PMOS device in the memory device region A2 has a uniform channel FN (Fowler-Nordheim) tunneling effect, so that the electrons are removed from the gate layer 13, and the LDMOS device is turned off.

[0093] Preferably, the second positive voltage ranges from 7.8V to 10V.

[0094] From the above, it can be seen that the programming operation and the erase operation on the semiconductor device are both realized by external voltage application, and by adjusting the applied voltage, the number of electrons in the gate layer 13 can be adjusted, and the degree of channel inversion can be adjusted, so that the threshold voltage of the LDMOS device can be continuously adjustable, and the controllability of the threshold voltage of the LDMOS device is better, and the perfect integration of the EEPROM device and the LDMOS device is realized.

[0095] In summary, the semiconductor device provided by the present application comprises: a substrate having a first trench isolation structure separating an LDMOS region and a memory device region; a gate layer comprising a gate lateral portion and a gate longitudinal portion connected together, the gate lateral portion extending from the LDMOS region through the first trench isolation structure to the memory device region, and the gate longitudinal portion being located in the first trench isolation structure of the LDMOS region, the gate lateral portion being sandwiched by a tunneling oxide layer and the substrate of the memory device region, and the gate longitudinal portion being sandwiched by a gate oxide layer and the substrate of the LDMOS region; a drift region formed in the substrate of the LDMOS region; a first source region formed in the drift region, and a first drain region formed in the drift region on a side of the first source region away from the gate longitudinal portion; and a second source region and a second drain region formed in the substrate on both sides of the gate lateral portion of the memory device region, the second drain region being sandwiched by a part of the tunneling oxide layer and the gate lateral portion. The semiconductor device provided by the present application makes it unnecessary to connect a gate drive circuit to the gate to control the on and off of the LDMOS device, thereby reducing the complexity of the on and off operation of the LDMOS device and the complexity of the circuit design in a DC-DC converter and the like.

[0096] An embodiment of the present application provides a manufacturing method of a semiconductor device, referring to Figure 3 , Figure 3 is a flowchart of the manufacturing method of the semiconductor device of an embodiment of the present application, and the manufacturing method of the semiconductor device comprises:

[0097] Step S1, providing a substrate having a first trench isolation structure separating an LDMOS region and a memory device region;

[0098] Step S2, forming a drift region in the substrate of the LDMOS region;

[0099] Step S3, forming a tunneling oxide layer, a gate oxide layer and a gate layer, the gate layer comprising a gate lateral portion and a gate longitudinal portion connected together, the gate lateral portion extending from the LDMOS region through the first trench isolation structure to the memory device region, and the gate longitudinal portion being located in the first trench isolation structure of the LDMOS region, the tunneling oxide layer being sandwiched between the gate lateral portion and the substrate of the memory device region, and the gate oxide layer being sandwiched between the gate longitudinal portion and the substrate of the LDMOS region;

[0100] Step S4, forming a first source region and a first drain region in the drift region, the first source region being formed in the drift region on a side of the first source region away from the gate longitudinal portion; and forming a second source region and a second drain region in the substrate on two sides of the gate lateral portion of the memory device region, the second drain region being sandwiched between the second source region and the gate lateral portion with part of the tunneling oxide layer.

[0101] Reference will now be made to Figures 1-2b A method for manufacturing a semiconductor device is provided in the embodiment.

[0102] According to step S1, a substrate is provided, the substrate having an LDMOS region A1 and a memory device region A2 isolated from each other. LDMOS refers to lateral diffusion metal oxide semiconductor, and the memory device region A2 is used for forming a memory device such as EEPROM, which refers to electrically erasable programmable non-volatile memory.

[0103] The substrate can be a bulk substrate or an SOI (Semiconductor On Insulator) substrate, the bulk substrate being commonly used in the semiconductor field, such as silicon, germanium, etc. The following embodiment takes the SOI substrate as an example, which includes a lower substrate 111, an insulating buried layer 112 and an upper semiconductor layer 113 from bottom to top, such as a silicon-on-insulator or germanium-on-insulator substrate.

[0104] The LDMOS region A1 and the memory device region A2 are isolated by a first trench isolation structure 12, that is, the LDMOS region A1 and the memory device region are both surrounded by the first trench isolation structure 12.

[0105] When the substrate is an SOI substrate, the first trench isolation structure 12 is preferably connected to the insulating buried layer 112.

[0106] According to step S2, a drift region 14 is formed in the substrate of the LDMOS region A1.

[0107] The drift region 14 is formed in the substrate of the LDMOS region A1 by ion implantation process.

[0108] When the substrate is an SOI substrate, the drift region 14 is formed in the upper semiconductor layer 113 of the trench sidewall.

[0109] According to step S3, a tunneling oxide layer 131, a gate oxide layer 132 and a gate layer 13 are formed, the gate layer 13 including a gate lateral portion and a gate longitudinal portion connected to each other, the gate lateral portion extending from the LDMOS region Al to the memory device region A2 through the first trench isolation structure 12, and the gate longitudinal portion being located in the first trench isolation structure 12 and serving as a trench gate of the LDMOS.

[0110] The tunneling oxide layer 131 is sandwiched between the gate lateral portion and the substrate of the memory device region A2, and the gate oxide layer 132 is sandwiched between the gate longitudinal portion and the substrate of the LDMOS region Al.

[0111] Before the tunneling oxide layer 131, the gate oxide layer 132 and the gate layer 13 are formed, a trench (not shown) can be formed in the first trench isolation structure 12 near the substrate side of the LDMOS region Al, a sidewall of the trench exposing the substrate of the LDMOS region Al, and the drift region 14 being in contact with the sidewall of the trench. The trench can be formed before or after the drift region 14 is formed.

[0112] The step of forming the tunneling oxide layer 131, the gate oxide layer 132 and the gate layer 13 can include the following steps: first, a thermal oxidation process is used to form the tunneling oxide layer 131 on part of the substrate 111 of the memory device region A2 and to form the gate oxide layer 132 on the sidewall of the trench exposing the substrate of the LDMOS region Al; then, a gate material is deposited on the substrate 111, and the gate material fills the trench; then, part of the gate material is etched away, and the gate material in the trench, the gate material on the tunneling oxide layer 131 and the gate material in the region between the trench and the tunneling oxide layer 131 are reserved as the gate layer 13, the gate material in the trench serving as the gate longitudinal portion, and the gate material on the tunneling oxide layer 131 and the gate material in the region between the trench and the tunneling oxide layer 131 serving as the gate lateral portion. In an embodiment, the gate material is polysilicon.

[0113] When the memory device region A2 is used to form an EEPROM device, since only one layer of the gate lateral portion is formed on the memory device region A2 as a gate, a single-layer gate EEPROM device is formed in the memory device region A2, and further, a single-layer polysilicon EEPROM device is formed.

[0114] Preferably, the thickness of the gate oxide layer 132 is, for example, The thickness of the gate oxide layer 132 is selected according to the working voltage of the LDMOS.

[0115] Preferably, the thickness of the tunneling oxide layer 131 is

[0116] In addition, after forming the drift region 14 in the substrate of the LDMOS region A1 and before forming the tunneling oxide layer 131, the gate oxide layer 132 and the gate electrode layer 13, the manufacturing method of the semiconductor device further comprises:

[0117] The first well region 154 is formed in the drift region 14 and the second well region 164 is formed in the substrate of the memory device region A2 by ion implantation. The first well region 154 contacts the sidewall of the trench, the first well region 154 is sandwiched by the gate vertical portion and part of the gate oxide layer 132, and the bottom surface of the first well region 154 is higher than the bottom surface of the gate vertical portion. When the substrate is an SOI substrate, the second well region 164 is formed in the upper semiconductor layer 113 of the memory device region A2.

[0118] According to step S4, the first source region 151 and the first drain region 152 are formed, and the second source region 161 and the second drain region 162 are formed by ion implantation.

[0119] In the LDMOS region A1, the first source region 151 is formed in the first well region 154 on one side of the trench, and the first drain region 152 is formed in the drift region 14 away from the gate vertical portion of the first source region 151. The first source region 151 contacts the sidewall of the trench.

[0120] In the memory device region A2, the second source region 161 and the second drain region 162 are formed in the substrate on both sides of the gate horizontal portion of the memory device region A2, respectively. The second well region 164 surrounds the second source region 161 and the second drain region 162, and part of the tunneling oxide layer 131 is sandwiched between the second source region 161 and the gate horizontal portion and between the second drain region 162 and the gate horizontal portion, i.e. the second source region 161 and the gate horizontal portion partially overlap in the direction perpendicular to the top surface of the substrate, and the second drain region 162 and the gate horizontal portion partially overlap.

[0121] The manufacturing method of the semiconductor device further comprises:

[0122] The first body contact region 153 is formed in the first well region 154 away from the gate vertical portion of the first source region 151. The first source region 151 contacts the first body contact region 153 (e.g. the first source region 151 and the first body contact region 153 are in the same plane). Figure 2aThe first body contact region 153 and the first drain region 152 are not in contact with each other; compared to the lack of contact between the first source region 151 and the first body contact region 153, contact between the first source region 151 and the first body contact region 153 can reduce the device area. Furthermore, the boundary of the first body contact region 153 away from the gate longitudinal portion can be flush with the boundary of the first well region 154 away from the gate longitudinal portion; alternatively, the boundary of the first body contact region 153 away from the gate longitudinal portion is closer to the gate longitudinal portion than the boundary of the first well region 154 away from the gate longitudinal portion.

[0123] A second body contact region 163 is formed in the second well region 164 on a side of the second source region 161 away from the second drain region 162 .

[0124] Furthermore, a second trench isolation structure 17 is formed between the second body contact region 163 and the second source region 161, thereby isolating the second body contact region 163 from the second source region 161. Furthermore, a second trench isolation structure 17 is also formed on the top of the second well region 164, surrounding the second source region 161, the second drain region 162, and the second body contact region 163. This second trench isolation structure 17 is connected to the second trench isolation structure 17 between the second body contact region 163 and the second source region 161. The bottom surface of the second trench isolation structure 17 is higher than the bottom surface of the first trench isolation structure 12.

[0125] Moreover, in the LDMOS region A1, the first well region 154 below the first source region 151 is the channel region, and the boundary region between the first well region 154 and the longitudinal portion of the gate forms the longitudinal channel of the LDMOS; in the memory device region A2, the region below the lateral portion of the gate and between the second source region 161 and the second drain region 162 is the channel region.

[0126] The method for manufacturing the semiconductor device further includes:

[0127] forming a metal silicide layer (not shown) on the first source region 151, the first drain region 152, the first body contact region 153, the second source region 161, the second drain region 162, and the second body contact region 163, with the metal silicide layer on the first source region 151 connected to the metal silicide layer on the first body contact region 153; the metal in the metal silicide layer may include one or a combination of two or more of tungsten, iron, nickel, cobalt, platinum, and titanium;

[0128] forming an interlayer dielectric layer 18 on the substrate;

[0129] A plurality of electrodes 19 are formed in the interlayer dielectric layer 18 on the first source region 151, the first drain region 152, the first body contact region 153, the second source region 161, the second drain region 162 and the second body contact region 163, and the electrode 19 on the first source region 151 is connected with the electrode 19 on the first body contact region 153, the top surface of the interlayer dielectric layer 18 exposes each of the electrodes 19 and exposes the gate layer 13, and each of the electrodes 19 and the gate layer 13 are insulated and separated by the interlayer dielectric layer 18.

[0130] In addition, when the substrate is an SOI substrate, the doping type of the lower substrate 111 is P type, and the doping type of the upper semiconductor layer 113 is N type.

[0131] The doping type of the second well region 164 and the second body contact region 163 is N type, and the doping type of the second source region 161 and the second drain region 162 is P type, at this time, the memory device formed in the memory device region A2 is equivalent to a PMOS device.

[0132] When the doping type of the drift region 14, the first source region 151 and the first drain region 152 is P type, the doping type of the first well region 154 and the first body contact region 153 is N type, at this time, the LDMOS device formed in the LDMOS region A1 is a PLDMOS device; when the doping type of the drift region 14, the first source region 151 and the first drain region 152 is N type, the doping type of the first well region 154 and the first body contact region 153 is P type, at this time, the LDMOS device formed in the LDMOS region A1 is a NLDMOS device.

[0133] The manufacturing method of the semiconductor device of the present application integrates the memory device and the LDMOS device together by setting the LDMOS region A1 and the memory device region A2 apart from each other in the substrate, forming the LDMOS device in the LDMOS region A1 and forming the memory device in the memory device region A2, and making the LDMOS device and the memory device share the gate layer 13, so that the semiconductor device has the non-volatile storage function of the memory device, and can also realize the programming operation by applying voltage to the first source region 151, the first body contact region 153 and the second drain region 162 so that the electrons enter the gate vertical part in the gate layer 13 through the part of the tunneling oxide layer 131 between the second drain region 162 and the gate horizontal part in the gate layer 13, and then enter the gate vertical part in the gate layer 13, and realizes the erasing operation by applying voltage to the second drain region 162, the second source region 161 and the second body contact region 163 so that the electrons move away from the gate layer 13, so that the opening and closing of the LDMOS device can be controlled by controlling the number of electrons in the gate layer 13 in the semiconductor device, without connecting the gate driving circuit to the gate layer 13 to control the opening and closing of the LDMOS device, so that the complexity of the opening and closing operation of the LDMOS device is reduced, and the complexity of the circuit design in the DC-DC converter and the like is reduced.

[0134] And since only one layer of the gate layer 13 is formed as the gate in the LDMOS region A1 and the memory device region A2 to realize the programming operation and the erasing operation, compared with forming the floating gate layer and the control gate layer as the gate, the process is simplified.

[0135] In summary, the semiconductor device manufacturing method provided by the present application comprises: providing a substrate, the substrate having a first trench isolation structure separating an LDMOS region and a memory device region; forming a drift region in the substrate of the LDMOS region; forming a tunneling oxide layer, a gate oxide layer and a gate layer, the gate layer comprising a gate lateral part and a gate longitudinal part connected together, the gate lateral part extending from the LDMOS region to the memory device region through the first trench isolation structure, the gate longitudinal part being located in the first trench isolation structure of the LDMOS region, the tunneling oxide layer being sandwiched between the gate lateral part and the substrate of the memory device region, the gate oxide layer being sandwiched between the gate longitudinal part and the substrate of the LDMOS region; forming a first source region and a first drain region, and forming a second source region and a second drain region, the first source region being formed in the drift region, the first drain region being formed in the drift region on the side of the first source region away from the gate longitudinal part; the second source region and the second drain region being formed in the substrate on both sides of the gate lateral part of the memory device region, the second drain region being sandwiched with part of the tunneling oxide layer between the second drain region and the gate lateral part. The semiconductor device manufacturing method of the present application makes it unnecessary to connect a gate drive circuit on the gate to control the opening and closing of the LDMOS device, thereby reducing the complexity of the opening and closing operation of the LDMOS device and reducing the complexity of the circuit design in the DC-DC converter and the like.

[0136] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application in any way. Any modification or change made by a person of ordinary skill in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate having a first trench isolation structure separating a LDMOS region and a memory device region; a gate layer comprising a gate lateral portion and a gate longitudinal portion, the gate lateral portion extending from the LDMOS region to the memory device region through the first trench isolation structure, the gate longitudinal portion being in the first trench isolation structure of the LDMOS region, a tunneling oxide layer being between the gate lateral portion and the substrate of the memory device region, a gate oxide layer being between the sidewall of the gate longitudinal portion and the substrate of the LDMOS region; a drift region formed in the substrate of the LDMOS region; a first source region formed in the drift region, and a first drain region formed in the drift region away from the first source region; a second source region and a second drain region formed in the substrate of the memory device region on both sides of the gate lateral portion, the second drain region being separated from the gate lateral portion by a part of the tunneling oxide layer.

2. The semiconductor device of claim 1, wherein, The semiconductor device further comprises: a first well region formed in the drift region, the first well region surrounding the first source region, a part of the gate oxide layer being between the first well region and the gate longitudinal portion; a second well region formed in the substrate of the memory device region, the second well region surrounding the second source region and the second drain region.

3. The semiconductor device of claim 2, wherein, The semiconductor device further comprises: a first body contact region formed in the first well region away from the first source region; a second body contact region formed in the second well region away from the second drain region.

4. The semiconductor device of claim 1, wherein, The substrate is an SOI substrate comprising a lower layer substrate, an insulating buried layer and an upper layer semiconductor layer, the first trench isolation structure being connected with the insulating buried layer.

5. The semiconductor device of claim 3, wherein, Electrodes are formed on the first source region, the first drain region, the first body contact region, the second source region, the second drain region and the second body contact region, and the electrode on the first source region is connected with the electrode on the first body contact region.

6. The semiconductor device of claim 3, wherein, A second trench isolation structure is formed between the second body contact region and the second source region.

7. The semiconductor device of claim 3, wherein, The second well region and the second body contact region are N-type, the second source region and the second drain region are P-type, the first well region and the first body contact region are N-type when the drift region, the first source region and the first drain region are P-type, and the first well region and the first body contact region are P-type when the drift region, the first source region and the first drain region are N-type.

8. The semiconductor device of claim 3, wherein, The programming of the semiconductor device comprises: applying a first positive voltage to the first source region, applying a negative voltage to the second drain region, the second source region being floating, and the second body contact region being grounded.

9. The semiconductor device of claim 3, wherein, The erasing of the semiconductor device comprises: applying a second positive voltage to the second drain region, the second source region and the second body contact region respectively.

10. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: A substrate is provided, the substrate having a first trench isolation structure separating a LDMOS region and a memory device region; forming a drift region in the substrate of the LDMOS region; forming a tunneling oxide layer, a gate oxide layer and a gate layer, the gate layer including a gate lateral portion and a gate vertical portion connected together, the gate lateral portion extending from the LDMOS region through the first trench isolation structure to the memory device region, the gate vertical portion being in the first trench isolation structure of the LDMOS region, the tunneling oxide layer being sandwiched between the gate lateral portion and the substrate of the memory device region, the gate oxide layer being sandwiched between a sidewall of the gate vertical portion and the substrate of the LDMOS region; forming a first source region and a first drain region in the drift region, the first source region being formed in the first well region, the first drain region being formed in the drift region on a side of the first source region away from the gate vertical portion; and forming a second source region and a second drain region in the substrate on both sides of the gate lateral portion of the memory device region, the second drain region being sandwiched with a portion of the tunneling oxide layer between the second drain region and the gate lateral portion.

11. The method of manufacturing a semiconductor device according to Claim 10, wherein After forming the drift region in the substrate of the LDMOS region and before forming the tunneling oxide layer, the gate oxide layer and the gate layer, the method further comprises: forming a first well region in the drift region and a second well region in the substrate of the memory device region, such that the first source region is formed in the first well region, a portion of the gate oxide layer is sandwiched between the first well region and the gate vertical portion, and the second source region and the second drain region are formed in the second well region.

12. The method of manufacturing a semiconductor device according to Claim 11, wherein The method further comprises: forming a first body contact region in the first well region on a side of the first source region away from the gate vertical portion; forming a second body contact region in the second well region on a side of the second source region away from the second drain region.

13. The method of manufacturing a semiconductor device according to Claim 12, wherein The method further comprises: forming electrodes on the first source region, the first drain region, the first body contact region, the second source region, the second drain region and the second body contact region, and the electrode on the first source region is connected to the electrode on the first body contact region.

14. The method of manufacturing a semiconductor device according to Claim 10, wherein The steps of forming the tunneling oxide layer, the gate oxide layer and the gate layer include: etching the first trench isolation structure to form a trench exposing the substrate of the LDMOS region; forming a tunneling oxide layer on a portion of the substrate of the memory device region and a gate oxide layer on the substrate of the LDMOS region exposed by the trench using a thermal oxidation process; depositing a gate material on the substrate and the first trench isolation structure, and the gate material filling the trench; etching to remove a portion of the gate material, leaving the gate material in the trench as the gate vertical portion, and leaving the gate material on the tunneling oxide layer and between the tunneling oxide layer and the trench as the gate lateral portion.

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