Wafer, semiconductor device, and method for manufacturing the same

Abstract

Provided are a wafer capable of improving characteristics, a semiconductor device, and a manufacturing method thereof. According to an embodiment, a wafer includes a substrate and a crystalline layer. The substrate includes a plurality of SiC regions including SiC and SiC inter-regions provided between the plurality of SiC regions and including Si. The crystalline layer includes a first layer including SiC and a first intermediate layer including SiC provided in a first direction between the substrate and the first layer. The first layer includes nitrogen at a first layer concentration. A first intermediate layer concentration of nitrogen in the first intermediate layer is higher than the first concentration.

Description

[0001] This application is based on Japanese Patent Application 2021-141053 (filed on August 31, 2021), and enjoys priority therefrom. This application incorporates the entire contents of that application by reference. Technical Field

[0002] The embodiments of the present invention relate to wafers, semiconductor devices, methods for manufacturing wafers, and methods for manufacturing semiconductor devices. Background Technology

[0003] In wafers used for manufacturing semiconductor devices, it is desirable to improve their characteristics. Summary of the Invention

[0004] Embodiments of the present invention provide wafers capable of improving performance, semiconductor devices, methods for manufacturing wafers, and methods for manufacturing semiconductor devices.

[0005] According to an embodiment of the present invention, a wafer includes a substrate and a crystalline layer. The substrate includes a plurality of SiC regions comprising SiC and inter-SiC regions disposed between the plurality of SiC regions and comprising Si. The crystalline layer includes a first layer comprising SiC and a first intermediate layer comprising SiC disposed in a first direction between the substrate and the first layer. The first layer comprises nitrogen at a first layer concentration. The first intermediate layer concentration of nitrogen in the first intermediate layer is higher than the first concentration.

[0006] Based on the wafer with the above structure, it is possible to provide a wafer with improved characteristics, a semiconductor device, a method for manufacturing the wafer, and a method for manufacturing the semiconductor device. Attached Figure Description

[0007] Figure 1 (a) and Figure 1 (b) is a schematic cross-sectional view illustrating the first embodiment of the wafer.

[0008] Figure 2 This is a graph illustrating the characteristics of a wafer.

[0009] Figure 3 (a) and Figure 3 (b) is a graph illustrating the characteristics of a wafer.

[0010] Figure 4 (a) and Figure 4 (b) is a graph illustrating the characteristics of a wafer.

[0011] Figure 5 (a) and Figure 5 (b) is a graph illustrating the characteristics of a wafer.

[0012] Figure 6This is a graph illustrating the characteristics of a wafer.

[0013] Figure 7 (a) and Figure 7 (b) is a schematic cross-sectional view illustrating the first embodiment of the wafer.

[0014] Figure 8 (a)~ Figure 8 (c) is a schematic cross-sectional view illustrating a wafer manufacturing method according to the second embodiment.

[0015] Figure 9 (a)~ Figure 9 (c) is a schematic cross-sectional view illustrating a wafer manufacturing method according to the second embodiment.

[0016] Figure 10 (a)~ Figure 10 (c) is a schematic cross-sectional view illustrating a wafer manufacturing method according to the second embodiment.

[0017] Figure 11 (a)~ Figure 11 (c) is a schematic cross-sectional view illustrating a wafer manufacturing method according to the second embodiment.

[0018] Figure 12 (a)~ Figure 12 (c) is a schematic cross-sectional view illustrating a wafer manufacturing method according to the second embodiment.

[0019] Figure 13 This is a graph illustrating the characteristics related to the manufacturing method of the semiconductor device in the embodiment.

[0020] Figure 14 (a)~ Figure 14 (d) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the third embodiment.

[0021] Figure 15 (a)~ Figure 15 (c) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the third embodiment.

[0022] Figure 16 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0023] Figure 17 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0024] Figure 18 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0025] Figure 19 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0026] Figure 20 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0027] Figure 21 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0028] (Symbol Explanation)

[0029] 10L: Crystalline layer; 10a, 10b: First and second SiC regions; 10p: SiC region; 10q: Inter-SiC region; 10s: Substrate; 10sa, 10sb: First and second substrate portions; 10sp: One portion; 10sq: Another portion; 11: First layer; 11B: Intermediate region; 11F: (11-21) plane; 11a, 11b: First and second partial regions; 12-15: Second to fifth semiconductor regions; 12A: Termination region; 12p: One portion; 12q: Another portion; 51-53: First to third electrodes; 51M: Conductive material; 61: First inter-SiC layer Intermediate layer; 61a~61c: First~Third layered regions; 61d: Altered region; 61s: First intermediate layer substrate; 62: Second intermediate layer; 65: Supporting component; 66: Resin layer; 68: Electromagnetic wave; 69: Ion; 69B: First element; 81, 82: First and second insulating components; θ1: Angle; 110, 110A~110D, 111~113: Semiconductor device; 210, 211: Wafer; C1: Concentration; L1: Length; Pm1: Curvature parameter; Pm2: Maximum value; RR1: Thickness ratio; Ra: Surface roughness; t0: Thickness; t1~t4: First~Fourth thickness Detailed Implementation

[0030] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0031] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc., may not be the same as the actual situation. Even when representing the same part, the dimensions and ratios of each other may sometimes be shown differently due to different accompanying drawings.

[0032] In this application specification and the various figures, for existing figures, the same symbols are added to the elements that are the same as those mentioned above, and detailed descriptions are appropriately omitted.

[0033] (First Implementation)

[0034] Figure 1 (a) and Figure 1 (b) is a schematic cross-sectional view illustrating the first embodiment of the wafer.

[0035] Figure 1 (b) is Figure 1 (a) is a magnified view of a portion thereof.

[0036] like Figure 1 As shown in (a), the wafer 210 of the embodiment includes a substrate 10s and a crystal layer 10L. The crystal layer 10L includes a first layer 11 and a first intermediate layer 61. For example, the crystal layer 10L is in contact with the substrate 10s.

[0037] A first intermediate layer 61 is disposed between the substrate 10s and the first layer 11 in a first direction. For example... Figure 1 As shown in (a), the first direction from the first intermediate layer 61 toward the first layer 11 is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction.

[0038] The substrate 10s extends along the X-Y plane. The first intermediate layer 61 and the first layer 11 are, for example, along the X-Y plane. For example, the first intermediate layer 61 is in contact with the substrate 10s.

[0039] like Figure 1 As shown in (b), the substrate 10s includes multiple SiC regions 10p and inter-SiC regions 10q. The multiple SiC regions 10p contain SiC. The inter-SiC regions 10q are disposed between the multiple SiC regions 10p. The inter-SiC regions 10q contain Si. For example, the substrate 10s may be a sintered substrate containing Si and Si-C. For example, Si may be filled between the multiple SiC regions 10p. The inter-SiC regions 10q may be, for example, in a network structure. The substrate 10s may be, for example, a Si-impregnated SiC sintered substrate. Such a substrate 10s exhibits excellent heat resistance. It is easy to perform processing such as grinding on such a substrate 10s.

[0040] In this example, the plurality of SiC regions 10p includes a plurality of first SiC regions 10a and a plurality of second SiC regions 10b. One dimension of the plurality of first SiC regions 10a is larger than one dimension of the plurality of second SiC regions 10b. One dimension of the plurality of first SiC regions 10a can be, for example, a length along any direction, or for example, a diameter. One dimension of the plurality of second SiC regions 10b can, for example, be a length along any direction, or for example, a diameter. It is also possible to substantially set two or more peaks in the distribution of the dimensions of the plurality of SiC regions 10p. Thus, smaller SiC regions are located between larger SiC regions. This reduces the gap between SiC regions (the length of the SiC inter-region 10q). The average size (average diameter) of the plurality of first SiC regions 10a is, for example, 1 μm or more and 10 μm or less. The average size (average diameter) of the plurality of second SiC regions 10b is, for example, 0.1 μm or more and less than 1 μm.

[0041] The substrate 10s includes multiple SiC regions 10p and inter-SiC regions 10q, thereby reducing the gaps between SiC cells. The substrate 10s also includes multiple SiC regions 10p and inter-SiC regions 10q, thereby reducing the surface roughness of the substrate 10s. For example, a substantially flat surface is easily obtained.

[0042] The first layer 11 contains SiC. The first layer 11 contains nitrogen at a first layer concentration. The first layer 11 contains nitrogen, thereby functioning as an n-type semiconductor layer. Nitrogen functions, for example, as an n-type impurity.

[0043] The first intermediate layer 61 contains SiC. The nitrogen concentration in the first intermediate layer 61 is higher than a first concentration. For example, the first layer 11 is a low-nitrogen-concentration SiC layer. For example, the first intermediate layer 61 is a high-nitrogen-concentration SiC layer.

[0044] For example, the first intermediate layer 61 comprises a single crystal of SiC. For example, the first intermediate layer 61 is a hexagonal single crystal layer of SiC. The first layer 11 comprises a single crystal of SiC. The first layer 11 is a single crystal layer of SiC. The first layer 11 functions as at least part of the functional layer of a semiconductor device, for example.

[0045] The thickness of the substrate 10s is sufficiently thicker than the thickness of the crystal layer 10L. The crystal layer 10L is supported by the thick substrate 10s.

[0046] For example, during the processing of a first layer 11, etc., disposed on a substrate 10s to form a semiconductor device, heat treatment is performed. There is a difference in the coefficient of thermal expansion between the substrate 10s and the first layer 11. Due to this difference in coefficient of thermal expansion, stress is generated in the substrate 10s and the crystal layer 10L. As mentioned above, the substrate 10s is sufficiently thicker than the crystal layer 10L. Therefore, when the first intermediate layer 61 is not disposed between the substrate 10s and the first layer 11, the generated stress is applied to the crystal layer 10L, making it prone to damage. For example, in the crystal layer 10L, dislocations increase, and the crystal quality of the crystal layer 10L decreases. Consequently, it is difficult to obtain the desired characteristics.

[0047] In this embodiment, a first intermediate layer 61 is provided between the substrate 10s and the first layer 11. The nitrogen concentration in the first intermediate layer 61 is higher than that in the first layer 11. The lattice length of the first intermediate layer 61, which has a higher nitrogen concentration, is shorter than that of the first layer 11, which has a lower nitrogen concentration. Stress is generated in the crystalline layer 10L based on the difference in lattice length. The direction of the stress based on the difference in lattice length is opposite to the direction of the stress caused by the difference in the coefficients of thermal expansion between the substrate 10s and the crystalline layer 10L. The stress caused by the difference in the coefficients of thermal expansion can be reduced by utilizing the stress based on the difference in lattice length. As a result, dislocations are suppressed, and a crystalline layer 10L with high crystal quality can be obtained. For example, a first layer 11 with good characteristics can be obtained. According to this embodiment, a wafer with improved characteristics can be provided.

[0048] It can also be like Figure 1 (a) shows the intermediate region 11B. The intermediate region 11B is disposed between the first intermediate layer 61 and the first layer 11. The nitrogen concentration in the intermediate region 11B is between the nitrogen concentration in the first intermediate layer 61 (first intermediate layer concentration) and the nitrogen concentration in the first layer 11 (first layer concentration). The intermediate region 11B is, for example, a migration layer. The intermediate region 11B is thinner than both the first intermediate layer 61 and the first layer 11. Therefore, the effect of the intermediate region 11B on stress can be substantially ignored.

[0049] For example, the concentration of the first intermediate layer is preferably five times or more than the concentration of the first layer. This allows the crystalline layer 10L to effectively generate stress based on the difference in lattice length. This effectively suppresses the stress caused by the aforementioned coefficient of thermal expansion. The concentration of the first intermediate layer can be 50,000 times or less than the concentration of the first layer. For example, when the concentration of the first layer becomes too low, it is difficult to obtain good electrical characteristics in a semiconductor device manufactured from a wafer.

[0050] The nitrogen concentration in the first layer 11 (first layer concentration) is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 2×10 17 cm -3The concentration of the first layer is 1×10⁻⁶. 15 cm -3 Therefore, good electrical properties are easily obtained, for example, in semiconductor devices manufactured from wafers. The first layer concentration is 2 × 10⁻⁶. 17 cm -3 This makes it easier to generate appropriate stress in the crystalline layer 10L, which includes the first layer 11 and the first intermediate layer 61.

[0051] The nitrogen concentration in the first intermediate layer 61 (first intermediate layer concentration) is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 5×10 19 cm -3 The concentration of the first intermediate layer is 1×10⁻⁶. 18 cm -3 This facilitates the generation of appropriate stress in the crystalline layer 10L. When the nitrogen concentration in the first intermediate layer 61 becomes too high, for example, the crystal quality in the first intermediate layer 61 tends to decrease. The concentration of the first intermediate layer is 5 × 10⁻⁶. 19 cm -3 This allows for the maintenance of high crystal quality.

[0052] like Figure 1 As shown in (a), the thickness (length) of the first layer 11 along a first direction (Z-axis direction) from the first intermediate layer 61 toward the first layer 11 is defined as the first thickness t1. The thickness (length) of the first intermediate layer 61 along the first direction is defined as the second thickness t2. In this embodiment, the first thickness t1 is preferably 0.2 times or more and 2 times or less than the second thickness t2. For example, the first thickness t1 is not significantly different from the second thickness t2. Thus, it is easy to utilize the difference in nitrogen concentration to appropriately generate the desired stress in the crystalline layer 10L.

[0053] In this embodiment, the first thickness t1 is preferably 10 μm or more and 80 μm or less. This facilitates the acquisition of good semiconductor properties.

[0054] In this embodiment, the second thickness t2 is preferably 10 μm or more and 80 μm or less. This effectively suppresses warping. More preferably, the second thickness t2 is 20 μm or more and 30 μm or less.

[0055] The substrate 10s has a third thickness t3 along a first direction (Z-axis direction). The crystalline layer 10L has a thickness t0 along the first direction (Z-axis direction). The thickness t0 substantially corresponds to the sum of the first thickness t1 and the second thickness t2. The third thickness t3 is, for example, more than four times the thickness t0. Thus, the substrate 10s does not deform substantially, and warping is suppressed. The third thickness t3 may also be, for example, more than five times the thickness t0. The third thickness t3 may also be, for example, more than ten times the thickness t0. The third thickness t3 may be, for example, less than 50 times the thickness t0. For example, when the thickness of the crystalline layer 10L becomes too thick, internal stresses such as thermal deformation are easily generated in the substrate 10s, causing warping.

[0056] The third thickness t3 is preferably 300 μm or more and 800 μm or less. This allows for good processing in the manufacturing method of semiconductor devices.

[0057] like Figure 1 As shown in (a), the first layer 11 has a (11-21) surface 11F. In the notation “(11-21)” in the specification, the “-” symbol corresponds to the “horizontal bar” of the number written after the “-”. The notation “(11-21)” follows the notation of Miller index.

[0058] The angle between plane 11F (11-21) in the first layer 11 and the X-Y plane is defined as angle θ1. Angle θ1 corresponds to the bias angle. The X-Y plane is a plane perpendicular to the direction (the first direction, Z-axis direction) from the first intermediate layer 61 toward the first layer 11. In this embodiment, angle θ1 can be less than 4.5 degrees. Due to the bias, good crystallinity is easily obtained in the crystalline layer 10L. For example, when angle θ1 exceeds 4.5 degrees, basal plane dislocations (BPDs) can easily enter the crystalline layer epitaxially grown on the crystalline layer 10L.

[0059] In some embodiments, for example, the base-plane dislocation density in the first intermediate layer 61 can be higher than that in the first layer 11. This allows for more effective stress mitigation in the first intermediate layer 61. The lower base-plane dislocation density in the first layer 11 facilitates the acquisition of good electrical properties, for example, in semiconductor devices derived from wafers.

[0060] The basal dislocation density in the first intermediate layer 61 is, for example, 8 × 10⁻⁶. 1 cm -2 Above and 1×10 3 cm -2 The dislocation density at the basal surface in the first intermediate layer 61 is 8 × 10⁻⁶. 1 cm -2This allows for the effective mitigation of stress, for example, when the basal dislocation density in the first intermediate layer 61 exceeds 1 × 10⁻⁶. 3 cm -2 At this time, for example, the basal dislocation density in the first layer 11 tends to be high. The basal dislocation density in the first intermediate layer 61 can also be, for example, 1.5 × 10⁻⁶. 2 cm -2 above.

[0061] The basal dislocation density in the first layer 11 is preferably, for example, 1 cm⁻¹. -2 Therefore, for example, good electrical characteristics can be easily obtained in semiconductor devices derived from wafers.

[0062] For example, in the first layer 11, the basal dislocation is transformed into a through-edge dislocation. For example, the bias angle (the aforementioned angle θ1) is 4.5 degrees or less, thereby achieving a high transformation efficiency to the through-edge dislocation. Good electrical characteristics can be obtained in the semiconductor device.

[0063] The following describes simulation results of an example of stress generated by the crystalline layer 10L. In the simulation model, the crystalline layer 10L is not fixed to the substrate 10s. In this model, the lattice length varies according to the difference in nitrogen concentration, resulting in stress between the first layer 11 and the first intermediate layer 61. In this model where the crystalline layer 10L is not fixed to the substrate 10s, the crystalline layer 10L deforms (warps) due to the stress caused by the difference in nitrogen concentration. The curvature of this deformation corresponds to the generated stress. Hereinafter, the curvature parameter is used as a parameter to represent the stress generated by the crystalline layer 10L.

[0064] Figure 2 This is a graph illustrating the characteristics of a wafer.

[0065] Figure 2 The horizontal axis represents the nitrogen concentration C1 in the first intermediate layer 61. The vertical axis represents the curvature parameter Pm1. As described above, the curvature parameter Pm1 corresponds to the stress generated in the crystal layer 10L when it is not fixed to the substrate 10s. A high curvature parameter Pm1 indicates a high stress. Figure 2 In the example, the nitrogen concentration in the first layer 11 (first layer concentration) is 5 × 10⁻⁶. 15 cm -3 The first thickness t1 of the first layer 11 is the same as the second thickness t2 of the first intermediate layer 61.

[0066] like Figure 2 As shown, when the nitrogen concentration C1 (first intermediate layer concentration) in the first intermediate layer 61 increases, the curvature parameter Pm1 increases. When the concentration C1 is approximately 1 × 10⁻⁶, the curvature parameter Pm1 increases. 17 cm -3In the following regions, the curvature parameter Pm1 increases slightly, but remains essentially unchanged. When the concentration C1 exceeds 1×10⁻⁶... 17 cm -3 At this time, the curvature parameter Pm1 increased significantly. At a concentration C1 of 1×10⁻⁶, the curvature parameter Pm1 increased significantly. 18 cm -3 At the above values, the curvature parameter Pm1 increases sharply.

[0067] In this embodiment, the concentration of the first intermediate layer is preferably 1×10⁻⁶. 18 cm -3 In conclusion, a high curvature parameter Pm1 can be obtained. Stress based on the nitrogen concentration difference can be effectively obtained. Therefore, the decrease in crystal quality of the crystalline layer 10L caused by changes in the coefficient of thermal expansion can be effectively suppressed.

[0068] Figure 3 (a) and Figure 3 (b) is a graph illustrating the characteristics of a wafer.

[0069] These figures illustrate simulation results of the curvature parameter Pm1 corresponding to the stress when the first thickness t1 of the first layer 11 and the second thickness t2 of the first intermediate layer 61 are changed. In this case, the crystalline layer 10L is also not fixed to the substrate 10s in the simulation model. In this example, the nitrogen concentration in the first layer 11 (first layer concentration) is 5 × 10⁻⁶. 15 cm -3 The nitrogen concentration C1 (first intermediate layer concentration) in the first intermediate layer 61 is 5 × 10⁻⁶. 18 cm -3 The horizontal axis of these graphs represents the second thickness t2 of the first intermediate layer 61. The vertical axis of these graphs represents the curvature parameter Pm1. Figure 3 (a) The first thickness t1 corresponding to the first layer 11 is 6μm to 30μm. Figure 3 (b) The first thickness t1 corresponding to the first layer 11 is 30 μm to 100 μm. The first thickness t1 of the first layer 11 varies in the range of 10 μm to 100 μm. The second thickness t2 of the first intermediate layer 61 varies in the range of 10 μm to 120 μm.

[0070] like Figure 3 (a) and Figure 3 As shown in (b), generally speaking, a high curvature parameter Pm1 can be obtained when the first thickness t1 of the first layer 11 is thin and the second thickness t2 of the first intermediate layer 61 is thin. Figure 3 As shown in (b), when the first thickness t1 is 30 μm to 120 μm, the curvature parameter Pm1 exhibits a peak when the second thickness t2 is changed. When the first thickness t1 becomes thinner, the second thickness t2, where the curvature parameter Pm1 peaks, also becomes thinner. Figure 3 As shown in (a), under the characteristics of a first thickness t1 of 6 μm to 20 μm, the curvature parameter Pm1 does not exhibit a peak. When from Figure 3 (b) By analogy, it is assumed that when the first thickness t1 is 6μm to 20μm, the curvature parameter Pm1 becomes the second thickness t2 of the peak and is less than 10μm.

[0071] Figure 4 (a) and Figure 4 (b) is a graph illustrating the characteristics of a wafer.

[0072] Regarding Figure 3 (a) and Figure 3 (b) The simulation results are illustrated by changing the axes in these figures. Figure 4 (a) and Figure 4 (b) The horizontal axis is the first thickness t1 of the first layer 11. The vertical axis of these graphs is the curvature parameter Pm1. Figure 4 (a) The second thickness t2 corresponding to the first intermediate layer 61 is 10 μm to 40 μm. Figure 4 (b) The characteristic of the second thickness t2 corresponding to the first intermediate layer 61 being 40 μm to 180 μm.

[0073] like Figure 4 (a) and Figure 4 As shown in (b), generally speaking, a high curvature parameter Pm1 can be obtained when the first thickness t1 of the first layer 11 is thin and the second thickness t2 of the first intermediate layer 61 is thin. Figure 4 As shown in (a) and (b), when the second thickness t2 is 20 μm to 180 μm, the curvature parameter Pm1 exhibits a peak when the first thickness t1 is changed. When the first thickness t1 is thinned, the second thickness t2, where the curvature parameter Pm1 peaks, also becomes thinner. Figure 4 As shown in (a), under the characteristics of a second thickness t2 of 10 μm, the curvature parameter Pm1 does not exhibit a peak. When from Figure 4 (b) By analogy, it is assumed that when the second thickness t2 is 10 μm, the curvature parameter Pm1 becomes the first thickness t1 below 10 μm of the peak.

[0074] Thus, in the combination of the first thickness t1 and the second thickness t2, there exists a condition where the curvature parameter Pm1 becomes the peak (highest).

[0075] Figure 5 (a) and Figure 5 (b) is a graph illustrating the characteristics of a wafer.

[0076] Figure 5(a) illustrates the variation of the highest value of the curvature parameter Pm1 when the first thickness t1 is fixed in various combinations of the first thickness t1 of the first layer 11 and the second thickness t2 of the first intermediate layer 61. Figure 5 (a) The horizontal axis is the first thickness t1 of the first layer 11. The vertical axis is the highest value Pm2 of the curvature parameter Pm1.

[0077] like Figure 5 As shown in (a), when the first thickness t1 is greater than 80 μm, the highest value of the curvature parameter Pm1, Pm2, is low. When the first thickness t1 is less than 80 μm, the highest value of the curvature parameter Pm1, Pm2, is high. When the first thickness t1 is less than 80 μm, a high curvature parameter Pm1 can be obtained. When the first thickness t1 is less than 80 μm, the highest value Pm2 increases sharply as the first thickness t1 decreases. Figure 5 As shown in (a), the maximum value decreases when the first thickness t1 is less than 10 μm.

[0078] In one embodiment, the first thickness t1 is preferably 80 μm or less. This allows for a high curvature parameter Pm1 (maximum value Pm2). In another embodiment, the first thickness t1 is preferably 10 μm or more. This facilitates obtaining a high maximum value Pm2.

[0079] Figure 5 (b) Examples illustrate the variation of the highest value of the curvature parameter Pm1 obtained when the second thickness t2 is fixed in various combinations of the first thickness t1 of the first layer 11 and the second thickness t2 of the first intermediate layer 61. Figure 5 (b) The horizontal axis is the second thickness t2 of the first intermediate layer 61. The vertical axis is the highest value Pm2 of the curvature parameter Pm1.

[0080] like Figure 5 As shown in (b), when the second thickness t2 is greater than 80 μm, the maximum value of the curvature parameter Pm1, Pm2, is low. When the second thickness t2 is less than 80 μm, the maximum value of the curvature parameter Pm1, Pm2, is high. When the second thickness t2 is less than 80 μm, a high curvature parameter Pm1 can be obtained. When the second thickness t2 is less than 80 μm, the maximum value Pm2 increases sharply as the first thickness t1 decreases. Figure 5 As shown in (b), the maximum value decreases when the first thickness t1 is less than 10 μm.

[0081] In this embodiment, the second thickness t2 is preferably 80 μm or less. This allows for a high curvature parameter Pm1 (maximum value Pm2). In this embodiment, the second thickness t2 is preferably 10 μm or more. This facilitates obtaining a high maximum value Pm2. The second thickness t2 can also be 20 μm or more. This facilitates obtaining a stable high maximum value Pm2.

[0082] Figure 6 This is a graph illustrating the characteristics of a wafer.

[0083] Figure 6 The horizontal axis represents the thickness ratio RR1. The thickness ratio RR1 is the ratio of the first thickness t1 to the second thickness t2. Figure 6 The vertical axis is the curvature parameter Pm1.

[0084] like Figure 6 As shown, when the first thickness t1 is 30 μm or more and 80 μm or less, the curvature parameter Pm1 exhibits a peak when the thickness ratio RR1 changes. For various thickness combinations, a higher curvature parameter Pm1 is preferred.

[0085] For example, in the range where the first thickness t1 is 30 μm or more and 80 μm or less, the thickness ratio RR1 for which the curvature parameter Pm1 becomes a peak is 0.4 or more and 0.75 or less. A high curvature parameter Pm1 (peak) can be obtained in the range where the thickness ratio RR1 is 0.4 or more and 0.75 or less. A certain degree of high curvature parameter Pm1 can also be obtained in thickness ratios RR1 that are either lower or higher than the thickness ratio RR1 for which the curvature parameter Pm1 becomes a peak.

[0086] For example, the range up to half the value of the peak of the curvature parameter Pm1 is defined as the "range of high curvature parameter Pm1". The ratio RR1 of at least this "range of high curvature parameter Pm1" is approximately 0.2 to 2 when the first thickness t1 is 30 μm or more and 80 μm or less. A high curvature parameter Pm1 can be obtained with such a thickness ratio RR1.

[0087] On the other hand, when the first thickness t1 is 20 μm, Figure 6 In the illustrated simulation results, the curvature parameter Pm1 does not exhibit a peak. With a first thickness t1 of 20 μm, the curvature parameter Pm1 decreases monotonically as the ratio RR1 increases. With a first thickness t1 of 20 μm, the value of the curvature parameter Pm1 is sufficiently high for any thickness ratio RR1. Therefore, with a first thickness t1 of 20 μm, a high curvature parameter Pm1 can be obtained even in the range where the ratio RR1 is above 0.2 and below 2.

[0088] In this embodiment, the thickness ratio RR1 is preferably 0.2 or more and 2 or less. That is, the first thickness t1 of the first layer 11 along the first direction (Z-axis direction) is preferably 0.2 times or more and 2 times or less than the second thickness t2 of the first intermediate layer 61 along the first direction. As a result, a high curvature parameter Pm1 can be obtained. This allows the crystalline layer 10L to generate a large stress corresponding to the high curvature parameter Pm1.

[0089] like Figure 6 As shown, the curvature parameter Pm1 can be 10m. -1 The above considers the case where the curvature parameter Pm1 becomes too high, resulting in excessive stress due to the difference in nitrogen concentration. This excessive stress exceeds the stress caused by the difference in thermal expansion coefficients between the substrate 10s and the crystalline layer 10L. In this case, it is assumed that defects will occur in the crystalline layer 10L due to the stress caused by the difference in nitrogen concentration. However, the situation where the stress caused by the difference in nitrogen concentration significantly exceeds the absolute value of the stress caused by the difference in thermal expansion coefficients is practically unrealistic. Therefore, it can be considered that a high curvature parameter Pm1 can be used within practical limits to mitigate the stress caused by the difference in thermal expansion coefficients.

[0090] like Figure 1 (b) As shown, in this embodiment, the substrate 10s may include a plurality of SiC inter-regions 10q. The average length L1 of the plurality of SiC inter-regions 10q is preferably 0.3 μm or less. The length L1 corresponds to the length of the SiC inter-region 10q along a direction perpendicular to the first direction (Z-axis direction). The length L1 may be, for example, the length along any direction in the X-Y plane (e.g., the X-axis direction). The length L1 may, for example, correspond to the distance between the plurality of SiC regions 10p.

[0091] The length L1 is long enough to correspond to a large gap between multiple SiC regions 10p. When the average length L1 exceeds 0.3 μm, the surface roughness of the substrate 10s becomes excessive. In this case, the adhesion between the substrate 10s and the crystalline layer 10L decreases, and for example, the crystalline layer 10L can easily detach from the substrate 10s due to high-temperature processing, etc. An average length L1 of 0.3 μm or less can suppress detachment. An average length L1 of 0.3 μm or less can reduce the surface roughness of the substrate 10s.

[0092] In this embodiment, the SiC inter-region 10q contains Si. For example, the gaps between multiple SiC regions 10p are filled with Si. This suppresses the formation of voids between the multiple SiC regions 10p. When voids are formed, liquids or gases can easily enter them during the manufacturing process of semiconductor devices using wafers, hindering desired processing. The SiC inter-region 10q contains Si, thereby suppressing voids. As a result, the manufacturing of semiconductor devices using wafers can be carried out stably.

[0093] Figure 7 (a) and Figure 7 (b) is a schematic cross-sectional view illustrating the first embodiment of the wafer.

[0094] Figure 7 (b) is Figure 7 (a) is a magnified view of a portion thereof.

[0095] like Figure 7 As shown in (a), the wafer 211 of the embodiment includes a substrate 10s, a first layer 11, a first intermediate layer 61, and a second intermediate layer 62. In wafer 211, the structure except for the second intermediate layer 62 can be the same as that of wafer 210.

[0096] A second intermediate layer 62 is disposed between the substrate 10s and the first intermediate layer 61. The second intermediate layer 62 contains SiC. The nitrogen concentration in the second intermediate layer 62 is higher than the nitrogen concentration in the first intermediate layer 61. Therefore, in the crystalline layer 10L, stress based on the difference in nitrogen concentration can be increased more stably. This also allows for more stable mitigation of stress caused by the difference in thermal expansion coefficients. Higher quality crystalline layer 10L is thus easily obtained.

[0097] The second intermediate layer 62 is, for example, an incomplete SiC layer with a high nitrogen concentration. The nitrogen concentration in the second intermediate layer 62 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 3×10 20 cm -3 The thickness of the second intermediate layer 62 (the fourth thickness t4) is, for example, 0.5 μm or more and 3 μm or less.

[0098] In the substrate 10s of the embodiment, at least a portion of the plurality of SiC regions 10p is preferably the α phase. As a result, phase changes are less likely to occur during heat treatment at high temperatures (e.g., 1600°C or higher).

[0099] The following describes an example of a wafer manufacturing method according to an embodiment.

[0100] (Second Implementation)

[0101] The second embodiment relates to a method for manufacturing wafers.

[0102] Figure 8 (a)~ Figure 8 (c) and Figure 9 (a)~ Figure 9 (c) is a schematic cross-sectional view illustrating a wafer manufacturing method according to the second embodiment.

[0103] like Figure 8 As shown in (a), a first intermediate layer substrate 61s is prepared. The first intermediate layer substrate 61s is a first intermediate layer 61 containing SiC. The first intermediate layer substrate 61s contains SiC. The nitrogen concentration in the first intermediate layer substrate 61s is 3 × 10⁻⁶. 18 cm -3 The above. The basal dislocation density in the first intermediate layer matrix 61s is, for example, 1.5 × 10⁻⁶. 2 cm-2 The first intermediate layer substrate 61s is, for example, a SiC single-crystal substrate.

[0104] like Figure 8 As shown in (b), a first layer 11 is formed on a first intermediate layer substrate 61s. The first layer 11 contains SiC. The first layer 11 can be formed, for example, by epitaxial growth. The first layer 11 contains nitrogen at a first layer concentration. As already explained, the nitrogen concentration in the first intermediate layer substrate 61s (e.g., the first intermediate layer concentration) is higher than the first layer concentration.

[0105] like Figure 8 As shown in (b), in one example, an intermediate region 11B may also be provided between the first intermediate layer substrate 61s and the first layer 11.

[0106] like Figure 8 As shown in (c), the first intermediate layer substrate 61s includes a first layered region 61a and a second layered region 61b. The first layered region 61a is located between the second layered region 61b and the first layer 11. The first layered region 61a is the region close to the first layer 11. The second layered region 61b is the region far from the first layer 11. Figure 8 (c) In the illustrated state, the boundaries of these layered regions may be indistinct.

[0107] like Figure 8 As shown in (c), after the first layer 11 is formed, a third layered region 61c is formed between the first layered region 61a and the second layered region 61b. For example, an electromagnetic wave 68 is irradiated onto the first intermediate layer substrate 61s. The electromagnetic wave 68 is, for example, a laser. The wavelength (center wavelength) of the laser is, for example, 390 nm or more and 1200 nm or less. The power of the laser is, for example, 30 mW or more and 30 W or less.

[0108] like Figure 8 As shown in (c), a modified region 61d is formed in the third layered region 61c by irradiation with electromagnetic wave 68 (laser). The mechanical strength of the modified region 61d is locally reduced. Thus, the formation of the third layered region 61c may include irradiating the first intermediate layer substrate 61s with electromagnetic wave 68. This forms the third layered region 61c. The third layered region 61c is, for example, a fractured layer. The mechanical strength of the third layered region 61c is lower than that of the other regions (the first layered region 61a and the second layered region 61b). For example, the crystallinity in the third layered region 61c is lower than that in the first layered region 61a. The crystallinity in the third layered region 61c is lower than that in the second layered region 61b. Information related to the crystallinity in these layers can be obtained, for example, by X-ray diffraction analysis. For example, in the case of low crystallinity, the intensity peaks obtained by X-ray diffraction are broadened.

[0109] When a third layered region 61c (e.g., a modified region 61d) is formed by irradiation with electromagnetic wave 68 (laser), the portion between the first layered region 61a and the second layered region 61b where the modified region 61d is formed detaches. As a result, the second layered region 61b is removed (see reference). Figure 9 (a) Thus, the removal of the second layered region 61b includes the formation of a third layered region 61c between the first layered region 61a and the second layered region 61b after the formation of the first layer 11.

[0110] like Figure 9 As shown in (b), the processed body in which the second layered region 61b is removed is positioned opposite the substrate 10s. For example, the remaining first layered region 61a is positioned opposite the substrate 10s.

[0111] like Figure 9 As shown in (c), the remaining first layered region 61a is bonded to the substrate 10s. The substrate 10s has the structure described with respect to the first embodiment. Figure 1 As illustrated in (b), the substrate 10s includes a plurality of SiC regions 10p containing SiC and an inter-SiC region 10q disposed between the plurality of SiC regions 10p and containing Si. The remaining first layered region 61a becomes the first intermediate layer 61.

[0112] In the bonding process, direct bonding may be performed, for example. Direct bonding is performed under reduced pressure (less than 1 atmosphere). The surface of the first layered region 61a may also be planarized before bonding. The surface of the substrate 10s may also be planarized before bonding. Ar or similar substances may be introduced into the space between the first layered region 61a and the substrate 10s during bonding. This performs sputter cleaning. During bonding, Si may also be deposited on at least one surface of the first layered region 61a and the substrate 10s.

[0113] Through the above processing, the wafer 210 of the embodiment can be obtained.

[0114] As described below, sometimes a third layered region 61c remains after the removal of the second layered region 61b. The third layered region 61c may also be removed before bonding. Furthermore, a portion (surface portion) of the remaining first layered region 61a may be removed as described above to achieve planarization. Thus, the wafer manufacturing method of the embodiment may also include removing a portion of the remaining first layered region 61b after the removal of the second layered region 61b and before bonding to achieve planarization.

[0115] It can also be like Figure 9(a) shows that after the first layer 11 is formed, a support member 65 (e.g., a support substrate) is fixed to the first layer 11. The support member 65 may contain graphite, for example. For example, a resin layer 66 is provided between the first layer 11 and the support member 65. The support member 65 is fixed to the first layer 11 by the resin layer 66. After the second layered region 61b is removed, the first layer 11 and the first layered region 61a are supported by the support member 65. The support member 65 can be fixed to the first layer 11 according to any technically possible process.

[0116] Figure 10 (a)~ Figure 10 (c) is a schematic cross-sectional view illustrating a wafer manufacturing method according to the second embodiment.

[0117] like Figure 10 As shown in (a), regarding Figure 8 (c) After the described process, a third layered region 61c remains after the removal of the second layered region 61b. The third layered region 61c is removed. Removal can be performed, for example, by CMP (Chemical Mechanical Polishing).

[0118] like Figure 10 As shown in (b), for example, ions 69 are implanted into a portion (surface portion) of the first layered region 61a exposed by the removal of the third layered region 61c. The ions 69 contain nitrogen. Thus, a region containing nitrogen at a high concentration (second intermediate layer 62) is formed. The remaining first layered region 61a becomes the first intermediate layer 61.

[0119] like Figure 10 As shown in (c), the second intermediate layer 62 is positioned opposite the substrate 10s. The second intermediate layer 62 and the substrate 10s are then bonded. The above-described direct bonding is performed during the bonding process. Thus, for example, the wafer 211 of the embodiment can be obtained.

[0120] Figure 11 (a)~ Figure 11 (c) and Figure 12 (a)~ Figure 12 (c) is a schematic cross-sectional view illustrating a wafer manufacturing method according to the second embodiment.

[0121] like Figure 11 (a) and Figure 11 (b) shows the removal of the third layered region 61c to form the second intermediate layer 62.

[0122] like Figure 11(c) shows the prepared substrate 10s. The substrate 10s includes a first substrate portion 10sa and a second substrate portion 10sb. The first substrate portion 10sa includes a plurality of SiC regions 10p and SiC inter-regions 10q (refer to...). Figure 1 (b)). The first substrate portion 10sa is, for example, a sintered substrate comprising Si and Si-C. The second substrate portion 10sb is disposed on the surface of the first substrate portion 10sa. The second substrate portion 10sb includes, for example, polycrystalline SiC. The second substrate portion 10sb can be formed, for example, by CVD (Chemical Vapor Deposition). The thickness of the second substrate portion 10sb is, for example, 0.1 μm or more and 300 μm or less.

[0123] like Figure 11 As shown in (c), the second substrate portion 10sb of the substrate 10s is positioned opposite the second intermediate layer 62.

[0124] like Figure 12 As shown in (a), the second intermediate layer 62 is bonded to the substrate 10s (second substrate portion 10sb). The aforementioned direct bonding is performed during bonding. This allows, for example, the wafer of the embodiment to be obtained. During and after bonding, at least a portion of the second substrate portion 10sb is located between at least a portion of the first substrate portion 10sa and at least a portion of the first layer 11. In this example, during and after bonding, a portion of the second substrate portion 10sb is located between the first substrate portion 10sa and the second intermediate layer 62.

[0125] like Figure 12 As shown in (b), the resin layer 66 and the support member 65 are removed. For example, the resin layer 66 is removed, thereby causing the support member 65 to detach. The resin layer 66 and the support member 65 can also be removed by grinding or the like.

[0126] It can also be like Figure 12 As shown in (c), at least a portion of the first substrate portion 10sa is removed, making the first substrate portion 10sa thinner. At this time, the corresponding portion of the second substrate portion 10sb is also removed. Alternatively, the entire first substrate portion 10sa can be removed. Alternatively, the second substrate portion 10sb can also be removed. In this way, the substrate 10s can also be thinned. Alternatively, the entire substrate 10s can be removed.

[0127] The nitrogen concentration in the second substrate portion 10sb can also be higher than the nitrogen concentration in the first intermediate layer 61 (the first intermediate layer concentration). In this case, at least a portion of the remaining second substrate portion 10sb can become at least a portion of the second intermediate layer 62. In this case, it can also be omitted. Figure 11(b) Formation of the second intermediate layer 62 as illustrated (e.g., introduction of ions 69).

[0128] Figure 13 This is a graph illustrating the characteristics related to the manufacturing method of the semiconductor device in the embodiment.

[0129] As already explained, the surface of the substrate 10s can be planarized before bonding with the substrate 10s. Planarization can be performed, for example, by grinding with abrasive particles. Figure 13 The horizontal axis represents the diameter d1 of the abrasive grains. The vertical axis represents the surface roughness Ra of the substrate after grinding with abrasive grains for 10 seconds.

[0130] like Figure 13 As shown, in the range where the diameter d1 is 5 μm or more, the surface roughness Ra decreases as the diameter d1 decreases. When the diameter d1 is less than 5 μm, the surface roughness Ra increases. This is because when the diameter d1 is too small, it is easier to remove Si from the SiC inter-region 10q contained in the substrate 10s. As a result, it is assumed that multiple SiC regions 10p remain, and the surface roughness Ra of the substrate 10s increases. When the diameter d1 is 5 μm or more, the removal of Si from the SiC inter-region 10q by abrasive particles is suppressed. Therefore, in the range where the diameter d1 is 5 μm or more, a smaller diameter d1 is preferable. This allows for the obtaining of a flat substrate 10s.

[0131] The diameter d1 of the sand grains is preferably greater than the length L1 of the multiple SiC inter-region 10q (refer to...). Figure 1 (b)) The average size is large. When the diameter d1 is too small, selective removal of Si from multiple SiC inter-region 10q tends to increase the surface roughness Ra. In practical terms, the diameter d1 is preferably the length L1 of the multiple SiC inter-region 10q (refer to...). Figure 1 (b)) more than twice the average.

[0132] The wafer manufacturing method of the embodiment may also include grinding the substrate 10s with multiple abrasive grains before bonding. Preferably, the average diameter d1 of the multiple abrasive grains is 0.5 μm or more. This allows for the production of a flat substrate 10s.

[0133] (Third Implementation)

[0134] The third embodiment relates to a method for manufacturing a semiconductor device.

[0135] Figure 14 (a)~ Figure 14 (d) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the third embodiment.

[0136] like Figure 14As shown in (a), a wafer (wafer 210 or 211, etc.) of the first embodiment is prepared. The substrate 10s may also include a first substrate portion 10sa and a second substrate portion 10sb (see Figure 10sb). Figure 12 (c) etc. The wafer may also include a second intermediate layer 62 in addition to the first intermediate layer 61 and the first layer 11.

[0137] like Figure 14 As shown in (b), a first element 69B is introduced into at least a portion of the first layer 11. The first element 69B includes at least any one selected from the group including B, Al, and Ga. The first element 69B functions as a p-type impurity. A second semiconductor region 12 containing the first element 69B is formed.

[0138] like Figure 14 As shown in (c), after the first element 69B is introduced, heat treatment is performed. The heat treatment is based on a temperature of 1600°C or higher. This activates the first element 69B. The second semiconductor region 12 then functions as a p-type semiconductor.

[0139] In this embodiment, the wafer includes a substrate 10s, a first intermediate layer 61, and a first layer 11. Consequently, stress is alleviated during high-temperature heat treatment, and warpage is suppressed. This enables the stable manufacture of semiconductor devices using the wafer.

[0140] like Figure 14 As shown in (d), after heat treatment, at least a portion of the substrate 10s is removed. This thins the substrate 10s. Alternatively, the entire substrate 10s may be removed. A first electrode 51 is formed on the surface exposed by the removal of at least a portion of the substrate 10s. In this example, the first electrode 51 is connected to the second intermediate layer 62. The first electrode 51 may also be connected to the first intermediate layer 61. This allows the semiconductor device 110A to be obtained.

[0141] Figure 15 (a)~ Figure 15 (c) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the third embodiment.

[0142] like Figure 15 As shown in (a), during heat treatment (refer to) Figure 12(c) After that, a portion 10sp of the substrate 10s is removed, leaving another portion 10sq of the substrate 10s. The removal of the portion 10sp of the substrate 10s may be performed, for example, by etching using a mask material. Etching may also include, for example, REI (Reactive Ion Etching). Etching may include wet etching. In this example, the substrate 10s may include a first substrate portion 10sa and a second substrate portion 10sb. During etching, the first intermediate layer 61 (or the second intermediate layer 62) may function as an etch barrier layer.

[0143] like Figure 15 As shown in (b), a first electrode 51 is formed on the surface exposed by removing a portion 10sp of the substrate 10s. The first electrode 51 is in contact with the exposed first intermediate layer 61 (or second intermediate layer 62). The first electrode 51 is in contact with another portion 10sq of the substrate 10s. The first electrode 51 is electrically connected to the first intermediate layer 61 (or second intermediate layer 62). Thus, the semiconductor device 110B can be obtained.

[0144] In this example, the first electrode 51 is electrically connected to the first intermediate layer 61 (or the second intermediate layer 62) without passing through all the substrates 10s. This reduces the resistance (on-resistance) in the semiconductor device 110B.

[0145] The semiconductor device 110B includes another portion 10sq of the substrate 10s. As a result, high mechanical strength can be obtained in the semiconductor device 110B.

[0146] It can also be like Figure 15 As shown in (c), a conductive material 51M is formed in the residual space of the recess formed by removing a portion 10sp of the substrate 10s. The conductive material 51M is embedded in the recess. The depth of the recess is reduced. Higher mechanical strength can be obtained.

[0147] (Fourth Implementation)

[0148] The fourth embodiment relates to a semiconductor device.

[0149] Figure 16 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0150] like Figure 16 As shown, the semiconductor device 110C of the embodiment includes a first intermediate layer 61, a first layer 11, and a first electrode 51. The first intermediate layer 61 is a substrate 10s (see reference). Figure 1The first intermediate layer is formed after at least a portion of (a) etc. is removed. Electrode 51 is electrically connected to the first intermediate layer 61 obtained by removing at least a portion of the substrate 10s of the wafer in the first embodiment. In the semiconductor device 110C of the embodiment, stress is mitigated. In the first layer 11 of the semiconductor device 110C, for example, a low dislocation density can be obtained. A semiconductor device with good characteristics can be obtained.

[0151] Figure 17 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0152] like Figure 17 As shown, the semiconductor device 110D of this embodiment includes a second intermediate layer 62, a first intermediate layer 61, a first layer 11, and a first electrode 51. The first intermediate layer 61 is electrically connected to the second intermediate layer 62. In this example, the first electrode 51 is electrically connected to the first intermediate layer 61 after at least a portion of the substrate 10s has been removed, via the second intermediate layer 62. In the semiconductor device 110D, stress is mitigated. In the first layer 11, for example, a low dislocation density can be obtained. A semiconductor device with good characteristics can be obtained.

[0153] Figure 18 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0154] like Figure 18 As shown, the semiconductor device 110 of the embodiment includes a first intermediate layer 61, a first layer 11, a second semiconductor region 12, a third semiconductor region 13, a first electrode 51, a second electrode 52, a third electrode 53, and a first insulating member 81. The first layer 11 corresponds to the first semiconductor region of type n containing nitrogen. The second semiconductor region corresponds to the semiconductor region of type p containing the first element 69B. The third semiconductor region 13 corresponds to the semiconductor region of type n containing nitrogen.

[0155] The first layer 11 includes a first region 11a and a second region 11b. A second direction from the second region 11b to the first region 11a intersects the first direction (Z-axis direction). The second direction is along the X-axis direction. The position of the second region 11b in the second direction is different from the position of the first region 11a in the second direction.

[0156] At least a portion of the third semiconductor region 13 is disposed in the first direction (Z-axis direction) between the second partial region 11b and a portion of the third electrode 53. A portion 12p of the second semiconductor region 12 is disposed in the first direction (Z-axis direction) between the second partial region 11b and the third semiconductor region 13. In the second direction (X-axis direction), another portion 12q of the second semiconductor region 12 is disposed between the third semiconductor region 13 and a portion of the first partial region 11a. The other portion 12q of the second semiconductor region 12 is located in the first direction (Z-axis direction) between the second partial region 11b and a portion of the third electrode 53.

[0157] In the first direction (Z-axis direction), the first insulating member 81 is located between the third semiconductor region 13 and the third electrode 53, between another portion 12q of the second semiconductor region 12 and the third electrode 53, and between the first portion region 11a and the third electrode 53. The second electrode 52 is electrically connected to the third semiconductor region 13.

[0158] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 can, for example, be a potential referenced to the potential of the second electrode 52. The first electrode 51 functions, for example, as a drain electrode. The second electrode 52 functions, for example, as a source electrode. The third electrode 53 functions, for example, as a gate electrode. The first insulating member 81 functions as a gate insulating film. The semiconductor device 110 is, for example, a transistor. The semiconductor device 110 is, for example, a MOS transistor.

[0159] In this example, a fourth semiconductor region 14 and a second insulating member 82 are provided. The fourth semiconductor region 14 includes a first element 69B. The fourth semiconductor region 14 corresponds to a p-type semiconductor region containing the first element 69B. In the second direction (X-axis direction), a third semiconductor region 13 is located between the fourth semiconductor region 14 and another portion 12q of the second semiconductor region 12. The second electrode 52 is electrically connected to the fourth semiconductor region 14.

[0160] The second insulating member 82 is disposed between the third electrode 53 and the second electrode 52. The second insulating member 82 electrically insulates the third electrode 53 from the second electrode 52.

[0161] Figure 19 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0162] like Figure 19As shown, the semiconductor device 111 of the embodiment includes a first intermediate layer 61, a first layer 11, a second semiconductor region 12, a third semiconductor region 13, a fifth semiconductor region 15, a first electrode 51, a second electrode 52, a third electrode 53, and a first insulating member 81. In the semiconductor device 111, the first layer 11, the second semiconductor region 12, the third semiconductor region 13, the first electrode 51, the second electrode 52, the third electrode 53, and the first insulating member 81 may be the same as these components in the semiconductor device 110.

[0163] The fifth semiconductor region 15 is disposed between the first electrode 51 and the first intermediate layer 61. The fifth semiconductor region 15 corresponds to a p-type semiconductor region containing the first element 69B. The semiconductor device 111 is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0164] Figure 20 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0165] like Figure 20 As shown, the semiconductor device 112 of this embodiment includes a first intermediate layer 61, a first layer 11, a first electrode 51, and a second electrode 52. The first intermediate layer 61 is located between the first electrode 51 and the second electrode 52. The first layer 11 is located between the first intermediate layer 61 and the second electrode 52. The first electrode 51 is electrically connected to the first intermediate layer 61. The second electrode 52 is electrically connected to the first layer 11. The semiconductor device 112 is, for example, a Schottky diode.

[0166] It can also be like Figure 20 The semiconductor device 112 shown includes a terminal region 12A. The terminal region 12A is disposed between the end of the first layer 11 and the second electrode 52. The terminal region 12A includes, for example, a first element 69B. The terminal region 12A corresponds, for example, to a p-type semiconductor region.

[0167] Figure 21 This is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

[0168] like Figure 21As shown, the semiconductor device 113 of this embodiment includes a first intermediate layer 61, a first layer 11, a second semiconductor region 12, a first electrode 51, and a second electrode 52. The first intermediate layer 61 is located between the first electrode 51 and the second electrode 52. The first layer 11 is located between the first intermediate layer 61 and the second electrode 52. The second semiconductor region 12 is located between the first layer 11 and the second electrode 52. The first electrode 51 is electrically connected to the first intermediate layer 61. The second electrode 52 is electrically connected to the second semiconductor region 12. The semiconductor device 113 is, for example, a pn diode. The semiconductor device 113 may also include a terminal region 12A.

[0169] In semiconductor devices 110-113, stress is mitigated, resulting in stable characteristics. For example, high electrical characteristics can be obtained.

[0170] In semiconductor devices 110-113, the first electrode 51 comprises, for example, Ni or Ni silicide. In semiconductor devices 110, 111, and 113, the second electrode 52 comprises, for example, at least one selected from the group including Ni and Ti. In semiconductor device 112, the second electrode 52 comprises, for example, at least one selected from the group including Ni and Ti / Al. In semiconductor devices 110-113, the third electrode 53 comprises, for example, at least one selected from the group including Ni and amorphous Si.

[0171] Implementation methods may include, for example, the following technical solutions.

[0172] (Technical Solution 1)

[0173] A wafer having:

[0174] A substrate comprising a plurality of SiC regions containing SiC and an inter-SiC region disposed between the plurality of SiC regions and containing Si; and

[0175] A crystalline layer comprising a first layer containing SiC and a first intermediate layer containing SiC disposed in a first direction between the substrate and the first layer, the first layer containing nitrogen at a first layer concentration, and the first intermediate layer containing nitrogen at a first intermediate layer concentration higher than the first concentration.

[0176] (Technical Solution 2)

[0177] According to the wafer described in technical solution 1, wherein,

[0178] The concentration of the first intermediate layer is more than 5 times that of the first layer.

[0179] (Technical Solution 3)

[0180] According to the wafer described in technical solution 1 or 2, wherein,

[0181] The concentration of the first layer is 1×10 15 cm -3 Above and 2×10 17 cm -3 the following,

[0182] The concentration of the first intermediate layer is 1×10 18 cm -3 Above and 5×10 19 cm -3 the following.

[0183] (Technical Solution 4)

[0184] The wafer described in any one of technical solutions 1 to 3, wherein,

[0185] The first thickness of the first layer along the first direction is more than 0.2 times and less than 2 times the second thickness of the first intermediate layer along the first direction.

[0186] (Technical Solution 5)

[0187] The wafer described in any one of technical solutions 1 to 4, wherein,

[0188] The thickness of the first layer along the first direction is more than 10 μm and less than 80 μm.

[0189] (Technical Solution 6)

[0190] The wafer described in any one of technical solutions 1 to 5, wherein,

[0191] The thickness of the first intermediate layer along the first direction is more than 20 μm and less than 80 μm.

[0192] (Technical Solution 7)

[0193] The wafer described in any one of technical solutions 1 to 6, wherein,

[0194] The third thickness of the substrate along the first direction is more than four times the thickness of the crystalline layer along the first direction.

[0195] (Technical Solution 8)

[0196] The wafer described in any one of technical solutions 1 to 7, wherein,

[0197] The substrate includes multiple SiC inter-regions.

[0198] The average length of the plurality of SiC inter-regions along the direction perpendicular to the first direction is less than 0.3 μm.

[0199] (Technical Solution 9)

[0200] The wafer described in any one of technical solutions 1 to 8, wherein,

[0201] The angle between the (11-21) plane in the first layer and the plane perpendicular to the direction from the first intermediate layer to the first layer is less than 4.5 degrees.

[0202] (Technical Solution 10)

[0203] The wafer described in any one of technical solutions 1 to 9, wherein,

[0204] The basal dislocation density in the first intermediate layer is higher than that in the first layer.

[0205] (Technical Solution 11)

[0206] The wafer described according to any one of technical solutions 1 to 10, wherein,

[0207] The wafer also includes a second intermediate layer disposed between the substrate and the first intermediate layer and comprising SiC.

[0208] The nitrogen concentration in the second intermediate layer is higher than that in the first intermediate layer.

[0209] (Technical Solution 12)

[0210] A semiconductor device comprising:

[0211] The first electrode is electrically connected to the first intermediate layer obtained by removing at least a portion of the substrate of the wafer described in any one of technical solutions 1 to 11.

[0212] The first intermediate layer after at least a portion of the substrate has been removed; and

[0213] The first layer.

[0214] (Technical Solution 13)

[0215] A method for manufacturing a wafer, wherein,

[0216] A first layer containing SiC is formed on a first intermediate layer substrate, which serves as a first intermediate layer containing SiC. The first layer contains nitrogen at a first layer concentration. The first intermediate layer substrate has a higher nitrogen concentration than the first layer concentration. The first intermediate layer substrate includes a first layered region and a second layered region, with the first layered region located between the second layered region and the first layer.

[0217] Remove the second layered region.

[0218] The remaining first layered region is bonded to a substrate, the substrate comprising a plurality of SiC regions containing SiC and an inter-SiC region disposed between the plurality of SiC regions and containing Si.

[0219] (Technical Solution 14)

[0220] According to the wafer manufacturing method described in technical solution 13, wherein,

[0221] The removal of the second layered region includes, after the formation of the first layer, forming a third layered region between the first layered region and the second layered region.

[0222] The crystallinity in the third layered region is lower than that in the first layered region and lower than that in the second layered region.

[0223] (Technical Solution 15)

[0224] According to the wafer manufacturing method described in technical solution 14, wherein,

[0225] The formation of the third layered region includes irradiating the first intermediate layer substrate with electromagnetic waves to form the third layered region.

[0226] (Technical Solution 16)

[0227] The wafer manufacturing method described in any one of technical solutions 13 to 15 further comprises:

[0228] After the removal of the second layered region and before the joining, a portion of the remaining first layered region is removed to achieve flattening.

[0229] (Technical Solution 17)

[0230] The wafer manufacturing method according to any one of technical solutions 13 to 16 further comprises:

[0231] Prior to the bonding of the substrate, the substrate is polished using multiple abrasive grains.

[0232] The average diameter of the plurality of sand grains is greater than 0.5 μm.

[0233] (Technical Solution 18)

[0234] According to any one of technical solutions 13 to 17, the wafer manufacturing method is described, wherein,

[0235] The substrate includes a first substrate portion and a second substrate portion.

[0236] The first substrate portion includes a plurality of SiC regions containing SiC and an inter-SiC region disposed between the plurality of SiC regions and containing Si.

[0237] The second substrate portion is disposed on the surface of the first substrate portion.

[0238] The second substrate portion comprises polycrystalline SiC.

[0239] The nitrogen concentration in the second substrate portion is higher than that in the first intermediate layer.

[0240] (Technical Solution 19)

[0241] A method for manufacturing a semiconductor device, wherein,

[0242] The first element is incorporated into at least a portion of the first layer of the wafer described in any one of technical solutions 1 to 11, wherein the first element includes at least any one selected from the group comprising B, Al, and Ga.

[0243] After the importation, a heat treatment at a temperature above 1600°C is performed.

[0244] (Technical Solution 20)

[0245] According to the semiconductor device manufacturing method described in technical solution 19, wherein,

[0246] After the heat treatment, at least a portion of the substrate is removed.

[0247] A first electrode is formed on the surface exposed by the removal of at least a portion of the substrate.

[0248] (Technical Solution 21)

[0249] According to the semiconductor device manufacturing method described in technical solution 19, wherein,

[0250] After the heat treatment, a portion of the substrate is removed, leaving the other portion of the substrate.

[0251] A first electrode is formed on the surface exposed by the removal of the portion of the substrate.

[0252] According to the embodiments, it is possible to provide a wafer with improved characteristics, a semiconductor device, a method for manufacturing a wafer, and a method for manufacturing a semiconductor device.

[0253] In this application specification, "the state of electrical connection" includes the state in which multiple conductors are physically connected and current flows between these multiple conductors. "The state of electrical connection" also includes the state in which other conductors are inserted between multiple conductors and current flows between these multiple conductors.

[0254] In this application specification, "perpendicular" and "parallel" include not only strict perpendicularity and strict parallelism, but also deviations in the manufacturing process, as long as they are substantially perpendicular and substantially parallel.

[0255] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, any specific structure of the various elements included in a wafer or semiconductor device, such as the substrate, intermediate layer, first layer, semiconductor region, electrode, and insulating member, is included within the scope of the present invention, provided that a person skilled in the art can appropriately select from the known range to similarly implement the present invention and obtain the same effects.

[0256] Furthermore, any example combining two or more elements of each specific example within a technically possible range is also included within the scope of this invention, provided it contains the spirit of the invention.

[0257] In addition, as embodiments of the present invention, all wafer, semiconductor device, wafer manufacturing method, and semiconductor device manufacturing method implemented by those skilled in the art based on the above-described wafer, semiconductor device, wafer manufacturing method, and semiconductor device manufacturing method with appropriate design modifications are also within the scope of the present invention as long as they contain the spirit of the present invention.

[0258] In addition, it should be understood that within the scope of the ideas of this invention, various modifications and alterations can be conceived by those skilled in the art, and these modifications and alterations also fall within the scope of this invention.

[0259] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as set forth in the patent claims and its equivalents.

Claims

1. A wafer comprising: A substrate comprising a plurality of SiC regions containing SiC and an inter-SiC region disposed between the plurality of SiC regions and containing Si; and A crystalline layer comprising a first layer containing SiC and a first intermediate layer containing SiC disposed in a first direction between the substrate and the first layer, wherein the first layer contains nitrogen at a first layer concentration, and the first intermediate layer contains nitrogen at a higher concentration than the first layer concentration. The angle between the (11-21) plane in the first layer and the plane perpendicular to the direction from the first intermediate layer toward the first layer is less than 4.5 degrees.

2. The wafer according to claim 1, wherein, The concentration of the first intermediate layer is more than 5 times that of the first layer.

3. The wafer according to claim 1 or 2, wherein, The concentration of the first layer is 1×10 15 cm -3 Above and 2×10 17 cm -3 the following, The concentration of the first intermediate layer is 1×10 18 cm -3 Above and 5×10 19 cm -3 the following.

4. The wafer according to claim 1 or 2, wherein, The first thickness of the first layer along the first direction is more than 0.2 times and less than 2 times the second thickness of the first intermediate layer along the first direction.

5. The wafer according to claim 1 or 2, wherein, The thickness of the first layer along the first direction is more than 10 μm and less than 80 μm.

6. The wafer according to claim 1 or 2, wherein, The thickness of the first intermediate layer along the first direction is more than 20 μm and less than 80 μm.

7. The wafer according to claim 1 or 2, wherein, The third thickness of the substrate along the first direction is more than four times the thickness of the crystalline layer along the first direction.

8. The wafer according to claim 1 or 2, wherein, The substrate includes multiple SiC inter-regions. The average length of the plurality of SiC inter-regions along the direction perpendicular to the first direction is less than 0.3 μm.

9. The wafer according to claim 1 or 2, wherein, The basal dislocation density in the first intermediate layer is higher than that in the first layer.

10. The wafer according to claim 1 or 2, wherein, The wafer also includes a second intermediate layer disposed between the substrate and the first intermediate layer and comprising SiC. The nitrogen concentration in the second intermediate layer is higher than that in the first intermediate layer.

11. A semiconductor device comprising: The first electrode is electrically connected to the first intermediate layer obtained by removing at least a portion of the substrate of the wafer according to any one of claims 1 to 10. The first intermediate layer after at least a portion of the substrate has been removed; and The first layer.

12. A method for manufacturing a wafer, wherein, A first layer containing SiC is formed on a first intermediate layer substrate, which serves as a first intermediate layer containing SiC. The first layer contains nitrogen at a first layer concentration. The first intermediate layer substrate has a higher nitrogen concentration than the first layer concentration. The first intermediate layer substrate includes a first layered region and a second layered region, with the first layered region located between the second layered region and the first layer. Remove the second layered region. The remaining first layered region is bonded to a substrate, the substrate comprising a plurality of SiC regions containing SiC and an inter-SiC region disposed between the plurality of SiC regions and containing Si.

13. The wafer manufacturing method according to claim 12, wherein, The removal of the second layered region also occurs after the formation of the first layer, forming a third layered region between the first and second layered regions. The crystallinity in the third layered region is lower than that in the first layered region and lower than that in the second layered region.

14. The wafer manufacturing method according to claim 13, wherein, The formation of the third layered region includes irradiating the first intermediate layer substrate with electromagnetic waves to form the third layered region.

15. The method for manufacturing a wafer according to any one of claims 12 to 14, further comprising: After the removal of the second layered region and before the joining, a portion of the remaining first layered region is removed to achieve flattening.

16. The method for manufacturing a wafer according to any one of claims 12 to 14, further comprising: Prior to the bonding of the substrate, the substrate is ground using a plurality of abrasive grains, the average diameter of which is 0.5 μm or more.

17. The method for manufacturing a wafer according to any one of claims 12 to 14, wherein, The substrate includes a first substrate portion and a second substrate portion. The first substrate portion includes a plurality of SiC regions containing SiC and an inter-SiC region disposed between the plurality of SiC regions and containing Si. The second substrate portion is disposed on the surface of the first substrate portion. The second substrate portion comprises polycrystalline SiC. The nitrogen concentration in the second substrate portion is higher than that in the first intermediate layer.

18. A method for manufacturing a semiconductor device, wherein, Introducing a first element into at least a portion of the first layer of the wafer according to any one of claims 1 to 10, the first element comprising at least any one selected from the group comprising B, Al, and Ga. After the importation, a heat treatment at a temperature above 1600°C is performed.

19. The method of manufacturing a semiconductor device according to claim 18, wherein, After the heat treatment, at least a portion of the substrate is removed. A first electrode is formed on the surface exposed by the removal of at least a portion of the substrate.

20. The method of manufacturing a semiconductor device according to claim 19, wherein, After the heat treatment, a portion of the substrate is removed, leaving the other portion of the substrate. A first electrode is formed on the surface exposed by the removal of the portion of the substrate.

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